c10fa9a2b737904fbff795b6904be2e142558edf
3 from UserDict
import UserDict
5 from wire_def
import generic_io
# special case
6 from wire_def
import muxwire
# special case
10 """ pin interface declaration.
11 * name is the name of the pin
12 * ready, enabled and io all create a (* .... *) prefix
13 * action changes it to an "in" if true
16 def __init__(self
, name
,
24 self
.enabled
= enabled
27 self
.bitspec
= bitspec
if bitspec
else '1'
29 def ifacefmt(self
, fmtfn
=None):
33 status
.append('always_ready')
35 status
.append('always_enabled')
37 status
.append('result="io"')
40 res
+= ','.join(status
)
45 name
= fmtfn(self
.name
)
49 res
+= ' (Bit#(%s) in)' % self
.bitspec
51 res
+= " Bit#(%s) " % self
.bitspec
56 def ifacedef(self
, fmtoutfn
=None, fmtinfn
=None, fmtdecfn
=None):
59 fmtname
= fmtinfn(self
.name
)
61 res
+= fmtdecfn(self
.name
)
62 res
+= '(Bit#(%s) in);\n' % self
.bitspec
63 res
+= ' %s<=in;\n' % fmtname
66 fmtname
= fmtoutfn(self
.name
)
67 res
+= "%s=%s;" % (self
.name
, fmtname
)
70 def wirefmt(self
, fmtoutfn
=None, fmtinfn
=None, fmtdecfn
=None):
71 res
= ' Wire#(Bit#(%s)) ' % self
.bitspec
73 res
+= '%s' % fmtinfn(self
.name
)
75 res
+= '%s' % fmtoutfn(self
.name
)
76 res
+= "<-mkDWire(0);"
80 class Interface(object):
81 """ create an interface from a list of pinspecs.
82 each pinspec is a dictionary, see Pin class arguments
85 def __init__(self
, ifacename
, pinspecs
):
86 self
.ifacename
= ifacename
88 self
.pinspecs
= pinspecs
92 if p
.get('outen') is True: # special case, generate 3 pins
94 for psuffix
in ['out', 'outen', 'in']:
95 _p
['name'] = "%s_%s" % (self
.pname(p
['name']), psuffix
)
96 _p
['action'] = psuffix
!= 'in'
97 self
.pins
.append(Pin(**_p
))
99 _p
['name'] = self
.pname(p
['name'])
100 self
.pins
.append(Pin(**_p
))
102 def getifacetype(self
, name
):
103 for p
in self
.pinspecs
:
104 fname
= "%s_%s" % (self
.ifacename
, p
['name'])
105 print "search", self
.ifacename
, name
, fname
114 def pname(self
, name
):
115 return '%s{0}_%s' % (self
.ifacename
, name
)
117 def wirefmt(self
, *args
):
118 res
= '\n'.join(map(self
.wirefmtpin
, self
.pins
)).format(*args
)
120 for p
in self
.pinspecs
:
121 name
= self
.pname(p
['name']).format(*args
)
122 res
+= " GenericIOType %s_io = GenericIOType{\n" % name
124 if p
.get('outen') is True:
125 outname
= self
.ifacefmtoutfn(name
)
126 params
.append('outputval:%s_out,' % outname
)
127 params
.append('output_en:%s_outen,' % outname
)
128 params
.append('input_en:~%s_outen,' % outname
)
129 elif p
.get('action'):
130 outname
= self
.ifacefmtoutfn(name
)
131 params
.append('outputval:%s,' % outname
)
132 params
.append('output_en:1,')
133 params
.append('input_en:0,')
135 params
.append('outputval:0,')
136 params
.append('output_en:0,')
137 params
.append('input_en:1,')
138 params
+= ['pullup_en:0,', 'pulldown_en:0,',
139 'pushpull_en:0,', 'drivestrength:0,',
142 res
+= ' %s\n' % param
146 def ifacefmt(self
, *args
):
147 res
= '\n'.join(map(self
.ifacefmtdecpin
, self
.pins
)).format(*args
)
150 def ifacefmtdecfn(self
, name
):
153 def ifacefmtdecfn2(self
, name
):
156 def ifacefmtoutfn(self
, name
):
159 def ifacefmtinfn(self
, name
):
162 def wirefmtpin(self
, pin
):
163 return pin
.wirefmt(self
.ifacefmtoutfn
, self
.ifacefmtinfn
,
166 def ifacefmtdecpin(self
, pin
):
167 return pin
.ifacefmt(self
.ifacefmtdecfn
)
169 def ifacefmtpin(self
, pin
):
170 return pin
.ifacedef(self
.ifacefmtoutfn
, self
.ifacefmtinfn
,
173 def ifacedef(self
, *args
):
174 res
= '\n'.join(map(self
.ifacefmtpin
, self
.pins
))
175 res
= res
.format(*args
)
176 return '\n' + res
+ '\n'
179 class MuxInterface(Interface
):
181 def wirefmt(self
, *args
):
182 return muxwire
.format(*args
)
185 class IOInterface(Interface
):
187 def ifacefmtoutfn(self
, name
):
188 """ for now strip off io{0}_ part """
189 return "cell{0}_mux_out.%s" % name
[6:]
191 def ifacefmtinfn(self
, name
):
192 return "cell{0}_mux_in"
194 def wirefmt(self
, *args
):
195 return generic_io
.format(*args
)
198 class Interfaces(UserDict
):
199 """ contains a list of interface definitions
202 def __init__(self
, pth
):
205 UserDict
.__init
__(self
, {})
206 ift
= 'interfaces.txt'
208 ift
= os
.path
.join(pth
, ift
)
209 with
open(ift
, 'r') as ifile
:
210 for ln
in ifile
.readlines():
215 spec
= self
.read_spec(pth
, name
)
216 self
.ifaceadd(name
, count
, Interface(name
, spec
))
218 def getifacetype(self
, fname
):
219 # finds the interface type, e.g sd_d0 returns "inout"
220 for iface
in self
.values():
221 typ
= iface
.getifacetype(fname
)
226 def ifaceadd(self
, name
, count
, iface
, at
=None):
228 at
= len(self
.ifacecount
)
229 self
.ifacecount
.insert(at
, (name
, count
))
232 def read_spec(self
, pth
, name
):
234 fname
= '%s.txt' % name
236 ift
= os
.path
.join(pth
, fname
)
237 with
open(ift
, 'r') as sfile
:
238 for ln
in sfile
.readlines():
244 elif ln
[1] == 'inout':
249 def ifacedef(self
, f
, *args
):
250 for (name
, count
) in self
.ifacecount
:
251 for i
in range(count
):
252 f
.write(self
.data
[name
].ifacedef(i
))
254 def ifacefmt(self
, f
, *args
):
256 // interface declaration between %s-{0} and pinmux'''
257 for (name
, count
) in self
.ifacecount
:
258 for i
in range(count
):
259 c
= comment
% name
.upper()
261 f
.write(self
.data
[name
].ifacefmt(i
))
263 def wirefmt(self
, f
, *args
):
264 comment
= '\n // following wires capture signals ' \
265 'to IO CELL if %s-{0} is\n' \
267 for (name
, count
) in self
.ifacecount
:
268 for i
in range(count
):
271 f
.write(self
.data
[name
].wirefmt(i
))
274 # ========= Interface declarations ================ #
276 mux_interface
= MuxInterface('cell', [{'name': 'mux', 'ready': False,
278 'bitspec': '{1}', 'action': True}])
280 io_interface
= IOInterface('io',
281 [{'name': 'outputval', 'enabled': False},
282 {'name': 'output_en', 'enabled': False},
283 {'name': 'input_en', 'enabled': False},
284 {'name': 'pullup_en', 'enabled': False},
285 {'name': 'pulldown_en', 'enabled': False},
286 {'name': 'drivestrength', 'enabled': False},
287 {'name': 'pushpull_en', 'enabled': False},
288 {'name': 'opendrain_en', 'enabled': False},
289 {'name': 'inputval', 'action': True, 'io': True},
292 # == Peripheral Interface definitions == #
293 # these are the interface of the peripherals to the pin mux
294 # Outputs from the peripherals will be inputs to the pinmux
295 # module. Hence the change in direction for most pins
297 # ======================================= #
300 if __name__
== '__main__':
302 uartinterface_decl
= Interface('uart',
304 {'name': 'tx', 'action': True},
307 twiinterface_decl
= Interface('twi',
308 [{'name': 'sda', 'outen': True},
309 {'name': 'scl', 'outen': True},
312 def _pinmunge(p
, sep
, repl
, dedupe
=True):
313 """ munges the text so it's easier to compare.
314 splits by separator, strips out blanks, re-joins.
319 p
= filter(lambda x
: x
, p
) # filter out blanks
323 """ munges the text so it's easier to compare.
325 # first join lines by semicolons, strip out returns
327 p
= map(lambda x
: x
.replace('\n', ''), p
)
329 # now split first by brackets, then spaces (deduping on spaces)
330 p
= _pinmunge(p
, "(", " ( ", False)
331 p
= _pinmunge(p
, ")", " ) ", False)
332 p
= _pinmunge(p
, " ", " ")
338 for p1
, p2
in zip(l1
, l2
):
344 ifaces
= Interfaces()
346 ifaceuart
= ifaces
['uart']
347 print ifaceuart
.ifacedef(0)
348 print uartinterface_decl
.ifacedef(0)
349 assert ifaceuart
.ifacedef(0) == uartinterface_decl
.ifacedef(0)
351 ifacetwi
= ifaces
['twi']
352 print ifacetwi
.ifacedef(0)
353 print twiinterface_decl
.ifacedef(0)
354 assert ifacetwi
.ifacedef(0) == twiinterface_decl
.ifacedef(0)