7 if isinstance(txt
, str):
12 line
= line
.split('\n')
17 res
.append(indent
+ line
)
24 def __init__(self
, name
):
27 def extifdecl(self
, name
, count
):
28 sname
= self
.get_iname(count
)
29 return "interface PeripheralSide%s %s;" % (name
.upper(), sname
)
31 def has_axi_master(self
):
37 def mk_dma_irq(self
, name
, count
):
38 if not self
.irq_name():
40 sname
= self
.get_iname(count
)
41 return "{0}_interrupt".format(sname
)
43 def mk_dma_rule(self
, name
, count
):
44 irqname
= self
.mk_dma_irq(name
, count
)
47 pirqname
= self
.irq_name().format(count
)
48 template
= " {0}_interrupt.send(\n" + \
49 " slow_peripherals.{1});"
50 return template
.format(irqname
, pirqname
)
52 def get_clock_reset(self
, name
, count
):
53 return "slow_clock,slow_reset"
55 def mk_dma_sync(self
, name
, count
):
56 irqname
= self
.mk_dma_irq(name
, count
)
59 sname
= self
.peripheral
.iname().format(count
)
60 template
= "SyncBitIfc#(Bit#(1)) {0} <-\n" + \
61 " <-mkSyncBitToCC({1});"
62 return template
.format(irqname
, self
.get_clock_reset(name
, count
))
64 def mk_dma_connect(self
, name
, count
):
65 irqname
= self
.mk_dma_irq(name
, count
)
68 return "{0}.read".format(irqname
)
70 def fastifdecl(self
, name
, count
):
73 def slowifdeclmux(self
, name
, count
):
79 def num_axi_regs32(self
):
85 def get_iname(self
, inum
):
86 return "{0}{1}".format(self
.name
, self
.mksuffix(self
.name
, inum
))
88 def axibase(self
, name
, ifacenum
):
90 return "%(name)s%(ifacenum)dBase" % locals()
92 def axiend(self
, name
, ifacenum
):
94 return "%(name)s%(ifacenum)dEnd" % locals()
96 def axi_reg_def(self
, start
, name
, ifacenum
):
98 offs
= self
.num_axi_regs32() * 4 * 16
101 end
= start
+ offs
- 1
102 bname
= self
.axibase(name
, ifacenum
)
103 bend
= self
.axiend(name
, ifacenum
)
104 comment
= "%d 32-bit regs" % self
.num_axi_regs32()
105 return (" `define %(bname)s 'h%(start)08X\n"
106 " `define %(bend)s 'h%(end)08X // %(comment)s" % locals(),
109 def axi_master_name(self
, name
, ifacenum
, typ
=''):
111 return "{0}{1}_master_num".format(name
, ifacenum
)
113 def axi_slave_name(self
, name
, ifacenum
, typ
=''):
115 return "{0}{1}_{2}slave_num".format(name
, ifacenum
, typ
)
117 def axi_master_idx(self
, idx
, name
, ifacenum
, typ
):
118 name
= self
.axi_master_name(name
, ifacenum
, typ
)
119 return ("typedef {0} {1};".format(idx
, name
), 1)
121 def axi_slave_idx(self
, idx
, name
, ifacenum
, typ
):
122 name
= self
.axi_slave_name(name
, ifacenum
, typ
)
123 return ("typedef {0} {1};".format(idx
, name
), 1)
125 def axi_fastaddr_map(self
, name
, ifacenum
):
126 return self
.axi_addr_map(name
, ifacenum
, 'fast')
128 def axi_addr_map(self
, name
, ifacenum
, typ
=""):
129 bname
= self
.axibase(name
, ifacenum
)
130 bend
= self
.axiend(name
, ifacenum
)
131 name
= self
.axi_slave_name(name
, ifacenum
, typ
)
133 if(addr>=`{0} && addr<=`{1})
134 return tuple2(True,fromInteger(valueOf({2})));
136 return template
.format(bname
, bend
, name
)
138 def _mk_pincon(self
, name
, count
, ptyp
):
139 # TODO: really should be using bsv.interface_decl.Interfaces
140 # pin-naming rules.... logic here is hard-coded to duplicate
141 # it (see Interface.__init__ outen)
143 for p
in self
.peripheral
.pinspecs
:
146 #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
147 n
= name
# "{0}{1}".format(self.name, self.mksuffix(name, count))
148 ret
.append("//%s %s" % (n
, str(p
)))
150 sname
= self
.get_iname(count
)
151 sname
= "{0}.{1}".format(sname
, pname
)
152 ps
= "slow_peripherals.%s" % sname
154 sname
= self
.peripheral
.iname().format(count
)
155 sname
= "{0}.{1}".format(sname
, pname
)
156 ps
= "pinmux.peripheral_side.%s" % sname
157 if typ
== 'out' or typ
== 'inout':
158 fname
= self
.pinname_out(pname
)
159 if not n
.startswith('gpio'): # XXX EURGH! horrible hack
160 n_
= "{0}{1}".format(n
, count
)
168 cn
= self
._mk
_actual
_connection
('out', name
,
170 pname
, ps_
, n_
, fname
)
174 fname
= self
.pinname_outen(pname
)
176 if isinstance(fname
, str):
177 fname
= "{0}.{1}".format(n_
, fname
)
178 fname
= self
.pinname_tweak(pname
, 'outen', fname
)
179 cn
= self
._mk
_actual
_connection
('outen', name
,
183 if typ
== 'in' or typ
== 'inout':
184 fname
= self
.pinname_in(pname
)
190 n_
= "{0}{1}".format(n
, count
)
191 n_
= '{0}.{1}'.format(n_
, fname
)
192 n_
= self
.ifname_tweak(pname
, 'in', n_
)
193 cn
= self
._mk
_actual
_connection
('in', name
,
195 pname
, ps_
, n_
, fname
)
197 return '\n'.join(ret
)
199 def _mk_actual_connection(self
, ctype
, name
, count
, typ
,
200 pname
, ps
, n
, fname
):
203 ret
.append("mkConnection({0},\n\t\t\t{1}.{2});"
204 .format(ps
, n
, fname
))
205 elif ctype
== 'outen':
206 ret
.append("mkConnection({0}_outen,\n\t\t\t{1});"
209 ck
= self
.get_clock_reset(name
, count
)
210 if ck
== PBase
.get_clock_reset(self
, name
, count
):
211 ret
.append("mkConnection({1},\n\t\t\t{0});".format(
214 n2
= "{0}{1}".format(name
, count
)
215 sync
= '{0}_{1}_sync'.format(n2
, pname
)
216 ret
.append("mkConnection({1}.put,\n\t\t\t{0});".format(
218 ret
.append("mkConnection({1},\n\t\t\t{0}.get);".format(
222 def mk_clk_con(self
, name
, count
):
224 ck
= self
.get_clock_reset(name
, count
)
225 if ck
== PBase
.get_clock_reset(self
, name
, count
):
227 spc
= "sp_clock, sp_reset"
229 Ifc_sync#({0}) {1}_sync <-mksyncconnection(
231 for p
in self
.peripheral
.pinspecs
:
235 if typ
== 'out' or typ
== 'inout':
236 if not n
.startswith('gpio'): # XXX EURGH! horrible hack
237 n_
= "{0}{1}".format(n
, count
)
240 ret
.append(template
.format("Bit#(1)", n_
, ck
, spc
))
241 if typ
== 'in' or typ
== 'inout':
242 #fname = self.pinname_in(pname)
243 n_
= "{0}{1}".format(n
, count
)
244 n_
= '{0}_{1}'.format(n_
, pname
)
245 #n_ = self.ifname_tweak(pname, 'in', n_)
246 ret
.append(template
.format("Bit#(1)", n_
, spc
, ck
))
247 return '\n'.join(ret
)
250 def mk_cellconn(self
, *args
):
253 def mkfast_peripheral(self
, size
=0):
256 def mkslow_peripheral(self
, size
=0):
259 def mksuffix(self
, name
, i
):
262 def __mk_connection(self
, con
, aname
, fabricname
):
263 txt
= "mkConnection ({2}.v_to_slaves\n" + \
264 " [fromInteger(valueOf({1}))],\n" + \
267 print "PBase __mk_connection", self
.name
, aname
270 return txt
.format(con
, aname
, fabricname
)
272 def __mk_master_connection(self
, con
, aname
):
273 txt
= "mkConnection (slow_fabric.v_to_slaves\n" + \
274 " [fromInteger(valueOf({1}))],\n" + \
277 print "PBase __mk_connection", self
.name
, aname
280 return txt
.format(con
, aname
)
282 def mk_connection(self
, count
, fabricname
, typ
, name
=None):
285 print "PBase mk_conn", self
.name
, count
286 aname
= self
.axi_slave_name(name
, count
, typ
)
287 #dname = self.mksuffix(name, count)
288 #dname = "{0}{1}".format(name, dname)
289 con
= self
._mk
_connection
(name
, count
).format(count
, aname
)
290 return self
.__mk
_connection
(con
, aname
, fabricname
)
292 def _mk_connection(self
, name
=None, count
=0):
295 def pinname_out(self
, pname
):
298 def pinname_in(self
, pname
):
301 def pinname_outen(self
, pname
):
304 def ifname_tweak(self
, pname
, typ
, txt
):
307 def pinname_tweak(self
, pname
, typ
, txt
):
313 def mk_plic(self
, inum
, irq_offs
):
315 print "mk_plic", self
.name
, inum
, irq_offs
316 niq
= self
.num_irqs()
318 return ('', irq_offs
)
319 name
= self
.get_iname(inum
)
320 res
.append("// PLIC rules for {0}".format(name
))
321 for idx
in range(niq
):
322 plic_obj
= self
.plic_object(name
, idx
)
323 print "plic_obj", name
, idx
, plic_obj
324 plic
= mkplic_rule
.format(name
, plic_obj
, irq_offs
)
326 irq_offs
+= 1 # increment to next irq
327 return ('\n'.join(res
), irq_offs
)
329 def mk_ext_ifacedef(self
, iname
, inum
):
332 def extfastifinstance(self
, name
, count
):
335 def _extifinstance(self
, name
, count
, suffix
, prefix
, samename
=False,
339 pname
= self
.get_iname(count
)
343 sname
= self
.peripheral
.iname().format(count
)
344 template
= "interface {0}{3} = {2}{1}{4};"
345 return template
.format(pname
, sname
, prefix
, suffix
, ifsuffix
)
347 def extifinstance2(self
, name
, count
):
350 def extifinstance(self
, name
, count
):
351 return self
._extifinstance
(name
, count
, "",
352 "pinmux.peripheral_side.")
356 rule rl_connect_{0}_to_plic_{2};
357 if({1} == 1'b1) begin
358 ff_gateway_queue[{2}].enq(1);
359 plic.ifc_external_irq[{2}].irq_frm_gateway(True);
364 axi_master_declarations
= """\
365 typedef 0 Dmem_master_num;
366 typedef 1 Imem_master_num;
368 typedef TAdd#(LastGen_master_num, `ifdef Debug 1 `else 0 `endif )
370 typedef TAdd#(Debug_master_num, `ifdef DMA 1 `else 0 `endif )
372 typedef TAdd#(DMA_master_num,1)
376 axi_fastslave_declarations
= """\
378 typedef TAdd#(LastGen_fastslave_num,1) Sdram_slave_num;
379 typedef TAdd#(Sdram_slave_num ,`ifdef SDRAM 1 `else 0 `endif )
381 typedef TAdd#(Sdram_cfg_slave_num,`ifdef BOOTROM 1 `else 0 `endif )
383 typedef TAdd#(BootRom_slave_num ,`ifdef Debug 1 `else 0 `endif )
385 typedef TAdd#(Debug_slave_num , `ifdef TCMemory 1 `else 0 `endif )
387 typedef TAdd#(TCM_slave_num ,`ifdef DMA 1 `else 0 `endif )
389 typedef TAdd#(Dma_slave_num ,1 ) SlowPeripheral_slave_num;
390 typedef TAdd#(SlowPeripheral_slave_num,`ifdef VME 1 `else 0 `endif )
392 typedef TAdd#(VME_slave_num,1) Num_Fast_Slaves;
395 axi_slave_declarations
= """\
396 typedef 0 SlowMaster;
398 typedef TAdd#(LastGen_slave_num,`ifdef CLINT 1 `else 0 `endif )
400 typedef TAdd#(CLINT_slave_num ,`ifdef PLIC 1 `else 0 `endif )
402 typedef TAdd#(Plic_slave_num ,`ifdef AXIEXP 1 `else 0 `endif )
404 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
407 pinmux_cellrule
= """\
408 rule connect_select_lines_pinmux;
414 class CallFn(object):
415 def __init__(self
, peripheral
, name
):
416 self
.peripheral
= peripheral
419 def __call__(self
, *args
):
420 #print "__call__", self.name, self.peripheral.slow, args
421 if not self
.peripheral
.slow
:
423 return getattr(self
.peripheral
.slow
, self
.name
)(*args
[1:])
426 class PeripheralIface(object):
427 def __init__(self
, ifacename
):
429 slow
= slowfactory
.getcls(ifacename
)
430 print "Iface", ifacename
, slow
432 self
.slow
= slow(ifacename
)
433 self
.slow
.peripheral
= self
434 for fname
in ['slowimport',
436 'extifinstance2', 'extifinstance', 'extifdecl',
437 'slowifdecl', 'slowifdeclmux',
440 'mk_dma_sync', 'mk_dma_connect', 'mk_dma_rule',
442 'mk_plic', 'mk_ext_ifacedef',
443 'mk_clk_con', 'mk_ext_ifacedef',
444 'mk_connection', 'mk_cellconn', '_mk_pincon']:
445 fn
= CallFn(self
, fname
)
446 setattr(self
, fname
, types
.MethodType(fn
, self
))
448 #print "PeripheralIface"
451 def mksuffix(self
, name
, i
):
452 if self
.slow
is None:
454 return self
.slow
.mksuffix(name
, i
)
456 def axi_reg_def(self
, start
, count
):
459 return self
.slow
.axi_reg_def(start
, self
.ifacename
, count
)
461 def axi_master_idx(self
, start
, count
, typ
):
462 if not self
.slow
or not self
.slow
.has_axi_master():
464 return self
.slow
.axi_master_idx(start
, self
.ifacename
, count
, typ
)
466 def axi_slave_idx(self
, start
, count
, typ
):
469 return self
.slow
.axi_slave_idx(start
, self
.ifacename
, count
, typ
)
471 def axi_fastaddr_map(self
, count
):
474 return self
.slow
.axi_fastaddr_map(self
.ifacename
, count
)
476 def axi_addr_map(self
, count
):
479 return self
.slow
.axi_addr_map(self
.ifacename
, count
)
482 class PeripheralInterfaces(object):
484 self
.fastbusmode
= False
486 def slowimport(self
, *args
):
488 for (name
, count
) in self
.ifacecount
:
489 #print "slowimport", name, self.data[name].slowimport
490 ret
.append(self
.data
[name
].slowimport())
491 return '\n'.join(li(list(filter(None, ret
)), 4))
493 def extfastifinstance(self
, *args
):
495 for (name
, count
) in self
.ifacecount
:
496 for i
in range(count
):
497 iname
= self
.data
[name
].iname().format(i
)
498 print "extfast", iname
, self
.is_on_fastbus(name
, i
)
499 if self
.is_on_fastbus(name
, i
):
501 ret
.append(self
.data
[name
].extfastifinstance(name
, i
))
502 return '\n'.join(li(list(filter(None, ret
)), 8))
504 def extifinstance2(self
, *args
):
506 for (name
, count
) in self
.ifacecount
:
507 for i
in range(count
):
508 iname
= self
.data
[name
].iname().format(i
)
509 ret
.append(self
.data
[name
].extifinstance2(name
, i
))
510 return '\n'.join(li(list(filter(None, ret
)), 8))
512 def extifinstance(self
, *args
):
514 for (name
, count
) in self
.ifacecount
:
515 for i
in range(count
):
516 iname
= self
.data
[name
].iname().format(i
)
517 if not self
.is_on_fastbus(name
, i
):
519 ret
.append(self
.data
[name
].extifinstance(name
, i
))
520 return '\n'.join(li(list(filter(None, ret
)), 8))
522 def extifdecl(self
, *args
):
524 for (name
, count
) in self
.ifacecount
:
525 for i
in range(count
):
526 if not self
.is_on_fastbus(name
, i
):
528 ret
.append(self
.data
[name
].extifdecl(name
, i
))
529 return '\n'.join(li(list(filter(None, ret
)), 8))
531 def slowifdeclmux(self
, *args
):
533 for (name
, count
) in self
.ifacecount
:
534 for i
in range(count
):
535 ret
.append(self
.data
[name
].slowifdeclmux(name
, i
))
536 return '\n'.join(li(list(filter(None, ret
)), 8))
538 def fastifdecl(self
, *args
):
540 for (name
, count
) in self
.ifacecount
:
541 for i
in range(count
):
542 print "fastifdecl", name
, i
, self
.is_on_fastbus(name
, i
)
543 if self
.is_on_fastbus(name
, i
):
545 ret
.append(self
.data
[name
].fastifdecl(name
, i
))
546 return '\n'.join(li(list(filter(None, ret
)), 4))
548 def slowifdecl(self
, *args
):
550 for (name
, count
) in self
.ifacecount
:
551 for i
in range(count
):
552 if self
.is_on_fastbus(name
, i
):
554 ret
.append(self
.data
[name
].slowifdecl().format(i
, name
))
555 return '\n'.join(list(filter(None, ret
)))
557 def axi_fastmem_def(self
, *args
):
558 return self
._axi
_reg
_def
(0x50000000, *args
)
560 def axi_reg_def(self
, *args
):
561 return self
._axi
_reg
_def
(0x00011100, *args
)
563 def _axi_reg_def(self
, start
, *args
):
565 for (name
, count
) in self
.ifacecount
:
566 for i
in range(count
):
567 if self
.is_on_fastbus(name
, i
):
569 x
= self
.data
[name
].axi_reg_def(start
, i
)
570 #print ("ifc", name, x)
574 return '\n'.join(list(filter(None, ret
)))
576 def _axi_num_idx(self
, start
, template
, typ
, idxtype
, *args
):
578 for (name
, count
) in self
.ifacecount
:
579 for i
in range(count
):
580 if self
.is_on_fastbus(name
, i
):
583 fn
= self
.data
[name
].axi_master_idx
585 fn
= self
.data
[name
].axi_slave_idx
586 (rdef
, offs
) = fn(start
, i
, idxtype
)
587 #print ("ifc", name, rdef, offs)
590 ret
.append("typedef %d LastGen_%s_num;" % (start
- 1, typ
))
591 decls
= '\n'.join(list(filter(None, ret
)))
592 return template
.format(decls
)
594 def axi_slave_idx(self
, *args
):
595 return self
._axi
_num
_idx
(0, axi_slave_declarations
, 'slave',
598 def axi_fastslave_idx(self
, *args
):
599 return self
._axi
_num
_idx
(0, axi_fastslave_declarations
, 'fastslave',
602 def axi_master_idx(self
, *args
):
603 return self
._axi
_num
_idx
(2, axi_master_declarations
, 'master',
606 def axi_fastslave_idx(self
, *args
):
607 return self
._axi
_num
_idx
(0, axi_fastslave_declarations
, 'fastslave',
610 def axi_fastaddr_map(self
, *args
):
612 for (name
, count
) in self
.ifacecount
:
613 for i
in range(count
):
614 if self
.is_on_fastbus(name
, i
):
616 ret
.append(self
.data
[name
].axi_fastaddr_map(i
))
617 return '\n'.join(li(list(filter(None, ret
)), 8))
619 def axi_addr_map(self
, *args
):
621 for (name
, count
) in self
.ifacecount
:
622 for i
in range(count
):
623 if self
.is_on_fastbus(name
, i
):
625 ret
.append(self
.data
[name
].axi_addr_map(i
))
626 return '\n'.join(li(list(filter(None, ret
)), 8))
628 def mkfast_peripheral(self
, *args
):
630 for (name
, count
) in self
.ifacecount
:
631 for i
in range(count
):
632 if self
.is_on_fastbus(name
, i
):
634 #print "mkfast", name, count
635 x
= self
.data
[name
].mkfast_peripheral()
637 suffix
= self
.data
[name
].mksuffix(name
, i
)
638 ret
.append(x
.format(suffix
))
639 return '\n'.join(li(list(filter(None, ret
)), 8))
641 def mkslow_peripheral(self
, *args
):
643 for (name
, count
) in self
.ifacecount
:
644 for i
in range(count
):
645 if self
.is_on_fastbus(name
, i
):
647 #print "mkslow", name, count
648 x
= self
.data
[name
].mkslow_peripheral()
650 suffix
= self
.data
[name
].mksuffix(name
, i
)
651 ret
.append(x
.format(suffix
))
652 return '\n'.join(li(list(filter(None, ret
)), 8))
654 def mk_fast_connection(self
, *args
):
656 for (name
, count
) in self
.ifacecount
:
657 for i
in range(count
):
658 if self
.is_on_fastbus(name
, i
):
660 txt
= self
.data
[name
].mk_connection(i
, "fabric", "fast")
663 print self
.data
[name
].mk_connection
665 return '\n'.join(li(list(filter(None, ret
)), 12))
667 def mk_connection(self
, *args
):
669 for (name
, count
) in self
.ifacecount
:
670 for i
in range(count
):
671 if self
.is_on_fastbus(name
, i
):
673 txt
= self
.data
[name
].mk_connection(i
, "slow_fabric", "")
676 print self
.data
[name
].mk_connection
678 return '\n'.join(li(list(filter(None, ret
)), 8))
680 def mk_cellconn(self
):
683 for (name
, count
) in self
.ifacecount
:
684 for i
in range(count
):
685 if self
.is_on_fastbus(name
, i
):
687 res
= self
.data
[name
].mk_cellconn(cellcount
, name
, i
)
690 (txt
, cellcount
) = res
692 ret
= li('\n'.join(list(filter(None, ret
))), 4)
693 return li(pinmux_cellrule
.format(ret
), 4)
696 return self
._mk
_pincon
("slow")
698 def mk_fast_pincon(self
):
699 return self
._mk
_pincon
("fast")
701 def _mk_pincon(self
, typ
):
703 for (name
, count
) in self
.ifacecount
:
704 for i
in range(count
):
705 if self
.is_on_fastbus(name
, i
):
707 txt
= self
.data
[name
]._mk
_pincon
(name
, i
, typ
)
709 return '\n'.join(li(list(filter(None, ret
)), 4))
711 def mk_dma_irq(self
):
719 for (name
, count
) in self
.ifacecount
:
721 for i
in range(count
):
722 if not self
.is_on_fastbus(name
, i
):
724 txt
= self
.data
[name
].mk_dma_sync(name
, i
)
728 txt
= self
.data
[name
].mk_dma_rule(name
, i
)
729 ifacerules
.append(txt
)
730 txt
= self
.data
[name
].mk_dma_connect(name
, i
)
732 ifacerules
= list(filter(None, ifacerules
))
734 txt
= "rule synchronize_%s_interrupts;" % name
737 rules
.append("endrule")
739 cnct
= list(filter(None, cnct
))
741 _cnct
= ["rule rl_connect_interrupt_to_DMA;",
742 " Bit #(%d) lv_interrupt_to_DMA={" % ct
]
745 cnct
= _cnct
+ [spc
+ spcsep
.join(cnct
)]
747 cnct
.append(" dma.interrupt_from_peripherals(\n" +
748 " lv_interrupt_to_DMA);")
749 cnct
.append("endrule;")
751 ret
= list(filter(None, sync
+ rules
+ cnct
))
753 return '\n'.join(ret
)
755 def num_dmachannels(self
):
756 return "`define NUM_DMACHANNELS {0}".format(self
.dma_count
)
758 def mk_ext_ifacedef(self
):
760 for (name
, count
) in self
.ifacecount
:
761 for i
in range(count
):
762 if self
.is_on_fastbus(name
, i
):
764 txt
= self
.data
[name
].mk_ext_ifacedef(name
, i
)
766 return '\n'.join(li(list(filter(None, ret
)), 8))
770 irq_offs
= 8 # XXX: DMA scovers 0-7?
771 for (name
, count
) in self
.ifacecount
:
772 for i
in range(count
):
773 if self
.is_on_fastbus(name
, i
):
775 res
= self
.data
[name
].mk_plic(i
, irq_offs
)
778 (txt
, irq_offs
) = res
780 self
.num_slow_irqs
= irq_offs
781 return '\n'.join(li(list(filter(None, ret
)), 4))
783 def mk_sloirqsdef(self
):
784 return " `define NUM_SLOW_IRQS {0}".format(self
.num_slow_irqs
)
786 def mk_clk_con(self
):
788 for (name
, count
) in self
.ifacecount
:
789 for i
in range(count
):
790 if self
.is_on_fastbus(name
, i
):
792 txt
= self
.data
[name
].mk_clk_con(name
, i
)
794 return '\n'.join(li(list(filter(None, ret
)), 8))
796 def is_on_fastbus(self
, name
, i
):
797 #print "fastbus mode", self.fastbusmode, name, i
798 iname
= self
.data
[name
].iname().format(i
)
800 return iname
not in self
.fastbus
801 return iname
in self
.fastbus
804 class PFactory(object):
805 def getcls(self
, name
):
806 from uart
import uart
807 from quart
import quart
808 from sdmmc
import sdmmc
810 from eint
import eint
811 from rs232
import rs232
813 from eint
import eint
814 from jtag
import jtag
815 from spi
import spi
, mspi
816 from qspi
import qspi
, mqspi
817 from gpio
import gpio
818 from rgbttl
import rgbttl
819 from flexbus
import flexbus
821 for k
, v
in {'uart': uart
,
837 if name
.startswith(k
):
842 slowfactory
= PFactory()
844 if __name__
== '__main__':
848 i
= PeripheralIface('uart')
850 i
= PeripheralIface('gpioa')