7 if isinstance(txt
, str):
12 line
= line
.split('\n')
17 res
.append(indent
+ line
)
24 def __init__(self
, name
):
27 def extifdecl(self
, name
, count
):
28 sname
= self
.get_iname(count
)
29 return "interface PeripheralSide%s %s;" % (name
.upper(), sname
)
31 def has_axi_master(self
):
37 def mk_dma_irq(self
, name
, count
):
38 if not self
.irq_name():
40 sname
= self
.get_iname(count
)
41 return "{0}_interrupt".format(sname
)
43 def mk_dma_rule(self
, name
, count
):
44 irqname
= self
.mk_dma_irq(name
, count
)
47 pirqname
= self
.irq_name().format(count
)
48 template
= " {0}.send(\n" + \
49 " slow_peripherals.{1});"
50 return template
.format(irqname
, pirqname
)
52 def get_clock_reset(self
, name
, count
):
53 return "slow_clock,slow_reset"
55 def mk_dma_sync(self
, name
, count
):
56 irqname
= self
.mk_dma_irq(name
, count
)
59 sname
= self
.peripheral
.iname().format(count
)
60 template
= "SyncBitIfc#(Bit#(1)) {0} <-\n" + \
61 " <-mkSyncBitToCC({1});"
62 return template
.format(irqname
, self
.get_clock_reset(name
, count
))
64 def mk_dma_connect(self
, name
, count
):
65 irqname
= self
.mk_dma_irq(name
, count
)
68 return "{0}.read".format(irqname
)
70 def fastifdecl(self
, name
, count
):
73 def slowifdeclmux(self
, name
, count
):
79 def num_axi_regs32(self
):
85 def get_iname(self
, inum
):
86 return "{0}{1}".format(self
.name
, self
.mksuffix(self
.name
, inum
))
88 def axibase(self
, name
, ifacenum
):
90 return "%(name)s%(ifacenum)dBase" % locals()
92 def axiend(self
, name
, ifacenum
):
94 return "%(name)s%(ifacenum)dEnd" % locals()
96 def axi_reg_def(self
, start
, name
, ifacenum
):
98 offs
= self
.num_axi_regs32() * 4 * 16
101 end
= start
+ offs
- 1
102 bname
= self
.axibase(name
, ifacenum
)
103 bend
= self
.axiend(name
, ifacenum
)
104 comment
= "%d 32-bit regs" % self
.num_axi_regs32()
105 return (" `define %(bname)s 'h%(start)08X\n"
106 " `define %(bend)s 'h%(end)08X // %(comment)s" % locals(),
109 def axi_master_name(self
, name
, ifacenum
, typ
=''):
111 return "{0}{1}_master_num".format(name
, ifacenum
)
113 def axi_slave_name(self
, name
, ifacenum
, typ
=''):
115 return "{0}{1}_{2}slave_num".format(name
, ifacenum
, typ
)
117 def axi_master_idx(self
, idx
, name
, ifacenum
, typ
):
118 name
= self
.axi_master_name(name
, ifacenum
, typ
)
119 return ("typedef {0} {1};".format(idx
, name
), 1)
121 def axi_slave_idx(self
, idx
, name
, ifacenum
, typ
):
122 name
= self
.axi_slave_name(name
, ifacenum
, typ
)
123 return ("typedef {0} {1};".format(idx
, name
), 1)
125 def axi_fastaddr_map(self
, name
, ifacenum
):
126 return self
.axi_addr_map(name
, ifacenum
, 'fast')
128 def axi_addr_map(self
, name
, ifacenum
, typ
=""):
129 bname
= self
.axibase(name
, ifacenum
)
130 bend
= self
.axiend(name
, ifacenum
)
131 name
= self
.axi_slave_name(name
, ifacenum
, typ
)
133 if(addr>=`{0} && addr<=`{1})
134 return tuple2(True,fromInteger(valueOf({2})));
136 return template
.format(bname
, bend
, name
)
138 def _mk_pincon(self
, name
, count
, ptyp
):
139 # TODO: really should be using bsv.interface_decl.Interfaces
140 # pin-naming rules.... logic here is hard-coded to duplicate
141 # it (see Interface.__init__ outen)
143 for p
in self
.peripheral
.pinspecs
:
146 #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
147 n
= name
# "{0}{1}".format(self.name, self.mksuffix(name, count))
148 ret
.append("//%s %s" % (n
, str(p
)))
150 sname
= self
.get_iname(count
)
151 sname
= "{0}.{1}".format(sname
, pname
)
152 ps
= "slow_peripherals.%s" % sname
154 sname
= self
.peripheral
.iname().format(count
)
155 sname
= "{0}.{1}".format(sname
, pname
)
156 ps
= "pinmux.peripheral_side.%s" % sname
157 if typ
== 'out' or typ
== 'inout':
158 fname
= self
.pinname_out(pname
)
159 if not n
.startswith('gpio'): # XXX EURGH! horrible hack
160 n_
= "{0}{1}".format(n
, count
)
168 cn
= self
._mk
_actual
_connection
('out', name
,
170 pname
, ps_
, n_
, fname
)
174 fname
= self
.pinname_outen(pname
)
176 if isinstance(fname
, str):
177 fname
= "{0}.{1}".format(n_
, fname
)
178 fname
= self
.pinname_tweak(pname
, 'outen', fname
)
179 cn
= self
._mk
_actual
_connection
('outen', name
,
183 if typ
== 'in' or typ
== 'inout':
184 fname
= self
.pinname_in(pname
)
190 n_
= "{0}{1}".format(n
, count
)
191 n_
= '{0}.{1}'.format(n_
, fname
)
192 n_
= self
.ifname_tweak(pname
, 'in', n_
)
193 cn
= self
._mk
_actual
_connection
('in', name
,
195 pname
, ps_
, n_
, fname
)
197 return '\n'.join(ret
)
199 def _mk_vpincon(self
, name
, count
, ptyp
, typ
, pname
, stype
=None):
203 ret
.append("//%s %s %s %s %s" % (name
, ptyp
, typ
, pname
, stype
))
205 sname
= self
.get_iname(count
)
206 ps
= "slow_peripherals.%s" % sname
208 sname
= self
.peripheral
.iname().format(count
)
209 ps
= "pinmux.peripheral_side.%s" % sname
210 n
= self
.get_iname(count
)
212 n
= "{0}.{1}".format(n
, stype
)
213 ps_
= "{0}.{1}".format(ps
, pname
)
214 ret
+= self
._mk
_actual
_connection
(typ
, name
, count
, typ
,
215 pname
, ps_
, n
, stype
)
216 return '\n'.join(ret
)
218 def _mk_actual_connection(self
, ctype
, name
, count
, typ
,
219 pname
, ps
, n
, fname
):
221 ck
= self
.get_clock_reset(name
, count
)
223 if ck
== PBase
.get_clock_reset(self
, name
, count
):
224 ret
.append("mkConnection({0},\n\t\t\t{1}.{2});"
225 .format(ps
, n
, fname
))
227 n2
= "{0}{1}".format(name
, count
)
228 sync
= '{0}_{1}_sync'.format(n2
, pname
)
229 ret
.append("mkConnection({0},\n\t\t\t{1}.get);"
231 ret
.append("mkConnection({0}.put,\n\t\t\t{1}.{2});"
232 .format(sync
, n
, fname
))
233 elif ctype
== 'outen':
234 ret
.append("mkConnection({0}_outen,\n\t\t\t{1});"
237 if ck
== PBase
.get_clock_reset(self
, name
, count
):
238 ret
.append("mkConnection({1},\n\t\t\t{0});".format(
241 n2
= "{0}{1}".format(name
, count
)
242 sync
= '{0}_{1}_sync'.format(n2
, pname
)
243 ret
.append("mkConnection({1}.put,\n\t\t\t{0});".format(
245 ret
.append("mkConnection({1},\n\t\t\t{0}.get);".format(
250 def _mk_clk_con(self
, name
, count
, ctype
):
252 ck
= self
.get_clock_reset(name
, count
)
253 if ck
== PBase
.get_clock_reset(self
, name
, count
):
256 spc
= "sp_clock, sp_reset"
259 ck
= "core_clock, core_reset"
261 Ifc_sync#({0}) {1}_sync <-mksyncconnection(
263 for p
in self
.peripheral
.pinspecs
:
267 if typ
== 'out' or typ
== 'inout':
268 fname
= self
.pinname_out(pname
)
271 if not n
.startswith('gpio'): # XXX EURGH! horrible hack
272 n_
= "{0}{1}".format(n
, count
)
275 n_
= '{0}_{1}'.format(n_
, pname
)
276 ret
.append(template
.format("Bit#(1)", n_
, ck
, spc
))
277 if typ
== 'in' or typ
== 'inout':
278 fname
= self
.pinname_in(pname
)
281 #fname = self.pinname_in(pname)
282 n_
= "{0}{1}".format(n
, count
)
283 n_
= '{0}_{1}'.format(n_
, pname
)
284 #n_ = self.ifname_tweak(pname, 'in', n_)
285 ret
.append(template
.format("Bit#(1)", n_
, spc
, ck
))
286 return '\n'.join(ret
)
288 def _mk_clk_vcon(self
, name
, count
, ctype
, typ
, pname
, bitspec
):
289 ck
= self
.get_clock_reset(name
, count
)
290 if ck
== PBase
.get_clock_reset(self
, name
, count
):
293 spc
= "sp_clock, sp_reset"
296 ck
= "core_clock, core_reset"
298 Ifc_sync#({0}) {1}_sync <-mksyncconnection(
301 n_
= "{0}{1}".format(name
, count
)
302 n_
= '{0}_{1}'.format(n_
, pname
)
303 return template
.format(bitspec
, n_
, ck
, spc
)
306 def mk_cellconn(self
, *args
):
309 def mkfast_peripheral(self
, size
=0):
312 def mkslow_peripheral(self
, size
=0):
315 def mksuffix(self
, name
, i
):
318 def __mk_connection(self
, con
, aname
, fabricname
):
319 txt
= "mkConnection ({2}.v_to_slaves\n" + \
320 " [fromInteger(valueOf({1}))],\n" + \
323 print "PBase __mk_connection", self
.name
, aname
326 return txt
.format(con
, aname
, fabricname
)
328 def __mk_master_connection(self
, con
, aname
):
329 txt
= "mkConnection (slow_fabric.v_to_slaves\n" + \
330 " [fromInteger(valueOf({1}))],\n" + \
333 print "PBase __mk_connection", self
.name
, aname
336 return txt
.format(con
, aname
)
338 def mk_connection(self
, count
, fabricname
, typ
, name
=None):
341 print "PBase mk_conn", self
.name
, count
342 aname
= self
.axi_slave_name(name
, count
, typ
)
343 #dname = self.mksuffix(name, count)
344 #dname = "{0}{1}".format(name, dname)
345 con
= self
._mk
_connection
(name
, count
).format(count
, aname
)
346 return self
.__mk
_connection
(con
, aname
, fabricname
)
348 def _mk_connection(self
, name
=None, count
=0):
351 def pinname_out(self
, pname
):
354 def pinname_in(self
, pname
):
357 def pinname_outen(self
, pname
):
360 def ifname_tweak(self
, pname
, typ
, txt
):
363 def pinname_tweak(self
, pname
, typ
, txt
):
369 def mk_plic(self
, inum
, irq_offs
):
371 print "mk_plic", self
.name
, inum
, irq_offs
372 niq
= self
.num_irqs()
374 return ('', irq_offs
)
375 name
= self
.get_iname(inum
)
376 res
.append("// PLIC rules for {0}".format(name
))
377 for idx
in range(niq
):
378 plic_obj
= self
.plic_object(name
, idx
)
379 print "plic_obj", name
, idx
, plic_obj
380 plic
= mkplic_rule
.format(name
, plic_obj
, irq_offs
)
382 irq_offs
+= 1 # increment to next irq
383 return ('\n'.join(res
), irq_offs
)
385 def mk_ext_ifacedef(self
, iname
, inum
):
388 def extfastifinstance(self
, name
, count
):
391 def _extifinstance(self
, name
, count
, suffix
, prefix
, samename
=False,
395 pname
= self
.get_iname(count
)
399 sname
= self
.peripheral
.iname().format(count
)
400 template
= "interface {0}{3} = {2}{1}{4};"
401 return template
.format(pname
, sname
, prefix
, suffix
, ifsuffix
)
403 def extifinstance2(self
, name
, count
):
406 def extifinstance(self
, name
, count
):
407 return self
._extifinstance
(name
, count
, "",
408 "pinmux.peripheral_side.")
412 rule rl_connect_{0}_to_plic_{2};
413 if({1} == 1'b1) begin
414 ff_gateway_queue[{2}].enq(1);
415 plic.ifc_external_irq[{2}].irq_frm_gateway(True);
420 axi_master_declarations
= """\
421 typedef 0 Dmem_master_num;
422 typedef 1 Imem_master_num;
424 typedef TAdd#(LastGen_master_num, `ifdef Debug 1 `else 0 `endif )
426 typedef TAdd#(Debug_master_num, `ifdef DMA 1 `else 0 `endif )
428 typedef TAdd#(DMA_master_num,1)
432 axi_fastslave_declarations
= """\
434 typedef TAdd#(LastGen_fastslave_num,1) Sdram_slave_num;
435 typedef TAdd#(Sdram_slave_num ,`ifdef SDRAM 1 `else 0 `endif )
437 typedef TAdd#(Sdram_cfg_slave_num,`ifdef BOOTROM 1 `else 0 `endif )
439 typedef TAdd#(BootRom_slave_num ,`ifdef Debug 1 `else 0 `endif )
441 typedef TAdd#(Debug_slave_num , `ifdef TCMemory 1 `else 0 `endif )
443 typedef TAdd#(TCM_slave_num ,`ifdef DMA 1 `else 0 `endif )
445 typedef TAdd#(Dma_slave_num ,1 ) SlowPeripheral_slave_num;
446 typedef TAdd#(SlowPeripheral_slave_num,`ifdef VME 1 `else 0 `endif )
448 typedef TAdd#(VME_slave_num,1) Num_Fast_Slaves;
451 axi_slave_declarations
= """\
452 typedef 0 SlowMaster;
454 typedef TAdd#(LastGen_slave_num,`ifdef CLINT 1 `else 0 `endif )
456 typedef TAdd#(CLINT_slave_num ,`ifdef PLIC 1 `else 0 `endif )
458 typedef TAdd#(Plic_slave_num ,`ifdef AXIEXP 1 `else 0 `endif )
460 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
463 pinmux_cellrule
= """\
464 rule connect_select_lines_pinmux;
470 class CallFn(object):
471 def __init__(self
, peripheral
, name
):
472 self
.peripheral
= peripheral
475 def __call__(self
, *args
):
476 #print "__call__", self.name, self.peripheral.slow, args
477 if not self
.peripheral
.slow
:
479 return getattr(self
.peripheral
.slow
, self
.name
)(*args
[1:])
482 class PeripheralIface(object):
483 def __init__(self
, ifacename
):
485 slow
= slowfactory
.getcls(ifacename
)
486 print "Iface", ifacename
, slow
488 self
.slow
= slow(ifacename
)
489 self
.slow
.peripheral
= self
490 for fname
in ['slowimport',
492 'extifinstance2', 'extifinstance', 'extifdecl',
493 'slowifdecl', 'slowifdeclmux',
496 'mk_dma_sync', 'mk_dma_connect', 'mk_dma_rule',
498 'mk_plic', 'mk_ext_ifacedef',
499 '_mk_clk_con', 'mk_ext_ifacedef',
500 'mk_connection', 'mk_cellconn', '_mk_pincon']:
501 fn
= CallFn(self
, fname
)
502 setattr(self
, fname
, types
.MethodType(fn
, self
))
504 #print "PeripheralIface"
507 def mksuffix(self
, name
, i
):
508 if self
.slow
is None:
510 return self
.slow
.mksuffix(name
, i
)
512 def axi_reg_def(self
, start
, count
):
515 return self
.slow
.axi_reg_def(start
, self
.ifacename
, count
)
517 def axi_master_idx(self
, start
, count
, typ
):
518 if not self
.slow
or not self
.slow
.has_axi_master():
520 return self
.slow
.axi_master_idx(start
, self
.ifacename
, count
, typ
)
522 def axi_slave_idx(self
, start
, count
, typ
):
525 return self
.slow
.axi_slave_idx(start
, self
.ifacename
, count
, typ
)
527 def axi_fastaddr_map(self
, count
):
530 return self
.slow
.axi_fastaddr_map(self
.ifacename
, count
)
532 def axi_addr_map(self
, count
):
535 return self
.slow
.axi_addr_map(self
.ifacename
, count
)
538 class PeripheralInterfaces(object):
540 self
.fastbusmode
= False
542 def slowimport(self
, *args
):
544 for (name
, count
) in self
.ifacecount
:
545 #print "slowimport", name, self.data[name].slowimport
546 ret
.append(self
.data
[name
].slowimport())
547 return '\n'.join(li(list(filter(None, ret
)), 4))
549 def extfastifinstance(self
, *args
):
551 for (name
, count
) in self
.ifacecount
:
552 for i
in range(count
):
553 iname
= self
.data
[name
].iname().format(i
)
554 print "extfast", iname
, self
.is_on_fastbus(name
, i
)
555 if self
.is_on_fastbus(name
, i
):
557 ret
.append(self
.data
[name
].extfastifinstance(name
, i
))
558 return '\n'.join(li(list(filter(None, ret
)), 8))
560 def extifinstance2(self
, *args
):
562 for (name
, count
) in self
.ifacecount
:
563 for i
in range(count
):
564 iname
= self
.data
[name
].iname().format(i
)
565 ret
.append(self
.data
[name
].extifinstance2(name
, i
))
566 return '\n'.join(li(list(filter(None, ret
)), 8))
568 def extifinstance(self
, *args
):
570 for (name
, count
) in self
.ifacecount
:
571 for i
in range(count
):
572 iname
= self
.data
[name
].iname().format(i
)
573 if not self
.is_on_fastbus(name
, i
):
575 ret
.append(self
.data
[name
].extifinstance(name
, i
))
576 return '\n'.join(li(list(filter(None, ret
)), 8))
578 def extifdecl(self
, *args
):
580 for (name
, count
) in self
.ifacecount
:
581 for i
in range(count
):
582 if not self
.is_on_fastbus(name
, i
):
584 ret
.append(self
.data
[name
].extifdecl(name
, i
))
585 return '\n'.join(li(list(filter(None, ret
)), 8))
587 def slowifdeclmux(self
, *args
):
589 for (name
, count
) in self
.ifacecount
:
590 for i
in range(count
):
591 ret
.append(self
.data
[name
].slowifdeclmux(name
, i
))
592 return '\n'.join(li(list(filter(None, ret
)), 8))
594 def fastifdecl(self
, *args
):
596 for (name
, count
) in self
.ifacecount
:
597 for i
in range(count
):
598 print "fastifdecl", name
, i
, self
.is_on_fastbus(name
, i
)
599 if self
.is_on_fastbus(name
, i
):
601 ret
.append(self
.data
[name
].fastifdecl(name
, i
))
602 return '\n'.join(li(list(filter(None, ret
)), 4))
604 def slowifdecl(self
, *args
):
606 for (name
, count
) in self
.ifacecount
:
607 for i
in range(count
):
608 if self
.is_on_fastbus(name
, i
):
610 ret
.append(self
.data
[name
].slowifdecl().format(i
, name
))
611 return '\n'.join(list(filter(None, ret
)))
613 def axi_fastmem_def(self
, *args
):
614 return self
._axi
_reg
_def
(0x50000000, *args
)
616 def axi_reg_def(self
, *args
):
617 return self
._axi
_reg
_def
(0x00011100, *args
)
619 def _axi_reg_def(self
, start
, *args
):
621 for (name
, count
) in self
.ifacecount
:
622 for i
in range(count
):
623 if self
.is_on_fastbus(name
, i
):
625 x
= self
.data
[name
].axi_reg_def(start
, i
)
626 #print ("ifc", name, x)
630 return '\n'.join(list(filter(None, ret
)))
632 def _axi_num_idx(self
, start
, template
, typ
, idxtype
, *args
):
634 for (name
, count
) in self
.ifacecount
:
635 for i
in range(count
):
636 if self
.is_on_fastbus(name
, i
):
639 fn
= self
.data
[name
].axi_master_idx
641 fn
= self
.data
[name
].axi_slave_idx
642 (rdef
, offs
) = fn(start
, i
, idxtype
)
643 #print ("ifc", name, rdef, offs)
646 ret
.append("typedef %d LastGen_%s_num;" % (start
- 1, typ
))
647 decls
= '\n'.join(list(filter(None, ret
)))
648 return template
.format(decls
)
650 def axi_slave_idx(self
, *args
):
651 return self
._axi
_num
_idx
(0, axi_slave_declarations
, 'slave',
654 def axi_fastslave_idx(self
, *args
):
655 return self
._axi
_num
_idx
(0, axi_fastslave_declarations
, 'fastslave',
658 def axi_master_idx(self
, *args
):
659 return self
._axi
_num
_idx
(2, axi_master_declarations
, 'master',
662 def axi_fastslave_idx(self
, *args
):
663 return self
._axi
_num
_idx
(0, axi_fastslave_declarations
, 'fastslave',
666 def axi_fastaddr_map(self
, *args
):
668 for (name
, count
) in self
.ifacecount
:
669 for i
in range(count
):
670 if self
.is_on_fastbus(name
, i
):
672 ret
.append(self
.data
[name
].axi_fastaddr_map(i
))
673 return '\n'.join(li(list(filter(None, ret
)), 8))
675 def axi_addr_map(self
, *args
):
677 for (name
, count
) in self
.ifacecount
:
678 for i
in range(count
):
679 if self
.is_on_fastbus(name
, i
):
681 ret
.append(self
.data
[name
].axi_addr_map(i
))
682 return '\n'.join(li(list(filter(None, ret
)), 8))
684 def mkfast_peripheral(self
, *args
):
686 for (name
, count
) in self
.ifacecount
:
687 for i
in range(count
):
688 if self
.is_on_fastbus(name
, i
):
690 #print "mkfast", name, count
691 x
= self
.data
[name
].mkfast_peripheral()
693 suffix
= self
.data
[name
].mksuffix(name
, i
)
694 ret
.append(x
.format(suffix
))
695 return '\n'.join(li(list(filter(None, ret
)), 8))
697 def mkslow_peripheral(self
, *args
):
699 for (name
, count
) in self
.ifacecount
:
700 for i
in range(count
):
701 if self
.is_on_fastbus(name
, i
):
703 #print "mkslow", name, count
704 x
= self
.data
[name
].mkslow_peripheral()
706 suffix
= self
.data
[name
].mksuffix(name
, i
)
707 ret
.append(x
.format(suffix
))
708 return '\n'.join(li(list(filter(None, ret
)), 8))
710 def mk_fast_connection(self
, *args
):
712 for (name
, count
) in self
.ifacecount
:
713 for i
in range(count
):
714 if self
.is_on_fastbus(name
, i
):
716 txt
= self
.data
[name
].mk_connection(i
, "fabric", "fast")
719 print self
.data
[name
].mk_connection
721 return '\n'.join(li(list(filter(None, ret
)), 12))
723 def mk_connection(self
, *args
):
725 for (name
, count
) in self
.ifacecount
:
726 for i
in range(count
):
727 if self
.is_on_fastbus(name
, i
):
729 txt
= self
.data
[name
].mk_connection(i
, "slow_fabric", "")
732 print self
.data
[name
].mk_connection
734 return '\n'.join(li(list(filter(None, ret
)), 8))
736 def mk_cellconn(self
):
739 for (name
, count
) in self
.ifacecount
:
740 for i
in range(count
):
741 if self
.is_on_fastbus(name
, i
):
743 res
= self
.data
[name
].mk_cellconn(cellcount
, name
, i
)
746 (txt
, cellcount
) = res
748 ret
= li('\n'.join(list(filter(None, ret
))), 4)
749 return li(pinmux_cellrule
.format(ret
), 4)
752 return self
._mk
_pincon
("slow")
754 def mk_fast_pincon(self
):
755 return self
._mk
_pincon
("fast")
757 def _mk_pincon(self
, typ
):
759 for (name
, count
) in self
.ifacecount
:
760 for i
in range(count
):
761 if self
.is_on_fastbus(name
, i
):
763 txt
= self
.data
[name
]._mk
_pincon
(name
, i
, typ
)
765 return '\n'.join(li(list(filter(None, ret
)), 4))
767 def mk_dma_irq(self
):
775 for (name
, count
) in self
.ifacecount
:
777 for i
in range(count
):
778 if not self
.is_on_fastbus(name
, i
):
780 txt
= self
.data
[name
].mk_dma_sync(name
, i
)
784 txt
= self
.data
[name
].mk_dma_rule(name
, i
)
785 ifacerules
.append(txt
)
786 txt
= self
.data
[name
].mk_dma_connect(name
, i
)
788 ifacerules
= list(filter(None, ifacerules
))
790 txt
= "rule synchronize_%s_interrupts;" % name
793 rules
.append("endrule")
795 cnct
= list(filter(None, cnct
))
797 _cnct
= ["rule rl_connect_interrupt_to_DMA;",
798 " Bit #(%d) lv_interrupt_to_DMA={" % ct
]
801 cnct
= _cnct
+ [spc
+ spcsep
.join(cnct
)]
803 cnct
.append(" dma.interrupt_from_peripherals(\n" +
804 " lv_interrupt_to_DMA);")
805 cnct
.append("endrule;")
807 ret
= list(filter(None, sync
+ rules
+ cnct
))
809 return '\n'.join(ret
)
811 def num_dmachannels(self
):
812 return "`define NUM_DMACHANNELS {0}".format(self
.dma_count
)
814 def mk_ext_ifacedef(self
):
816 for (name
, count
) in self
.ifacecount
:
817 for i
in range(count
):
818 if self
.is_on_fastbus(name
, i
):
820 txt
= self
.data
[name
].mk_ext_ifacedef(name
, i
)
822 return '\n'.join(li(list(filter(None, ret
)), 8))
826 irq_offs
= 8 # XXX: DMA scovers 0-7?
827 for (name
, count
) in self
.ifacecount
:
828 for i
in range(count
):
829 if self
.is_on_fastbus(name
, i
):
831 res
= self
.data
[name
].mk_plic(i
, irq_offs
)
834 (txt
, irq_offs
) = res
836 self
.num_slow_irqs
= irq_offs
837 return '\n'.join(li(list(filter(None, ret
)), 4))
839 def mk_sloirqsdef(self
):
840 return " `define NUM_SLOW_IRQS {0}".format(self
.num_slow_irqs
)
842 def mk_fastclk_con(self
):
843 return self
._mk
_clk
_con
("fast")
845 def mk_slowclk_con(self
):
846 return self
._mk
_clk
_con
("slow")
848 def _mk_clk_con(self
, ctype
):
850 for (name
, count
) in self
.ifacecount
:
851 for i
in range(count
):
852 if self
.is_on_fastbus(name
, i
):
854 txt
= self
.data
[name
]._mk
_clk
_con
(name
, i
, ctype
)
856 return '\n'.join(li(list(filter(None, ret
)), 8))
858 def is_on_fastbus(self
, name
, i
):
859 #print "fastbus mode", self.fastbusmode, name, i
860 iname
= self
.data
[name
].iname().format(i
)
862 return iname
not in self
.fastbus
863 return iname
in self
.fastbus
866 class PFactory(object):
867 def getcls(self
, name
):
868 from uart
import uart
869 from quart
import quart
870 from sdmmc
import sdmmc
872 from eint
import eint
873 from rs232
import rs232
875 from eint
import eint
876 from jtag
import jtag
877 from spi
import spi
, mspi
878 from qspi
import qspi
, mqspi
879 from gpio
import gpio
880 from rgbttl
import rgbttl
881 from flexbus
import flexbus
883 for k
, v
in {'uart': uart
,
899 if name
.startswith(k
):
904 slowfactory
= PFactory()
906 if __name__
== '__main__':
910 i
= PeripheralIface('uart')
912 i
= PeripheralIface('gpioa')