7 if isinstance(txt
, str):
12 line
= line
.split('\n')
17 res
.append(indent
+ line
)
23 class MMapConfig(object):
25 def get_mmap_configs(self
):
27 for cfg
in self
.peripheral
.configs
:
28 res
.append(cfg
.get('mmap', None))
29 # XXX HACK! assume all configs same for each peripheral!
32 def map_to_idx(self
, cfg
, idx
):
33 if isinstance(idx
, int):
35 for (i
, c
) in enumerate(cfg
):
38 assert "config name %s not found" % s
40 def get_mmap_cfg_start(self
, idx
):
41 cfg
= self
.get_mmap_configs()
43 nregs
= self
.num_axi_regs32()
44 if isinstance(nregs
, int) or len(nregs
) == 1:
47 idx
= self
.map_to_idx(cfg
, idx
)
50 def get_mmap_cfg_name(self
, idx
):
51 cfg
= self
.get_mmap_configs()
53 nregs
= self
.num_axi_regs32()
54 if isinstance(nregs
, int) or len(nregs
) == 1:
59 def num_axi_regs32cfg(self
):
60 cfg
= self
.get_mmap_configs()
62 return self
.num_axi_regs32()
69 class PBase(MMapConfig
):
70 def __init__(self
, name
):
72 MMapConfig
.__init
__(self
)
74 def extifdecl(self
, name
, count
):
75 sname
= self
.get_iname(count
)
76 return "interface PeripheralSide%s %s;" % (name
.upper(), sname
)
78 def has_axi_master(self
):
84 def mk_dma_irq(self
, name
, count
):
85 if not self
.irq_name():
87 sname
= self
.get_iname(count
)
88 return "{0}_interrupt".format(sname
)
90 def mk_dma_rule(self
, name
, count
):
91 irqname
= self
.mk_dma_irq(name
, count
)
94 pirqname
= self
.irq_name().format(count
)
95 template
= " {0}.send(\n" + \
96 " slow_peripherals.{1});"
97 return template
.format(irqname
, pirqname
)
99 def get_clock_reset(self
, name
, count
):
100 return "slow_clock,slow_reset"
102 def mk_dma_sync(self
, name
, count
):
103 irqname
= self
.mk_dma_irq(name
, count
)
106 sname
= self
.peripheral
.iname().format(count
)
107 template
= "SyncBitIfc#(Bit#(1)) {0} <-\n" + \
108 " <-mkSyncBitToCC({1});"
109 return template
.format(irqname
, self
.get_clock_reset(name
, count
))
111 def mk_dma_connect(self
, name
, count
):
112 irqname
= self
.mk_dma_irq(name
, count
)
115 return "{0}.read".format(irqname
)
117 def fastifdecl(self
, name
, count
):
120 def slowifdeclmux(self
, name
, count
):
123 def slowimport(self
):
126 def num_axi_regs32(self
):
129 def slowifdecl(self
):
132 def get_iname(self
, inum
):
133 return "{0}{1}".format(self
.name
, self
.mksuffix(self
.name
, inum
))
135 def axibase(self
, name
, ifacenum
, idx
):
137 return "%(name)s%(ifacenum)d%(idx)sBase" % locals()
139 def axiend(self
, name
, ifacenum
, idx
):
141 return "%(name)s%(ifacenum)d%(idx)sEnd" % locals()
143 def _axi_reg_def(self
, idx
, numregs
, start
, name
, ifacenum
):
145 offs
= numregs
* 4 * 16
148 cfgstart
= self
.get_mmap_cfg_start(idx
)
151 end
= start
+ offs
- 1
152 offs
= 0 # don't do contiguous addressing
154 end
= start
+ offs
- 1
155 bname
= self
.axibase(name
, ifacenum
, idx
)
156 bend
= self
.axiend(name
, ifacenum
, idx
)
157 comment
= "%d 32-bit regs" % numregs
158 return ("`define %(bname)s 'h%(start)08X\n"
159 "`define %(bend)s 'h%(end)08X // %(comment)s" % locals(),
162 def axi_reg_def(self
, start
, name
, ifacenum
):
163 offs
= self
.num_axi_regs32cfg()
166 if not isinstance(offs
, list):
171 for (idx
, nregs
) in enumerate(offs
):
172 cfg
= self
.get_mmap_cfg_name(idx
)
173 (txt
, off
) = self
._axi
_reg
_def
(cfg
, nregs
, start
, name
, ifacenum
)
177 return ('\n'.join(res
), offstotal
)
179 def axi_master_name(self
, name
, ifacenum
, typ
=''):
181 return "{0}{1}_master_num".format(name
, ifacenum
)
183 def axi_slave_name(self
, idx
, name
, ifacenum
, typ
=''):
185 return "{0}{1}{3}_{2}slave_num".format(name
, ifacenum
, typ
, idx
)
187 def axi_master_idx(self
, idx
, name
, ifacenum
, typ
):
188 name
= self
.axi_master_name(name
, ifacenum
, typ
)
189 return ("typedef {0} {1};".format(idx
, name
), 1)
191 def axi_slave_idx(self
, idx
, name
, ifacenum
, typ
):
192 offs
= self
.num_axi_regs32()
195 if not isinstance(offs
, list):
198 for (i
, nregs
) in enumerate(offs
):
199 cfg
= self
.get_mmap_cfg_name(i
)
200 name_
= self
.axi_slave_name(cfg
, name
, ifacenum
, typ
)
201 res
.append("typedef {0} {1};".format(idx
+ i
, name_
))
202 return ('\n'.join(res
), len(offs
))
204 def axi_fastaddr_map(self
, name
, ifacenum
):
205 return self
.axi_addr_map(name
, ifacenum
, 'fast')
207 def _axi_addr_map(self
, idx
, name
, ifacenum
, typ
=""):
208 bname
= self
.axibase(name
, ifacenum
, idx
)
209 bend
= self
.axiend(name
, ifacenum
, idx
)
210 name
= self
.axi_slave_name(idx
, name
, ifacenum
, typ
)
212 if(addr>=`{0} && addr<=`{1})
213 return tuple2(True,fromInteger(valueOf({2})));
215 return template
.format(bname
, bend
, name
)
217 def axi_addr_map(self
, name
, ifacenum
, typ
=""):
218 offs
= self
.num_axi_regs32()
221 if not isinstance(offs
, list):
224 for (idx
, nregs
) in enumerate(offs
):
225 cfg
= self
.get_mmap_cfg_name(idx
)
226 res
.append(self
._axi
_addr
_map
(cfg
, name
, ifacenum
, typ
))
227 return '\n'.join(res
)
229 def _mk_pincon(self
, name
, count
, ptyp
):
230 # TODO: really should be using bsv.interface_decl.Interfaces
231 # pin-naming rules.... logic here is hard-coded to duplicate
232 # it (see Interface.__init__ outen)
234 for p
in self
.peripheral
.pinspecs
:
237 #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
238 n
= name
# "{0}{1}".format(self.name, self.mksuffix(name, count))
239 ret
.append("//%s %s" % (n
, str(p
)))
241 sname
= self
.get_iname(count
)
242 sname
= "{0}.{1}".format(sname
, pname
)
243 ps
= "slow_peripherals.%s" % sname
245 sname
= self
.peripheral
.iname().format(count
)
246 sname
= "{0}.{1}".format(sname
, pname
)
247 ps
= "pinmux.peripheral_side.%s" % sname
248 if typ
== 'out' or typ
== 'inout':
249 fname
= self
.pinname_out(pname
)
250 if not n
.startswith('gpio'): # XXX EURGH! horrible hack
251 n_
= "{0}{1}".format(n
, count
)
259 cn
= self
._mk
_actual
_connection
('out', name
,
261 pname
, ps_
, n_
, fname
)
265 fname
= self
.pinname_outen(pname
)
267 if isinstance(fname
, str):
268 fname
= "{0}.{1}".format(n_
, fname
)
269 fname
= self
.pinname_tweak(pname
, 'outen', fname
)
270 cn
= self
._mk
_actual
_connection
('outen', name
,
274 if typ
== 'in' or typ
== 'inout':
275 fname
= self
.pinname_in(pname
)
281 n_
= "{0}{1}".format(n
, count
)
282 n_
= '{0}.{1}'.format(n_
, fname
)
283 n_
= self
.ifname_tweak(pname
, 'in', n_
)
284 cn
= self
._mk
_actual
_connection
('in', name
,
286 pname
, ps_
, n_
, fname
)
288 return '\n'.join(ret
)
290 def _mk_vpincon(self
, name
, count
, ptyp
, typ
, pname
, stype
=None):
294 ret
.append("//%s %s %s %s %s" % (name
, ptyp
, typ
, pname
, stype
))
296 sname
= self
.get_iname(count
)
297 ps
= "slow_peripherals.%s" % sname
299 sname
= self
.peripheral
.iname().format(count
)
300 ps
= "pinmux.peripheral_side.%s" % sname
301 n
= self
.get_iname(count
)
303 n
= "{0}.{1}".format(n
, stype
)
304 ps_
= "{0}.{1}".format(ps
, pname
)
305 ret
+= self
._mk
_actual
_connection
(typ
, name
, count
, typ
,
306 pname
, ps_
, n
, stype
)
307 return '\n'.join(ret
)
309 def _mk_actual_connection(self
, ctype
, name
, count
, typ
,
310 pname
, ps
, n
, fname
):
312 ck
= self
.get_clock_reset(name
, count
)
314 if ck
== PBase
.get_clock_reset(self
, name
, count
):
315 ret
.append("mkConnection({0},\n\t\t\t{1}.{2});"
316 .format(ps
, n
, fname
))
318 n2
= "{0}{1}".format(name
, count
)
319 sync
= '{0}_{1}_sync'.format(n2
, pname
)
320 ret
.append("mkConnection({0},\n\t\t\t{1}.get);"
322 ret
.append("mkConnection({0}.put,\n\t\t\t{1}.{2});"
323 .format(sync
, n
, fname
))
324 elif ctype
== 'outen':
325 ret
.append("mkConnection({0}_outen,\n\t\t\t{1});"
328 if ck
== PBase
.get_clock_reset(self
, name
, count
):
329 ret
.append("mkConnection({1},\n\t\t\t{0});".format(
332 n2
= "{0}{1}".format(name
, count
)
333 sync
= '{0}_{1}_sync'.format(n2
, pname
)
334 ret
.append("mkConnection({1}.put,\n\t\t\t{0});".format(
336 ret
.append("mkConnection({1},\n\t\t\t{0}.get);".format(
340 def _mk_clk_con(self
, name
, count
, ctype
):
342 ck
= self
.get_clock_reset(name
, count
)
343 if ck
== PBase
.get_clock_reset(self
, name
, count
):
346 spc
= self
.get_clk_spc(ctype
)
349 ck
= self
.get_clk_spc(ctype
)
351 Ifc_sync#({0}) {1}_sync <-mksyncconnection(
353 for p
in self
.peripheral
.pinspecs
:
357 if typ
== 'out' or typ
== 'inout':
358 fname
= self
.pinname_out(pname
)
361 if not n
.startswith('gpio'): # XXX EURGH! horrible hack
362 n_
= "{0}{1}".format(n
, count
)
365 n_
= '{0}_{1}'.format(n_
, pname
)
366 ret
.append(template
.format("Bit#(1)", n_
, ck
, spc
))
367 if typ
== 'in' or typ
== 'inout':
368 fname
= self
.pinname_in(pname
)
371 #fname = self.pinname_in(pname)
372 n_
= "{0}{1}".format(n
, count
)
373 n_
= '{0}_{1}'.format(n_
, pname
)
374 #n_ = self.ifname_tweak(pname, 'in', n_)
375 ret
.append(template
.format("Bit#(1)", n_
, spc
, ck
))
376 return '\n'.join(ret
)
378 def get_clk_spc(self
, ctype
):
380 return "sp_clock, sp_reset"
382 return "core_clock, core_reset"
384 def _mk_clk_vcon(self
, name
, count
, ctype
, typ
, pname
, bitspec
):
385 ck
= self
.get_clock_reset(name
, count
)
386 if ck
== PBase
.get_clock_reset(self
, name
, count
):
389 spc
= self
.get_clk_spc(ctype
)
392 ck
= self
.get_clk_spc(ctype
)
394 Ifc_sync#({0}) {1}_sync <-mksyncconnection(
397 n_
= "{0}{1}".format(name
, count
)
398 n_
= '{0}_{1}'.format(n_
, pname
)
399 if typ
== 'in' or typ
== 'inout':
401 return template
.format(bitspec
, n_
, ck
, spc
)
403 def mk_cellconn(self
, *args
):
406 def mkfast_peripheral(self
, size
=0):
409 def mkslow_peripheral(self
, size
=0):
412 def mksuffix(self
, name
, i
):
415 def __mk_connection(self
, con
, aname
, count
, fabricname
):
416 txt
= "mkConnection ({2}.v_to_slaves\n" + \
417 " [fromInteger(valueOf({1}))],\n" + \
420 print "PBase __mk_connection", self
.name
, aname
423 con
= con
.format(count
, aname
)
424 return txt
.format(con
, aname
, fabricname
)
426 def __mk_master_connection(self
, con
, aname
, count
, fabricname
):
427 txt
= "mkConnection ({0}, {2}.v_from_masters\n" + \
428 " [fromInteger(valueOf({1}))]);\n"
430 print "PBase __mk_master_connection", self
.name
, aname
433 con
= con
.format(count
, aname
)
434 return txt
.format(con
, aname
, fabricname
)
436 def mk_master_connection(self
, count
, fabricname
, typ
, name
=None):
437 if not self
.has_axi_master():
441 print "PBase mk_master_conn", self
.name
, count
442 aname
= self
.axi_master_name(name
, count
, typ
)
444 connections
= self
._mk
_connection
(name
, count
, True)
445 if not isinstance(connections
, list):
446 connections
= [connections
]
447 for con
in connections
:
448 ret
.append(self
.__mk
_master
_connection
(con
, aname
, count
,
450 return '\n'.join(ret
)
452 def mk_connection(self
, count
, fabricname
, typ
, name
=None):
455 print "PBase mk_conn", self
.name
, count
457 connections
= self
._mk
_connection
(name
, count
)
458 if not isinstance(connections
, list):
459 connections
= [connections
]
460 for (idx
, con
) in enumerate(connections
):
461 if len(connections
) == 1:
465 aname
= self
.axi_slave_name(idx
, name
, count
, typ
)
466 ret
.append(self
.__mk
_connection
(con
, aname
, count
, fabricname
))
467 return '\n'.join(ret
)
469 def _mk_connection(self
, name
=None, count
=0):
472 def pinname_out(self
, pname
):
475 def pinname_in(self
, pname
):
478 def pinname_outen(self
, pname
):
481 def ifname_tweak(self
, pname
, typ
, txt
):
484 def pinname_tweak(self
, pname
, typ
, txt
):
490 def mk_plic(self
, inum
, irq_offs
):
492 print "mk_plic", self
.name
, inum
, irq_offs
493 niq
= self
.num_irqs()
495 return ('', irq_offs
)
496 name
= self
.get_iname(inum
)
497 res
.append("// PLIC rules for {0}".format(name
))
498 for idx
in range(niq
):
499 plic_obj
= self
.plic_object(name
, idx
)
500 print "plic_obj", name
, idx
, plic_obj
501 plic
= mkplic_rule
.format(name
, plic_obj
, irq_offs
)
503 irq_offs
+= 1 # increment to next irq
504 return ('\n'.join(res
), irq_offs
)
506 def mk_ext_ifacedef(self
, iname
, inum
):
509 def extfastifinstance(self
, name
, count
):
512 def _extifinstance(self
, name
, count
, suffix
, prefix
, samename
=False,
516 pname
= self
.get_iname(count
)
520 sname
= self
.peripheral
.iname().format(count
)
521 template
= "interface {0}{3} = {2}{1}{4};"
522 return template
.format(pname
, sname
, prefix
, suffix
, ifsuffix
)
524 def extifinstance2(self
, name
, count
):
527 def extifinstance(self
, name
, count
):
528 return self
._extifinstance
(name
, count
, "",
529 "pinmux.peripheral_side.")
533 rule rl_connect_{0}_to_plic_{2};
534 if({1} == 1'b1) begin
535 ff_gateway_queue[{2}].enq(1);
536 plic.ifc_external_irq[{2}].irq_frm_gateway(True);
541 axi_master_declarations
= """\
542 typedef 0 Dmem_master_num;
543 typedef 1 Imem_master_num;
545 typedef TAdd#(LastGen_master_num, `ifdef Debug 1 `else 0 `endif )
547 typedef TAdd#(Debug_master_num, `ifdef DMA 1 `else 0 `endif )
549 typedef TAdd#(DMA_master_num,1)
553 axi_fastslave_declarations
= """\
555 typedef TAdd#(LastGen_fastslave_num,1) Sdram_slave_num;
556 typedef TAdd#(Sdram_slave_num ,`ifdef SDRAM 1 `else 0 `endif )
558 typedef TAdd#(Sdram_cfg_slave_num,`ifdef BOOTROM 1 `else 0 `endif )
560 typedef TAdd#(BootRom_slave_num ,`ifdef Debug 1 `else 0 `endif )
562 typedef TAdd#(Debug_slave_num , `ifdef TCMemory 1 `else 0 `endif )
564 typedef TAdd#(TCM_slave_num ,`ifdef DMA 1 `else 0 `endif )
566 typedef TAdd#(Dma_slave_num ,1 ) SlowPeripheral_slave_num;
567 typedef TAdd#(SlowPeripheral_slave_num,`ifdef VME 1 `else 0 `endif )
569 typedef TAdd#(VME_slave_num,1) Num_Fast_Slaves;
572 axi_slave_declarations
= """\
573 typedef 0 SlowMaster;
575 typedef TAdd#(LastGen_slave_num,`ifdef CLINT 1 `else 0 `endif )
577 typedef TAdd#(CLINT_slave_num ,`ifdef PLIC 1 `else 0 `endif )
579 typedef TAdd#(Plic_slave_num ,`ifdef AXIEXP 1 `else 0 `endif )
581 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
584 pinmux_cellrule
= """\
585 rule connect_select_lines_pinmux;
591 class CallFn(object):
592 def __init__(self
, peripheral
, name
):
593 self
.peripheral
= peripheral
596 def __call__(self
, *args
):
597 #print "__call__", self.name, self.peripheral.slow, args
598 if not self
.peripheral
.slow
:
600 return getattr(self
.peripheral
.slow
, self
.name
)(*args
[1:])
603 class PeripheralIface(object):
604 def __init__(self
, ifacename
):
606 slow
= slowfactory
.getcls(ifacename
)
607 print "Iface", ifacename
, slow
609 self
.slow
= slow(ifacename
)
610 self
.slow
.peripheral
= self
611 for fname
in ['slowimport',
613 'extifinstance2', 'extifinstance', 'extifdecl',
614 'slowifdecl', 'slowifdeclmux',
617 'mk_dma_sync', 'mk_dma_connect', 'mk_dma_rule',
619 'mk_plic', 'mk_ext_ifacedef',
620 '_mk_clk_con', 'mk_ext_ifacedef',
621 'mk_connection', 'mk_master_connection',
622 'mk_cellconn', '_mk_pincon']:
623 fn
= CallFn(self
, fname
)
624 setattr(self
, fname
, types
.MethodType(fn
, self
))
626 #print "PeripheralIface"
629 def mksuffix(self
, name
, i
):
630 if self
.slow
is None:
632 return self
.slow
.mksuffix(name
, i
)
634 def axi_reg_def(self
, start
, count
):
637 return self
.slow
.axi_reg_def(start
, self
.ifacename
, count
)
639 def axi_master_idx(self
, start
, count
, typ
):
640 if not self
.slow
or not self
.slow
.has_axi_master():
642 return self
.slow
.axi_master_idx(start
, self
.ifacename
, count
, typ
)
644 def axi_slave_idx(self
, start
, count
, typ
):
647 return self
.slow
.axi_slave_idx(start
, self
.ifacename
, count
, typ
)
649 def axi_fastaddr_map(self
, count
):
652 return self
.slow
.axi_fastaddr_map(self
.ifacename
, count
)
654 def axi_addr_map(self
, count
):
657 return self
.slow
.axi_addr_map(self
.ifacename
, count
)
660 class PeripheralInterfaces(object):
662 self
.fastbusmode
= False
664 def slowimport(self
, *args
):
666 for (name
, count
) in self
.ifacecount
:
667 #print "slowimport", name, self.data[name].slowimport
668 ret
.append(self
.data
[name
].slowimport())
669 return '\n'.join(li(list(filter(None, ret
)), 4))
671 def extfastifinstance(self
, *args
):
673 for (name
, count
) in self
.ifacecount
:
674 for i
in range(count
):
675 iname
= self
.data
[name
].iname().format(i
)
676 print "extfast", iname
, self
.is_on_fastbus(name
, i
)
677 if self
.is_on_fastbus(name
, i
):
679 ret
.append(self
.data
[name
].extfastifinstance(name
, i
))
680 return '\n'.join(li(list(filter(None, ret
)), 8))
682 def extifinstance2(self
, *args
):
684 for (name
, count
) in self
.ifacecount
:
685 for i
in range(count
):
686 iname
= self
.data
[name
].iname().format(i
)
687 ret
.append(self
.data
[name
].extifinstance2(name
, i
))
688 return '\n'.join(li(list(filter(None, ret
)), 8))
690 def extifinstance(self
, *args
):
692 for (name
, count
) in self
.ifacecount
:
693 for i
in range(count
):
694 iname
= self
.data
[name
].iname().format(i
)
695 if not self
.is_on_fastbus(name
, i
):
697 ret
.append(self
.data
[name
].extifinstance(name
, i
))
698 return '\n'.join(li(list(filter(None, ret
)), 8))
700 def extifdecl(self
, *args
):
702 for (name
, count
) in self
.ifacecount
:
703 for i
in range(count
):
704 if not self
.is_on_fastbus(name
, i
):
706 ret
.append(self
.data
[name
].extifdecl(name
, i
))
707 return '\n'.join(li(list(filter(None, ret
)), 8))
709 def slowifdeclmux(self
, *args
):
711 for (name
, count
) in self
.ifacecount
:
712 for i
in range(count
):
713 ret
.append(self
.data
[name
].slowifdeclmux(name
, i
))
714 return '\n'.join(li(list(filter(None, ret
)), 8))
716 def fastifdecl(self
, *args
):
718 for (name
, count
) in self
.ifacecount
:
719 for i
in range(count
):
720 print "fastifdecl", name
, i
, self
.is_on_fastbus(name
, i
)
721 if self
.is_on_fastbus(name
, i
):
723 ret
.append(self
.data
[name
].fastifdecl(name
, i
))
724 return '\n'.join(li(list(filter(None, ret
)), 4))
726 def slowifdecl(self
, *args
):
728 for (name
, count
) in self
.ifacecount
:
729 for i
in range(count
):
730 if self
.is_on_fastbus(name
, i
):
732 ret
.append(self
.data
[name
].slowifdecl().format(i
, name
))
733 return '\n'.join(list(filter(None, ret
)))
735 def axi_fastmem_def(self
, *args
):
736 return self
._axi
_reg
_def
(0x50000000, *args
)
738 def axi_reg_def(self
, *args
):
739 return self
._axi
_reg
_def
(0x00011100, *args
)
741 def _axi_reg_def(self
, start
, *args
):
743 for (name
, count
) in self
.ifacecount
:
744 for i
in range(count
):
745 if self
.is_on_fastbus(name
, i
):
747 x
= self
.data
[name
].axi_reg_def(start
, i
)
748 #print ("ifc", name, x)
752 return '\n'.join(list(filter(None, ret
)))
754 def _axi_num_idx(self
, start
, template
, typ
, idxtype
, *args
):
756 for (name
, count
) in self
.ifacecount
:
757 for i
in range(count
):
758 if self
.is_on_fastbus(name
, i
):
761 fn
= self
.data
[name
].axi_master_idx
763 fn
= self
.data
[name
].axi_slave_idx
764 (rdef
, offs
) = fn(start
, i
, idxtype
)
765 #print ("ifc", name, rdef, offs)
768 ret
.append("typedef %d LastGen_%s_num;" % (start
- 1, typ
))
769 decls
= '\n'.join(list(filter(None, ret
)))
770 return template
.format(decls
)
772 def axi_slave_idx(self
, *args
):
773 return self
._axi
_num
_idx
(0, axi_slave_declarations
, 'slave',
776 def axi_fastslave_idx(self
, *args
):
777 return self
._axi
_num
_idx
(0, axi_fastslave_declarations
, 'fastslave',
780 def axi_master_idx(self
, *args
):
781 return self
._axi
_num
_idx
(2, axi_master_declarations
, 'master',
784 def axi_fastslave_idx(self
, *args
):
785 return self
._axi
_num
_idx
(0, axi_fastslave_declarations
, 'fastslave',
788 def axi_fastaddr_map(self
, *args
):
790 for (name
, count
) in self
.ifacecount
:
791 for i
in range(count
):
792 if self
.is_on_fastbus(name
, i
):
794 ret
.append(self
.data
[name
].axi_fastaddr_map(i
))
795 return '\n'.join(li(list(filter(None, ret
)), 8))
797 def axi_addr_map(self
, *args
):
799 for (name
, count
) in self
.ifacecount
:
800 for i
in range(count
):
801 if self
.is_on_fastbus(name
, i
):
803 ret
.append(self
.data
[name
].axi_addr_map(i
))
804 return '\n'.join(li(list(filter(None, ret
)), 8))
806 def mkfast_peripheral(self
, *args
):
808 for (name
, count
) in self
.ifacecount
:
809 for i
in range(count
):
810 if self
.is_on_fastbus(name
, i
):
812 #print "mkfast", name, count
813 x
= self
.data
[name
].mkfast_peripheral()
815 suffix
= self
.data
[name
].mksuffix(name
, i
)
816 ret
.append(x
.format(suffix
))
817 return '\n'.join(li(list(filter(None, ret
)), 8))
819 def mkslow_peripheral(self
, *args
):
821 for (name
, count
) in self
.ifacecount
:
822 for i
in range(count
):
823 if self
.is_on_fastbus(name
, i
):
825 #print "mkslow", name, count
826 x
= self
.data
[name
].mkslow_peripheral()
828 suffix
= self
.data
[name
].mksuffix(name
, i
)
829 ret
.append(x
.format(suffix
))
830 return '\n'.join(li(list(filter(None, ret
)), 8))
832 def _mk_connection(self
, fabric
, typ
, indent
, master
, *args
):
834 for (name
, count
) in self
.ifacecount
:
835 for i
in range(count
):
836 if self
.is_on_fastbus(name
, i
):
839 txt
= self
.data
[name
].mk_master_connection(i
, fabric
, typ
)
841 txt
= self
.data
[name
].mk_connection(i
, fabric
, typ
)
845 return '\n'.join(li(list(filter(None, ret
)), indent
))
847 def mk_master_connection(self
, *args
):
848 return self
._mk
_connection
("fabric", "fast", 8, True, *args
)
850 def mk_fast_connection(self
, *args
):
851 return self
._mk
_connection
("fabric", "fast", 12, False, *args
)
853 def mk_connection(self
, *args
):
854 return self
._mk
_connection
("slow_fabric", "", 8, False, *args
)
856 def mk_cellconn(self
):
859 for (name
, count
) in self
.ifacecount
:
860 for i
in range(count
):
861 if self
.is_on_fastbus(name
, i
):
863 res
= self
.data
[name
].mk_cellconn(cellcount
, name
, i
)
866 (txt
, cellcount
) = res
868 ret
= li('\n'.join(list(filter(None, ret
))), 4)
869 return li(pinmux_cellrule
.format(ret
), 4)
872 return self
._mk
_pincon
("slow")
874 def mk_fast_pincon(self
):
875 return self
._mk
_pincon
("fast")
877 def _mk_pincon(self
, typ
):
879 for (name
, count
) in self
.ifacecount
:
880 for i
in range(count
):
881 if self
.is_on_fastbus(name
, i
):
883 txt
= self
.data
[name
]._mk
_pincon
(name
, i
, typ
)
885 return '\n'.join(li(list(filter(None, ret
)), 4))
887 def mk_dma_irq(self
):
895 for (name
, count
) in self
.ifacecount
:
897 for i
in range(count
):
898 if not self
.is_on_fastbus(name
, i
):
900 txt
= self
.data
[name
].mk_dma_sync(name
, i
)
904 txt
= self
.data
[name
].mk_dma_rule(name
, i
)
905 ifacerules
.append(txt
)
906 txt
= self
.data
[name
].mk_dma_connect(name
, i
)
908 ifacerules
= list(filter(None, ifacerules
))
910 txt
= "rule synchronize_%s_interrupts;" % name
913 rules
.append("endrule")
915 cnct
= list(filter(None, cnct
))
917 _cnct
= ["rule rl_connect_interrupt_to_DMA;",
918 " Bit #(%d) lv_interrupt_to_DMA={" % ct
]
921 cnct
= _cnct
+ [spc
+ spcsep
.join(cnct
)]
923 cnct
.append(" dma.interrupt_from_peripherals(\n" +
924 " lv_interrupt_to_DMA);")
925 cnct
.append("endrule;")
927 ret
= list(filter(None, sync
+ rules
+ cnct
))
929 return '\n'.join(ret
)
931 def num_dmachannels(self
):
932 return "`define NUM_DMACHANNELS {0}".format(self
.dma_count
)
934 def mk_ext_ifacedef(self
):
936 for (name
, count
) in self
.ifacecount
:
937 for i
in range(count
):
938 if self
.is_on_fastbus(name
, i
):
940 txt
= self
.data
[name
].mk_ext_ifacedef(name
, i
)
942 return '\n'.join(li(list(filter(None, ret
)), 8))
946 irq_offs
= 8 # XXX: DMA scovers 0-7?
947 for (name
, count
) in self
.ifacecount
:
948 for i
in range(count
):
949 if self
.is_on_fastbus(name
, i
):
951 res
= self
.data
[name
].mk_plic(i
, irq_offs
)
954 (txt
, irq_offs
) = res
956 self
.num_slow_irqs
= irq_offs
957 return '\n'.join(li(list(filter(None, ret
)), 4))
959 def mk_sloirqsdef(self
):
960 return " `define NUM_SLOW_IRQS {0}".format(self
.num_slow_irqs
)
962 def mk_fastclk_con(self
):
963 return self
._mk
_clk
_con
("fast")
965 def mk_slowclk_con(self
):
966 return self
._mk
_clk
_con
("slow")
968 def _mk_clk_con(self
, ctype
):
970 for (name
, count
) in self
.ifacecount
:
971 for i
in range(count
):
972 if self
.is_on_fastbus(name
, i
):
974 txt
= self
.data
[name
]._mk
_clk
_con
(name
, i
, ctype
)
976 return '\n'.join(li(list(filter(None, ret
)), 8))
978 def is_on_fastbus(self
, name
, i
):
979 #print "fastbus mode", self.fastbusmode, name, i
980 iname
= self
.data
[name
].iname().format(i
)
982 return iname
not in self
.fastbus
983 return iname
in self
.fastbus
986 class PFactory(object):
987 def getcls(self
, name
):
988 from uart
import uart
989 from quart
import quart
990 from sdmmc
import sdmmc
992 from eint
import eint
993 from rs232
import rs232
995 from eint
import eint
996 from jtag
import jtag
997 from spi
import spi
, mspi
998 from qspi
import qspi
, mqspi
999 from gpio
import gpio
1000 from rgbttl
import rgbttl
1001 from flexbus
import flexbus
1002 from sdram
import sdram
1004 for k
, v
in {'uart': uart
,
1021 if name
.startswith(k
):
1026 slowfactory
= PFactory()
1028 if __name__
== '__main__':
1030 print p
.slowimport()
1031 print p
.slowifdecl()
1032 i
= PeripheralIface('uart')
1034 i
= PeripheralIface('gpioa')