7 if isinstance(txt
, str):
12 line
= line
.split('\n')
17 res
.append(indent
+ line
)
24 def __init__(self
, name
):
27 def extifdecl(self
, name
, count
):
28 sname
= self
.get_iname(count
)
29 return "interface PeripheralSide%s %s;" % (name
.upper(), sname
)
31 def has_axi_master(self
):
37 def mk_dma_irq(self
, name
, count
):
38 if not self
.irq_name():
40 sname
= self
.get_iname(count
)
41 return "{0}_interrupt".format(sname
)
43 def mk_dma_rule(self
, name
, count
):
44 irqname
= self
.mk_dma_irq(name
, count
)
47 pirqname
= self
.irq_name().format(count
)
48 template
= " {0}.send(\n" + \
49 " slow_peripherals.{1});"
50 return template
.format(irqname
, pirqname
)
52 def get_clock_reset(self
, name
, count
):
53 return "slow_clock,slow_reset"
55 def mk_dma_sync(self
, name
, count
):
56 irqname
= self
.mk_dma_irq(name
, count
)
59 sname
= self
.peripheral
.iname().format(count
)
60 template
= "SyncBitIfc#(Bit#(1)) {0} <-\n" + \
61 " <-mkSyncBitToCC({1});"
62 return template
.format(irqname
, self
.get_clock_reset(name
, count
))
64 def mk_dma_connect(self
, name
, count
):
65 irqname
= self
.mk_dma_irq(name
, count
)
68 return "{0}.read".format(irqname
)
70 def fastifdecl(self
, name
, count
):
73 def slowifdeclmux(self
, name
, count
):
79 def num_axi_regs32(self
):
85 def get_iname(self
, inum
):
86 return "{0}{1}".format(self
.name
, self
.mksuffix(self
.name
, inum
))
88 def axibase(self
, name
, ifacenum
):
90 return "%(name)s%(ifacenum)dBase" % locals()
92 def axiend(self
, name
, ifacenum
):
94 return "%(name)s%(ifacenum)dEnd" % locals()
96 def axi_reg_def(self
, start
, name
, ifacenum
):
98 offs
= self
.num_axi_regs32() * 4 * 16
101 end
= start
+ offs
- 1
102 bname
= self
.axibase(name
, ifacenum
)
103 bend
= self
.axiend(name
, ifacenum
)
104 comment
= "%d 32-bit regs" % self
.num_axi_regs32()
105 return (" `define %(bname)s 'h%(start)08X\n"
106 " `define %(bend)s 'h%(end)08X // %(comment)s" % locals(),
109 def axi_master_name(self
, name
, ifacenum
, typ
=''):
111 return "{0}{1}_master_num".format(name
, ifacenum
)
113 def axi_slave_name(self
, name
, ifacenum
, typ
=''):
115 return "{0}{1}_{2}slave_num".format(name
, ifacenum
, typ
)
117 def axi_master_idx(self
, idx
, name
, ifacenum
, typ
):
118 name
= self
.axi_master_name(name
, ifacenum
, typ
)
119 return ("typedef {0} {1};".format(idx
, name
), 1)
121 def axi_slave_idx(self
, idx
, name
, ifacenum
, typ
):
122 name
= self
.axi_slave_name(name
, ifacenum
, typ
)
123 return ("typedef {0} {1};".format(idx
, name
), 1)
125 def axi_fastaddr_map(self
, name
, ifacenum
):
126 return self
.axi_addr_map(name
, ifacenum
, 'fast')
128 def axi_addr_map(self
, name
, ifacenum
, typ
=""):
129 bname
= self
.axibase(name
, ifacenum
)
130 bend
= self
.axiend(name
, ifacenum
)
131 name
= self
.axi_slave_name(name
, ifacenum
, typ
)
133 if(addr>=`{0} && addr<=`{1})
134 return tuple2(True,fromInteger(valueOf({2})));
136 return template
.format(bname
, bend
, name
)
138 def _mk_pincon(self
, name
, count
, ptyp
):
139 # TODO: really should be using bsv.interface_decl.Interfaces
140 # pin-naming rules.... logic here is hard-coded to duplicate
141 # it (see Interface.__init__ outen)
143 for p
in self
.peripheral
.pinspecs
:
146 #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
147 n
= name
# "{0}{1}".format(self.name, self.mksuffix(name, count))
148 ret
.append("//%s %s" % (n
, str(p
)))
150 sname
= self
.get_iname(count
)
151 sname
= "{0}.{1}".format(sname
, pname
)
152 ps
= "slow_peripherals.%s" % sname
154 sname
= self
.peripheral
.iname().format(count
)
155 sname
= "{0}.{1}".format(sname
, pname
)
156 ps
= "pinmux.peripheral_side.%s" % sname
157 if typ
== 'out' or typ
== 'inout':
158 fname
= self
.pinname_out(pname
)
159 if not n
.startswith('gpio'): # XXX EURGH! horrible hack
160 n_
= "{0}{1}".format(n
, count
)
168 cn
= self
._mk
_actual
_connection
('out', name
,
170 pname
, ps_
, n_
, fname
)
174 fname
= self
.pinname_outen(pname
)
176 if isinstance(fname
, str):
177 fname
= "{0}.{1}".format(n_
, fname
)
178 fname
= self
.pinname_tweak(pname
, 'outen', fname
)
179 cn
= self
._mk
_actual
_connection
('outen', name
,
183 if typ
== 'in' or typ
== 'inout':
184 fname
= self
.pinname_in(pname
)
190 n_
= "{0}{1}".format(n
, count
)
191 n_
= '{0}.{1}'.format(n_
, fname
)
192 n_
= self
.ifname_tweak(pname
, 'in', n_
)
193 cn
= self
._mk
_actual
_connection
('in', name
,
195 pname
, ps_
, n_
, fname
)
197 return '\n'.join(ret
)
199 def _mk_vpincon(self
, name
, count
, ptyp
, typ
, pname
, stype
=None):
204 sname
= self
.get_iname(count
)
205 ps
= "slow_peripherals.%s" % sname
207 sname
= self
.peripheral
.iname().format(count
)
208 ps
= "pinmux.peripheral_side.%s" % sname
209 n
= self
.get_iname(count
)
210 ps_
= "{0}.{1}".format(ps
, pname
)
211 ret
+= self
._mk
_actual
_connection
(typ
, name
, count
, typ
,
212 pname
, ps_
, n
, stype
)
213 return '\n'.join(ret
)
215 def _mk_actual_connection(self
, ctype
, name
, count
, typ
,
216 pname
, ps
, n
, fname
):
218 ck
= self
.get_clock_reset(name
, count
)
220 if ck
== PBase
.get_clock_reset(self
, name
, count
):
221 ret
.append("mkConnection({0},\n\t\t\t{1}.{2});"
222 .format(ps
, n
, fname
))
224 n2
= "{0}{1}".format(name
, count
)
225 sync
= '{0}_{1}_sync'.format(n2
, pname
)
226 ret
.append("mkConnection({0},\n\t\t\t{1}.get);"
228 ret
.append("mkConnection({0}.put,\n\t\t\t{1}.{2});"
229 .format(sync
, n
, fname
))
230 elif ctype
== 'outen':
231 ret
.append("mkConnection({0}_outen,\n\t\t\t{1});"
234 if ck
== PBase
.get_clock_reset(self
, name
, count
):
235 ret
.append("mkConnection({1},\n\t\t\t{0});".format(
238 n2
= "{0}{1}".format(name
, count
)
239 sync
= '{0}_{1}_sync'.format(n2
, pname
)
240 ret
.append("mkConnection({1}.put,\n\t\t\t{0});".format(
242 ret
.append("mkConnection({1},\n\t\t\t{0}.get);".format(
247 def _mk_clk_con(self
, name
, count
, ctype
):
249 ck
= self
.get_clock_reset(name
, count
)
250 if ck
== PBase
.get_clock_reset(self
, name
, count
):
253 spc
= "sp_clock, sp_reset"
256 ck
= "core_clock, core_reset"
258 Ifc_sync#({0}) {1}_sync <-mksyncconnection(
260 for p
in self
.peripheral
.pinspecs
:
264 if typ
== 'out' or typ
== 'inout':
265 fname
= self
.pinname_out(pname
)
268 if not n
.startswith('gpio'): # XXX EURGH! horrible hack
269 n_
= "{0}{1}".format(n
, count
)
272 n_
= '{0}_{1}'.format(n_
, pname
)
273 ret
.append(template
.format("Bit#(1)", n_
, ck
, spc
))
274 if typ
== 'in' or typ
== 'inout':
275 fname
= self
.pinname_in(pname
)
278 #fname = self.pinname_in(pname)
279 n_
= "{0}{1}".format(n
, count
)
280 n_
= '{0}_{1}'.format(n_
, pname
)
281 #n_ = self.ifname_tweak(pname, 'in', n_)
282 ret
.append(template
.format("Bit#(1)", n_
, spc
, ck
))
283 return '\n'.join(ret
)
285 def _mk_clk_vcon(self
, name
, count
, ctype
, typ
, pname
, bitspec
):
286 ck
= self
.get_clock_reset(name
, count
)
287 if ck
== PBase
.get_clock_reset(self
, name
, count
):
290 spc
= "sp_clock, sp_reset"
293 ck
= "core_clock, core_reset"
295 Ifc_sync#({0}) {1}_sync <-mksyncconnection(
298 n_
= "{0}{1}".format(name
, count
)
299 n_
= '{0}_{1}'.format(n_
, pname
)
300 return template
.format(bitspec
, n_
, ck
, spc
)
303 def mk_cellconn(self
, *args
):
306 def mkfast_peripheral(self
, size
=0):
309 def mkslow_peripheral(self
, size
=0):
312 def mksuffix(self
, name
, i
):
315 def __mk_connection(self
, con
, aname
, fabricname
):
316 txt
= "mkConnection ({2}.v_to_slaves\n" + \
317 " [fromInteger(valueOf({1}))],\n" + \
320 print "PBase __mk_connection", self
.name
, aname
323 return txt
.format(con
, aname
, fabricname
)
325 def __mk_master_connection(self
, con
, aname
):
326 txt
= "mkConnection (slow_fabric.v_to_slaves\n" + \
327 " [fromInteger(valueOf({1}))],\n" + \
330 print "PBase __mk_connection", self
.name
, aname
333 return txt
.format(con
, aname
)
335 def mk_connection(self
, count
, fabricname
, typ
, name
=None):
338 print "PBase mk_conn", self
.name
, count
339 aname
= self
.axi_slave_name(name
, count
, typ
)
340 #dname = self.mksuffix(name, count)
341 #dname = "{0}{1}".format(name, dname)
342 con
= self
._mk
_connection
(name
, count
).format(count
, aname
)
343 return self
.__mk
_connection
(con
, aname
, fabricname
)
345 def _mk_connection(self
, name
=None, count
=0):
348 def pinname_out(self
, pname
):
351 def pinname_in(self
, pname
):
354 def pinname_outen(self
, pname
):
357 def ifname_tweak(self
, pname
, typ
, txt
):
360 def pinname_tweak(self
, pname
, typ
, txt
):
366 def mk_plic(self
, inum
, irq_offs
):
368 print "mk_plic", self
.name
, inum
, irq_offs
369 niq
= self
.num_irqs()
371 return ('', irq_offs
)
372 name
= self
.get_iname(inum
)
373 res
.append("// PLIC rules for {0}".format(name
))
374 for idx
in range(niq
):
375 plic_obj
= self
.plic_object(name
, idx
)
376 print "plic_obj", name
, idx
, plic_obj
377 plic
= mkplic_rule
.format(name
, plic_obj
, irq_offs
)
379 irq_offs
+= 1 # increment to next irq
380 return ('\n'.join(res
), irq_offs
)
382 def mk_ext_ifacedef(self
, iname
, inum
):
385 def extfastifinstance(self
, name
, count
):
388 def _extifinstance(self
, name
, count
, suffix
, prefix
, samename
=False,
392 pname
= self
.get_iname(count
)
396 sname
= self
.peripheral
.iname().format(count
)
397 template
= "interface {0}{3} = {2}{1}{4};"
398 return template
.format(pname
, sname
, prefix
, suffix
, ifsuffix
)
400 def extifinstance2(self
, name
, count
):
403 def extifinstance(self
, name
, count
):
404 return self
._extifinstance
(name
, count
, "",
405 "pinmux.peripheral_side.")
409 rule rl_connect_{0}_to_plic_{2};
410 if({1} == 1'b1) begin
411 ff_gateway_queue[{2}].enq(1);
412 plic.ifc_external_irq[{2}].irq_frm_gateway(True);
417 axi_master_declarations
= """\
418 typedef 0 Dmem_master_num;
419 typedef 1 Imem_master_num;
421 typedef TAdd#(LastGen_master_num, `ifdef Debug 1 `else 0 `endif )
423 typedef TAdd#(Debug_master_num, `ifdef DMA 1 `else 0 `endif )
425 typedef TAdd#(DMA_master_num,1)
429 axi_fastslave_declarations
= """\
431 typedef TAdd#(LastGen_fastslave_num,1) Sdram_slave_num;
432 typedef TAdd#(Sdram_slave_num ,`ifdef SDRAM 1 `else 0 `endif )
434 typedef TAdd#(Sdram_cfg_slave_num,`ifdef BOOTROM 1 `else 0 `endif )
436 typedef TAdd#(BootRom_slave_num ,`ifdef Debug 1 `else 0 `endif )
438 typedef TAdd#(Debug_slave_num , `ifdef TCMemory 1 `else 0 `endif )
440 typedef TAdd#(TCM_slave_num ,`ifdef DMA 1 `else 0 `endif )
442 typedef TAdd#(Dma_slave_num ,1 ) SlowPeripheral_slave_num;
443 typedef TAdd#(SlowPeripheral_slave_num,`ifdef VME 1 `else 0 `endif )
445 typedef TAdd#(VME_slave_num,1) Num_Fast_Slaves;
448 axi_slave_declarations
= """\
449 typedef 0 SlowMaster;
451 typedef TAdd#(LastGen_slave_num,`ifdef CLINT 1 `else 0 `endif )
453 typedef TAdd#(CLINT_slave_num ,`ifdef PLIC 1 `else 0 `endif )
455 typedef TAdd#(Plic_slave_num ,`ifdef AXIEXP 1 `else 0 `endif )
457 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
460 pinmux_cellrule
= """\
461 rule connect_select_lines_pinmux;
467 class CallFn(object):
468 def __init__(self
, peripheral
, name
):
469 self
.peripheral
= peripheral
472 def __call__(self
, *args
):
473 #print "__call__", self.name, self.peripheral.slow, args
474 if not self
.peripheral
.slow
:
476 return getattr(self
.peripheral
.slow
, self
.name
)(*args
[1:])
479 class PeripheralIface(object):
480 def __init__(self
, ifacename
):
482 slow
= slowfactory
.getcls(ifacename
)
483 print "Iface", ifacename
, slow
485 self
.slow
= slow(ifacename
)
486 self
.slow
.peripheral
= self
487 for fname
in ['slowimport',
489 'extifinstance2', 'extifinstance', 'extifdecl',
490 'slowifdecl', 'slowifdeclmux',
493 'mk_dma_sync', 'mk_dma_connect', 'mk_dma_rule',
495 'mk_plic', 'mk_ext_ifacedef',
496 '_mk_clk_con', 'mk_ext_ifacedef',
497 'mk_connection', 'mk_cellconn', '_mk_pincon']:
498 fn
= CallFn(self
, fname
)
499 setattr(self
, fname
, types
.MethodType(fn
, self
))
501 #print "PeripheralIface"
504 def mksuffix(self
, name
, i
):
505 if self
.slow
is None:
507 return self
.slow
.mksuffix(name
, i
)
509 def axi_reg_def(self
, start
, count
):
512 return self
.slow
.axi_reg_def(start
, self
.ifacename
, count
)
514 def axi_master_idx(self
, start
, count
, typ
):
515 if not self
.slow
or not self
.slow
.has_axi_master():
517 return self
.slow
.axi_master_idx(start
, self
.ifacename
, count
, typ
)
519 def axi_slave_idx(self
, start
, count
, typ
):
522 return self
.slow
.axi_slave_idx(start
, self
.ifacename
, count
, typ
)
524 def axi_fastaddr_map(self
, count
):
527 return self
.slow
.axi_fastaddr_map(self
.ifacename
, count
)
529 def axi_addr_map(self
, count
):
532 return self
.slow
.axi_addr_map(self
.ifacename
, count
)
535 class PeripheralInterfaces(object):
537 self
.fastbusmode
= False
539 def slowimport(self
, *args
):
541 for (name
, count
) in self
.ifacecount
:
542 #print "slowimport", name, self.data[name].slowimport
543 ret
.append(self
.data
[name
].slowimport())
544 return '\n'.join(li(list(filter(None, ret
)), 4))
546 def extfastifinstance(self
, *args
):
548 for (name
, count
) in self
.ifacecount
:
549 for i
in range(count
):
550 iname
= self
.data
[name
].iname().format(i
)
551 print "extfast", iname
, self
.is_on_fastbus(name
, i
)
552 if self
.is_on_fastbus(name
, i
):
554 ret
.append(self
.data
[name
].extfastifinstance(name
, i
))
555 return '\n'.join(li(list(filter(None, ret
)), 8))
557 def extifinstance2(self
, *args
):
559 for (name
, count
) in self
.ifacecount
:
560 for i
in range(count
):
561 iname
= self
.data
[name
].iname().format(i
)
562 ret
.append(self
.data
[name
].extifinstance2(name
, i
))
563 return '\n'.join(li(list(filter(None, ret
)), 8))
565 def extifinstance(self
, *args
):
567 for (name
, count
) in self
.ifacecount
:
568 for i
in range(count
):
569 iname
= self
.data
[name
].iname().format(i
)
570 if not self
.is_on_fastbus(name
, i
):
572 ret
.append(self
.data
[name
].extifinstance(name
, i
))
573 return '\n'.join(li(list(filter(None, ret
)), 8))
575 def extifdecl(self
, *args
):
577 for (name
, count
) in self
.ifacecount
:
578 for i
in range(count
):
579 if not self
.is_on_fastbus(name
, i
):
581 ret
.append(self
.data
[name
].extifdecl(name
, i
))
582 return '\n'.join(li(list(filter(None, ret
)), 8))
584 def slowifdeclmux(self
, *args
):
586 for (name
, count
) in self
.ifacecount
:
587 for i
in range(count
):
588 ret
.append(self
.data
[name
].slowifdeclmux(name
, i
))
589 return '\n'.join(li(list(filter(None, ret
)), 8))
591 def fastifdecl(self
, *args
):
593 for (name
, count
) in self
.ifacecount
:
594 for i
in range(count
):
595 print "fastifdecl", name
, i
, self
.is_on_fastbus(name
, i
)
596 if self
.is_on_fastbus(name
, i
):
598 ret
.append(self
.data
[name
].fastifdecl(name
, i
))
599 return '\n'.join(li(list(filter(None, ret
)), 4))
601 def slowifdecl(self
, *args
):
603 for (name
, count
) in self
.ifacecount
:
604 for i
in range(count
):
605 if self
.is_on_fastbus(name
, i
):
607 ret
.append(self
.data
[name
].slowifdecl().format(i
, name
))
608 return '\n'.join(list(filter(None, ret
)))
610 def axi_fastmem_def(self
, *args
):
611 return self
._axi
_reg
_def
(0x50000000, *args
)
613 def axi_reg_def(self
, *args
):
614 return self
._axi
_reg
_def
(0x00011100, *args
)
616 def _axi_reg_def(self
, start
, *args
):
618 for (name
, count
) in self
.ifacecount
:
619 for i
in range(count
):
620 if self
.is_on_fastbus(name
, i
):
622 x
= self
.data
[name
].axi_reg_def(start
, i
)
623 #print ("ifc", name, x)
627 return '\n'.join(list(filter(None, ret
)))
629 def _axi_num_idx(self
, start
, template
, typ
, idxtype
, *args
):
631 for (name
, count
) in self
.ifacecount
:
632 for i
in range(count
):
633 if self
.is_on_fastbus(name
, i
):
636 fn
= self
.data
[name
].axi_master_idx
638 fn
= self
.data
[name
].axi_slave_idx
639 (rdef
, offs
) = fn(start
, i
, idxtype
)
640 #print ("ifc", name, rdef, offs)
643 ret
.append("typedef %d LastGen_%s_num;" % (start
- 1, typ
))
644 decls
= '\n'.join(list(filter(None, ret
)))
645 return template
.format(decls
)
647 def axi_slave_idx(self
, *args
):
648 return self
._axi
_num
_idx
(0, axi_slave_declarations
, 'slave',
651 def axi_fastslave_idx(self
, *args
):
652 return self
._axi
_num
_idx
(0, axi_fastslave_declarations
, 'fastslave',
655 def axi_master_idx(self
, *args
):
656 return self
._axi
_num
_idx
(2, axi_master_declarations
, 'master',
659 def axi_fastslave_idx(self
, *args
):
660 return self
._axi
_num
_idx
(0, axi_fastslave_declarations
, 'fastslave',
663 def axi_fastaddr_map(self
, *args
):
665 for (name
, count
) in self
.ifacecount
:
666 for i
in range(count
):
667 if self
.is_on_fastbus(name
, i
):
669 ret
.append(self
.data
[name
].axi_fastaddr_map(i
))
670 return '\n'.join(li(list(filter(None, ret
)), 8))
672 def axi_addr_map(self
, *args
):
674 for (name
, count
) in self
.ifacecount
:
675 for i
in range(count
):
676 if self
.is_on_fastbus(name
, i
):
678 ret
.append(self
.data
[name
].axi_addr_map(i
))
679 return '\n'.join(li(list(filter(None, ret
)), 8))
681 def mkfast_peripheral(self
, *args
):
683 for (name
, count
) in self
.ifacecount
:
684 for i
in range(count
):
685 if self
.is_on_fastbus(name
, i
):
687 #print "mkfast", name, count
688 x
= self
.data
[name
].mkfast_peripheral()
690 suffix
= self
.data
[name
].mksuffix(name
, i
)
691 ret
.append(x
.format(suffix
))
692 return '\n'.join(li(list(filter(None, ret
)), 8))
694 def mkslow_peripheral(self
, *args
):
696 for (name
, count
) in self
.ifacecount
:
697 for i
in range(count
):
698 if self
.is_on_fastbus(name
, i
):
700 #print "mkslow", name, count
701 x
= self
.data
[name
].mkslow_peripheral()
703 suffix
= self
.data
[name
].mksuffix(name
, i
)
704 ret
.append(x
.format(suffix
))
705 return '\n'.join(li(list(filter(None, ret
)), 8))
707 def mk_fast_connection(self
, *args
):
709 for (name
, count
) in self
.ifacecount
:
710 for i
in range(count
):
711 if self
.is_on_fastbus(name
, i
):
713 txt
= self
.data
[name
].mk_connection(i
, "fabric", "fast")
716 print self
.data
[name
].mk_connection
718 return '\n'.join(li(list(filter(None, ret
)), 12))
720 def mk_connection(self
, *args
):
722 for (name
, count
) in self
.ifacecount
:
723 for i
in range(count
):
724 if self
.is_on_fastbus(name
, i
):
726 txt
= self
.data
[name
].mk_connection(i
, "slow_fabric", "")
729 print self
.data
[name
].mk_connection
731 return '\n'.join(li(list(filter(None, ret
)), 8))
733 def mk_cellconn(self
):
736 for (name
, count
) in self
.ifacecount
:
737 for i
in range(count
):
738 if self
.is_on_fastbus(name
, i
):
740 res
= self
.data
[name
].mk_cellconn(cellcount
, name
, i
)
743 (txt
, cellcount
) = res
745 ret
= li('\n'.join(list(filter(None, ret
))), 4)
746 return li(pinmux_cellrule
.format(ret
), 4)
749 return self
._mk
_pincon
("slow")
751 def mk_fast_pincon(self
):
752 return self
._mk
_pincon
("fast")
754 def _mk_pincon(self
, typ
):
756 for (name
, count
) in self
.ifacecount
:
757 for i
in range(count
):
758 if self
.is_on_fastbus(name
, i
):
760 txt
= self
.data
[name
]._mk
_pincon
(name
, i
, typ
)
762 return '\n'.join(li(list(filter(None, ret
)), 4))
764 def mk_dma_irq(self
):
772 for (name
, count
) in self
.ifacecount
:
774 for i
in range(count
):
775 if not self
.is_on_fastbus(name
, i
):
777 txt
= self
.data
[name
].mk_dma_sync(name
, i
)
781 txt
= self
.data
[name
].mk_dma_rule(name
, i
)
782 ifacerules
.append(txt
)
783 txt
= self
.data
[name
].mk_dma_connect(name
, i
)
785 ifacerules
= list(filter(None, ifacerules
))
787 txt
= "rule synchronize_%s_interrupts;" % name
790 rules
.append("endrule")
792 cnct
= list(filter(None, cnct
))
794 _cnct
= ["rule rl_connect_interrupt_to_DMA;",
795 " Bit #(%d) lv_interrupt_to_DMA={" % ct
]
798 cnct
= _cnct
+ [spc
+ spcsep
.join(cnct
)]
800 cnct
.append(" dma.interrupt_from_peripherals(\n" +
801 " lv_interrupt_to_DMA);")
802 cnct
.append("endrule;")
804 ret
= list(filter(None, sync
+ rules
+ cnct
))
806 return '\n'.join(ret
)
808 def num_dmachannels(self
):
809 return "`define NUM_DMACHANNELS {0}".format(self
.dma_count
)
811 def mk_ext_ifacedef(self
):
813 for (name
, count
) in self
.ifacecount
:
814 for i
in range(count
):
815 if self
.is_on_fastbus(name
, i
):
817 txt
= self
.data
[name
].mk_ext_ifacedef(name
, i
)
819 return '\n'.join(li(list(filter(None, ret
)), 8))
823 irq_offs
= 8 # XXX: DMA scovers 0-7?
824 for (name
, count
) in self
.ifacecount
:
825 for i
in range(count
):
826 if self
.is_on_fastbus(name
, i
):
828 res
= self
.data
[name
].mk_plic(i
, irq_offs
)
831 (txt
, irq_offs
) = res
833 self
.num_slow_irqs
= irq_offs
834 return '\n'.join(li(list(filter(None, ret
)), 4))
836 def mk_sloirqsdef(self
):
837 return " `define NUM_SLOW_IRQS {0}".format(self
.num_slow_irqs
)
839 def mk_fastclk_con(self
):
840 return self
._mk
_clk
_con
("fast")
842 def mk_slowclk_con(self
):
843 return self
._mk
_clk
_con
("slow")
845 def _mk_clk_con(self
, ctype
):
847 for (name
, count
) in self
.ifacecount
:
848 for i
in range(count
):
849 if self
.is_on_fastbus(name
, i
):
851 txt
= self
.data
[name
]._mk
_clk
_con
(name
, i
, ctype
)
853 return '\n'.join(li(list(filter(None, ret
)), 8))
855 def is_on_fastbus(self
, name
, i
):
856 #print "fastbus mode", self.fastbusmode, name, i
857 iname
= self
.data
[name
].iname().format(i
)
859 return iname
not in self
.fastbus
860 return iname
in self
.fastbus
863 class PFactory(object):
864 def getcls(self
, name
):
865 from uart
import uart
866 from quart
import quart
867 from sdmmc
import sdmmc
869 from eint
import eint
870 from rs232
import rs232
872 from eint
import eint
873 from jtag
import jtag
874 from spi
import spi
, mspi
875 from qspi
import qspi
, mqspi
876 from gpio
import gpio
877 from rgbttl
import rgbttl
878 from flexbus
import flexbus
880 for k
, v
in {'uart': uart
,
896 if name
.startswith(k
):
901 slowfactory
= PFactory()
903 if __name__
== '__main__':
907 i
= PeripheralIface('uart')
909 i
= PeripheralIface('gpioa')