4725496e33156a6bfc5385a63fc30b61f15bf33d
1 from bsv
.peripheral_gen
.base
import PBase
7 return "import FlexBus_Types::*;"
9 def num_axi_regs32(self
):
10 return 0x400000 # defines an entire memory range
12 def extfastifinstance(self
, name
, count
):
13 return "// TODO" + self
._extifinstance
(name
, count
, "_out", "", True,
16 def fastifdecl(self
, name
, count
):
17 return "//interface FlexBus_Master_IFC fb{0}_out;".format(count
)
19 def get_clock_reset(self
, name
, count
):
20 return "slow_clock, slow_reset"
22 def mkfast_peripheral(self
):
23 return "AXI4_Slave_to_FlexBus_Master_Xactor_IFC " + \
24 "#(`PADDR, `DATA, `USERSPACE)\n" + \
25 " fb{0} <- mkAXI4_Slave_to_FlexBus_Master_Xactor;"
27 def _mk_connection(self
, name
=None, count
=0):
28 return "fb{0}.axi_side"
30 def pinname_in(self
, pname
):
31 return {'ta': 'flexbus_side.m_tAn',
34 def pinname_out(self
, pname
):
35 return {'ale': 'flexbus_side.m_ALE',
36 'oe': 'flexbus_side.m_OEn',
37 'tbst': 'flexbus_side.m_TBSTn',
38 'rw': 'flexbus_side.m_R_Wn',
41 def _mk_clk_con(self
, name
, count
, ctype
):
42 ret
= [PBase
._mk
_clk
_con
(self
, name
, count
, ctype
)]
43 for pname
, sz
, ptype
in [
47 ('ad_out', 32, 'out'),
49 ('ad_out_en', 32, 'out'),
51 bitspec
= "Bit#(%d)" % sz
52 txt
= self
._mk
_clk
_vcon
(name
, count
, ctype
, ptype
, pname
, bitspec
)
56 def _mk_pincon(self
, name
, count
, typ
):
57 ret
= [PBase
._mk
_pincon
(self
, name
, count
, typ
)]
58 assert typ
== 'fast' # TODO slow?
59 for pname
, stype
, ptype
in [
60 ('cs', 'm_FBCSn', 'out'),
61 ('bwe', 'm_BWEn', 'out'),
62 ('tsiz', 'm_TSIZ', 'out'),
63 ('ad_out', 'm_AD', 'out'),
64 ('ad_in', 'm_din', 'in'),
65 ('ad_out_en', 'm_OE32n', 'out'),
67 ret
.append(self
._mk
_vpincon
(name
, count
, typ
, ptype
, pname
,
68 "flexbus_side.{0}".format(stype
)))