9b6b1e3525cf9f966b7e4885cdb60c5d25328670
1 from bsv
.peripheral_gen
.base
import PBase
7 return "import quart :: *;"
10 return "quart{0}_intr"
13 return "interface QUART_AXI4_Lite_Ifc quart{0};\n" + \
14 "method Bit#(1) %s;" % self
.irq_name()
16 def get_clock_reset(self
, name
, count
):
17 return "slow_clock,slow_reset" # XXX TODO: change to uart_clock/reset
19 def num_axi_regs32(self
):
22 def mkslow_peripheral(self
, size
=0):
23 return "// XXX TODO: change to uart_clock/reset\n" + \
24 "QUART_AXI4_Lite_Ifc quart{0} <- \n" + \
25 " mkUart16550(clocked_by sp_clock,\n" + \
26 " reset_by sp_reset, sp_clock, sp_reset);"
28 def _mk_connection(self
, name
=None, count
=0):
29 return "quart{0}.slave"
31 def pinname_out(self
, pname
):
32 return {'tx': 'out.stx_out',
36 def pinname_in(self
, pname
):
37 return {'rx': 'out.srx_in',
41 def __disabled_mk_pincon(self
, name
, count
):
42 ret
= [PBase
.mk_pincon(self
, name
, count
)]
43 ret
.append("rule con_%s%d_io_in;" % (name
, count
))
44 ret
.append(" {0}{1}.out.modem_input(".format(name
, count
))
45 for idx
, pname
in enumerate(['rx', 'cts']):
46 sname
= self
.peripheral
.pname(pname
).format(count
)
47 ps
= "pinmux.peripheral_side.%s" % sname
48 ret
.append(" {0},".format(ps
))
49 ret
.append(" 1'b1,1'b0,1'b1")
58 def plic_object(self
, pname
, idx
):
59 return "{0}_interrupt.read".format(pname
)
61 def mk_plic(self
, inum
, irq_offs
):
62 name
= self
.get_iname(inum
)
63 ret
= [uart_plic_template
.format(name
, irq_offs
)]
64 (ret2
, irq_offs
) = PBase
.mk_plic(self
, inum
, irq_offs
)
66 return ('\n'.join(ret
), irq_offs
)
68 def mk_ext_ifacedef(self
, iname
, inum
):
69 name
= self
.get_iname(inum
)
70 return "method {0}_intr = {0}.irq;".format(name
)
72 def slowifdeclmux(self
, name
, count
):
73 sname
= self
.peripheral
.iname().format(count
)
74 return "method Bit#(1) %s_intr;" % sname
77 uart_plic_template
= """\
78 // PLIC {0} synchronisation with irq {1}
79 SyncBitIfc#(Bit#(1)) {0}_interrupt <-
80 mkSyncBitToCC(sp_clock, uart_reset);
81 rule plic_synchronize_{0}_interrupt_{1};
82 {0}_interrupt.send({0}.irq);