9cdf1fdb9cde827fbdd503acb635fdde952cd3c0
1 from bsv
.peripheral_gen
.base
import PBase
7 return "import sdr_top::*;"
9 def num_axi_regs32(self
):
10 return 0x400000 # defines an entire memory range
12 def extfastifinstance(self
, name
, count
):
13 return "// TODO" + self
._extifinstance
(name
, count
, "_out", "", True,
16 def fastifdecl(self
, name
, count
):
17 return "// (*always_ready*) interface " + \
18 "Ifc_sdram_out sdr{0}_out;".format(count
)
20 def get_clock_reset(self
, name
, count
):
21 return "slow_clock, slow_reset"
23 def mkfast_peripheral(self
):
24 return "Ifc_sdr_slave sdr{0} <- mksdr_axi4_slave(clk0);"
26 def _mk_connection(self
, name
=None, count
=0):
27 return "sdr{0}.axi_side"
29 def pinname_in(self
, pname
):
30 return {'ta': 'sdram_side.m_tAn',
33 def pinname_out(self
, pname
):
34 return {'ale': 'sdram_side.m_ALE',
35 'oe': 'sdram_side.m_OEn',
36 'tbst': 'sdram_side.m_TBSTn',
37 'rw': 'sdram_side.m_R_Wn',
40 def _mk_clk_con(self
, name
, count
, ctype
):
41 ret
= [PBase
._mk
_clk
_con
(self
, name
, count
, ctype
)]
42 for pname
, sz
, ptype
in [
46 ('ad_out', 32, 'out'),
48 ('ad_out_en', 32, 'out'),
50 bitspec
= "Bit#(%d)" % sz
51 txt
= self
._mk
_clk
_vcon
(name
, count
, ctype
, ptype
, pname
, bitspec
)
55 def _mk_pincon(self
, name
, count
, typ
):
56 ret
= [PBase
._mk
_pincon
(self
, name
, count
, typ
)]
57 assert typ
== 'fast' # TODO slow?
58 for pname
, stype
, ptype
in [
59 ('cs', 'm_FBCSn', 'out'),
60 ('bwe', 'm_BWEn', 'out'),
61 ('tsiz', 'm_TSIZ', 'out'),
62 ('ad_out', 'm_AD', 'out'),
63 ('ad_in', 'm_din', 'in'),
64 ('ad_out_en', 'm_OE32n', 'out'),
66 ret
.append(self
._mk
_vpincon
(name
, count
, typ
, ptype
, pname
,
67 "sdram_side.{0}".format(stype
)))