cc6c0bdf49215bd2dc0b19f1aef56f5ae4348e14
1 from bsv
.peripheral_gen
.base
import PBase
7 return "import sdr_top::*;"
9 def num_axi_regs32(self
):
10 return 0x400000 # defines an entire memory range
12 def extfastifinstance(self
, name
, count
):
13 return "// TODO" + self
._extifinstance
(name
, count
, "_out", "", True,
16 def fastifdecl(self
, name
, count
):
17 return "//interface FlexBus_Master_IFC sdr{0}_out;".format(count
)
19 def get_clock_reset(self
, name
, count
):
20 return "slow_clock, slow_reset"
22 def mkfast_peripheral(self
):
23 return "Ifc_sdr_slave sdr{0} <- mksdr_axi4_slave(clk0);"
25 def _mk_connection(self
, name
=None, count
=0):
26 return "sdr{0}.axi_side"
28 def pinname_in(self
, pname
):
29 return {'ta': 'sdram_side.m_tAn',
32 def pinname_out(self
, pname
):
33 return {'ale': 'sdram_side.m_ALE',
34 'oe': 'sdram_side.m_OEn',
35 'tbst': 'sdram_side.m_TBSTn',
36 'rw': 'sdram_side.m_R_Wn',
39 def _mk_clk_con(self
, name
, count
, ctype
):
40 ret
= [PBase
._mk
_clk
_con
(self
, name
, count
, ctype
)]
41 for pname
, sz
, ptype
in [
45 ('ad_out', 32, 'out'),
47 ('ad_out_en', 32, 'out'),
49 bitspec
= "Bit#(%d)" % sz
50 txt
= self
._mk
_clk
_vcon
(name
, count
, ctype
, ptype
, pname
, bitspec
)
54 def _mk_pincon(self
, name
, count
, typ
):
55 ret
= [PBase
._mk
_pincon
(self
, name
, count
, typ
)]
56 assert typ
== 'fast' # TODO slow?
57 for pname
, stype
, ptype
in [
58 ('cs', 'm_FBCSn', 'out'),
59 ('bwe', 'm_BWEn', 'out'),
60 ('tsiz', 'm_TSIZ', 'out'),
61 ('ad_out', 'm_AD', 'out'),
62 ('ad_in', 'm_din', 'in'),
63 ('ad_out_en', 'm_OE32n', 'out'),
65 ret
.append(self
._mk
_vpincon
(name
, count
, typ
, ptype
, pname
,
66 "sdram_side.{0}".format(stype
)))