5d2d98aa39d5341ca426cfe6437f2b464f6992aa
2 from copy
import deepcopy
6 def __init__(self
, name
):
9 def slowifdeclmux(self
):
12 def slowifinstance(self
):
18 def num_axi_regs32(self
):
24 def get_iname(self
, inum
):
25 return "{0}{1}".format(self
.name
, self
.mksuffix(self
.name
, inum
))
27 def axibase(self
, name
, ifacenum
):
29 return "%(name)s%(ifacenum)dBase" % locals()
31 def axiend(self
, name
, ifacenum
):
33 return "%(name)s%(ifacenum)dEnd" % locals()
35 def axi_reg_def(self
, start
, name
, ifacenum
):
37 offs
= self
.num_axi_regs32() * 4 * 16
40 end
= start
+ offs
- 1
41 bname
= self
.axibase(name
, ifacenum
)
42 bend
= self
.axiend(name
, ifacenum
)
43 comment
= "%d 32-bit regs" % self
.num_axi_regs32()
44 return (" `define %(bname)s 'h%(start)08X\n"
45 " `define %(bend)s 'h%(end)08X // %(comment)s" % locals(),
48 def axi_slave_name(self
, name
, ifacenum
):
50 return "{0}{1}_slave_num".format(name
, ifacenum
)
52 def axi_slave_idx(self
, idx
, name
, ifacenum
):
53 name
= self
.axi_slave_name(name
, ifacenum
)
54 return ("typedef {0} {1};".format(idx
, name
), 1)
56 def axi_addr_map(self
, name
, ifacenum
):
57 bname
= self
.axibase(name
, ifacenum
)
58 bend
= self
.axiend(name
, ifacenum
)
59 name
= self
.axi_slave_name(name
, ifacenum
)
61 if(addr>=`{0} && addr<=`{1})
62 return tuple2(True,fromInteger(valueOf({2})));
63 else""".format(bname
, bend
, name
)
65 def mk_pincon(self
, name
, count
):
66 # TODO: really should be using bsv.interface_decl.Interfaces
67 # pin-naming rules.... logic here is hard-coded to duplicate
68 # it (see Interface.__init__ outen)
70 for p
in self
.peripheral
.pinspecs
:
73 #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
74 n
= name
# "{0}{1}".format(self.name, self.mksuffix(name, count))
75 ret
.append(" //%s %s" % (n
, str(p
)))
76 sname
= self
.peripheral
.pname(pname
).format(count
)
77 ps
= "pinmux.peripheral_side.%s" % sname
78 if typ
== 'out' or typ
== 'inout':
79 ret
.append(" rule con_%s%d_%s_out;" % (name
, count
, pname
))
80 fname
= self
.pinname_out(pname
)
81 if not n
.startswith('gpio'): # XXX EURGH! horrible hack
82 n_
= "{0}{1}".format(n
, count
)
90 ret
.append(" {0}({1}.{2});".format(ps_
, n_
, fname
))
93 fname
= self
.pinname_outen(pname
)
95 if isinstance(fname
, str):
96 fname
= "{0}.{1}".format(n_
, fname
)
97 fname
= self
.pinname_tweak(pname
, 'outen', fname
)
98 ret
.append(" {0}_outen({1});".format(ps
, fname
))
99 ret
.append(" endrule")
100 if typ
== 'in' or typ
== 'inout':
101 fname
= self
.pinname_in(pname
)
108 " rule con_%s%d_%s_in;" %
109 (name
, count
, pname
))
110 n_
= "{0}{1}".format(n
, count
)
111 n_
= '{0}.{1}'.format(n_
, fname
)
112 n_
= self
.ifname_tweak(pname
, 'in', n_
)
113 ret
.append(" {1}({0});".format(ps_
, n_
))
114 ret
.append(" endrule")
115 return '\n'.join(ret
)
117 def mk_cellconn(self
, *args
):
120 def mkslow_peripheral(self
, size
=0):
123 def mksuffix(self
, name
, i
):
126 def __mk_connection(self
, con
, aname
):
127 txt
= " mkConnection (slow_fabric.v_to_slaves\n" + \
128 " [fromInteger(valueOf({1}))],\n" + \
131 print "PBase __mk_connection", self
.name
, aname
134 return txt
.format(con
, aname
)
136 def mk_connection(self
, count
, name
=None):
139 print "PBase mk_conn", self
.name
, count
140 aname
= self
.axi_slave_name(name
, count
)
141 #dname = self.mksuffix(name, count)
142 #dname = "{0}{1}".format(name, dname)
143 con
= self
._mk
_connection
(name
, count
).format(count
, aname
)
144 return self
.__mk
_connection
(con
, aname
)
146 def _mk_connection(self
, name
=None, count
=0):
149 def pinname_out(self
, pname
):
152 def pinname_in(self
, pname
):
155 def pinname_outen(self
, pname
):
158 def ifname_tweak(self
, pname
, typ
, txt
):
161 def pinname_tweak(self
, pname
, typ
, txt
):
167 def mk_plic(self
, inum
, irq_offs
):
169 print "mk_plic", self
.name
, inum
, irq_offs
170 niq
= self
.num_irqs()
172 return ('', irq_offs
)
173 name
= self
.get_iname(inum
)
174 res
.append(" // PLIC rules for {0}".format(name
))
175 for idx
in range(niq
):
176 plic_obj
= self
.plic_object(name
, idx
)
177 print "plic_obj", name
, idx
, plic_obj
178 plic
= mkplic_rule
.format(name
, plic_obj
, irq_offs
)
180 irq_offs
+= 1 # increment to next irq
181 return ('\n'.join(res
), irq_offs
)
183 def mk_ext_ifacedef(self
, iname
, inum
):
188 rule rl_connect_{0}_to_plic_{2};
189 if({1} == 1'b1) begin
190 ff_gateway_queue[{2}].enq(1);
191 plic.ifc_external_irq[{2}].irq_frm_gateway(True);
198 def slowimport(self
):
199 return " import Uart_bs :: *;\n" + \
200 " import RS232_modified::*;"
202 def slowifdecl(self
):
203 return " interface RS232 uart{0}_coe;\n" + \
204 " method Bit#(1) uart{0}_intr;"
206 def num_axi_regs32(self
):
209 def mkslow_peripheral(self
, size
=0):
210 return " Ifc_Uart_bs uart{0} <- \n" + \
211 " mkUart_bs(clocked_by sp_clock,\n" + \
212 " reset_by uart_reset, sp_clock, sp_reset);"
214 def _mk_connection(self
, name
=None, count
=0):
215 return "uart{0}.slave_axi_uart"
217 def pinname_out(self
, pname
):
218 return {'tx': 'coe_rs232.sout'}.get(pname
, '')
220 def pinname_in(self
, pname
):
221 return {'rx': 'coe_rs232.sin'}.get(pname
, '')
226 def slowimport(self
):
227 return " import Uart16550 :: *;"
229 def slowifdecl(self
):
230 return " interface RS232_PHY_Ifc quart{0}_coe;\n" + \
231 " method Bit#(1) quart{0}_intr;"
233 def num_axi_regs32(self
):
236 def mkslow_peripheral(self
, size
=0):
237 return " Uart16550_AXI4_Lite_Ifc quart{0} <- \n" + \
238 " mkUart16550(clocked_by sp_clock,\n" + \
239 " reset_by uart_reset, sp_clock, sp_reset);"
241 def _mk_connection(self
, name
=None, count
=0):
242 return "quart{0}.slave_axi_uart"
244 def pinname_out(self
, pname
):
245 return {'tx' : 'coe_rs232.modem_output_stx',
246 'rts': 'coe_rs232.modem_output_rts',
249 def _pinname_in(self
, pname
):
250 return {'rx': 'coe_rs232.modem_input.srx',
251 'cts': 'coe_rs232.modem_input.cts'
254 def mk_pincon(self
, name
, count
):
255 ret
= [PBase
.mk_pincon(self
, name
, count
)]
256 ret
.append(" rule con_%s%d_io_in;" % (name
, count
))
257 ret
.append(" {0}{1}.coe_rs232.modem_input(".format(name
, count
))
258 for idx
, pname
in enumerate(['rx', 'cts']):
259 sname
= self
.peripheral
.pname(pname
).format(count
)
260 ps
= "pinmux.peripheral_side.%s" % sname
261 ret
.append(" {0},".format(ps
))
262 ret
.append(" 1'b1,1'b0,1'b1")
264 ret
.append(" endrule")
266 return '\n'.join(ret
)
271 def plic_object(self
, pname
, idx
):
272 return "{0}_interrupt.read".format(pname
)
274 def mk_plic(self
, inum
, irq_offs
):
275 name
= self
.get_iname(inum
)
276 ret
= [uart_plic_template
.format(name
, irq_offs
)]
277 (ret2
, irq_offs
) = PBase
.mk_plic(self
, inum
, irq_offs
)
279 return ('\n'.join(ret
), irq_offs
)
281 def mk_ext_ifacedef(self
, iname
, inum
):
282 name
= self
.get_iname(inum
)
283 return " method {0}_intr = {0}.irq;".format(name
)
285 def slowifdeclmux(self
):
286 return " method Bit#(1) {1}{0}_intr;"
288 uart_plic_template
= """\
289 // PLIC {0} synchronisation with irq {1}
290 SyncBitIfc#(Bit#(1)) {0}_interrupt <-
291 mkSyncBitToCC(sp_clock, uart_reset);
292 rule plic_synchronize_{0}_interrupt_{1};
293 {0}_interrupt.send({0}.irq);
299 def slowimport(self
):
300 return " import Uart_bs::*;\n" + \
301 " import RS232_modified::*;"
303 def slowifdecl(self
):
304 return " interface RS232 uart{0}_coe;"
306 def num_axi_regs32(self
):
309 def mkslow_peripheral(self
, size
=0):
310 return " //Ifc_Uart_bs uart{0} <-" + \
311 " // mkUart_bs(clocked_by uart_clock,\n" + \
312 " // reset_by uart_reset,sp_clock, sp_reset);" +\
313 " Ifc_Uart_bs uart{0} <-" + \
314 " mkUart_bs(clocked_by sp_clock,\n" + \
315 " reset_by sp_reset, sp_clock, sp_reset);"
317 def _mk_connection(self
, name
=None, count
=0):
318 return "uart{0}.slave_axi_uart"
320 def pinname_out(self
, pname
):
321 return {'tx': 'coe_rs232.sout'}.get(pname
, '')
323 def pinname_in(self
, pname
):
324 return {'rx': 'coe_rs232.sin'}.get(pname
, '')
329 def slowimport(self
):
330 return " import I2C_top :: *;"
332 def slowifdecl(self
):
333 return " interface I2C_out twi{0}_out;\n" + \
334 " method Bit#(1) twi{0}_isint;"
336 def num_axi_regs32(self
):
339 def mkslow_peripheral(self
, size
=0):
340 return " I2C_IFC twi{0} <- mkI2CController();"
342 def _mk_connection(self
, name
=None, count
=0):
343 return "twi{0}.slave_i2c_axi"
345 def pinname_out(self
, pname
):
346 return {'sda': 'out.sda_out',
347 'scl': 'out.scl_out'}.get(pname
, '')
349 def pinname_in(self
, pname
):
350 return {'sda': 'out.sda_in',
351 'scl': 'out.scl_in'}.get(pname
, '')
353 def pinname_outen(self
, pname
):
354 return {'sda': 'out.sda_out_en',
355 'scl': 'out.scl_out_en'}.get(pname
, '')
357 def pinname_tweak(self
, pname
, typ
, txt
):
359 return "pack({0})".format(txt
)
365 def plic_object(self
, pname
, idx
):
366 return ["{0}.isint()",
371 def mk_ext_ifacedef(self
, iname
, inum
):
372 name
= self
.get_iname(inum
)
373 return " method {0}_isint = {0}.isint;".format(name
)
375 def slowifdeclmux(self
):
376 return " method Bit#(1) {1}{0}_isint;"
381 def slowimport(self
):
382 size
= len(self
.peripheral
.pinspecs
)
383 return " `define NUM_EINTS %d" % size
385 def mkslow_peripheral(self
, size
=0):
386 size
= len(self
.peripheral
.pinspecs
)
387 return " Wire#(Bit#(%d)) wr_interrupt <- mkWire();" % size
389 def axi_slave_name(self
, name
, ifacenum
):
392 def axi_slave_idx(self
, idx
, name
, ifacenum
):
395 def axi_addr_map(self
, name
, ifacenum
):
398 def ifname_tweak(self
, pname
, typ
, txt
):
401 print "ifnameweak", pname
, typ
, txt
402 return "wr_interrupt[{0}] <= ".format(pname
)
404 def mk_pincon(self
, name
, count
):
405 ret
= [PBase
.mk_pincon(self
, name
, count
)]
406 size
= len(self
.peripheral
.pinspecs
)
407 ret
.append(eint_pincon_template
.format(size
))
408 ret
.append(" rule con_%s%d_io_in;" % (name
, count
))
409 ret
.append(" wr_interrupt <= ({")
410 for idx
, p
in enumerate(self
.peripheral
.pinspecs
):
412 sname
= self
.peripheral
.pname(pname
).format(count
)
413 ps
= "pinmux.peripheral_side.%s" % sname
414 comma
= '' if idx
== size
- 1 else ','
415 ret
.append(" {0}{1}".format(ps
, comma
))
417 ret
.append(" endrule")
419 return '\n'.join(ret
)
422 eint_pincon_template
= '''\
423 // EINT is offset at end of other peripheral interrupts
425 for(Integer i=0;i<{0};i=i+ 1)begin
426 rule connect_int_to_plic(wr_interrupt[i]==1);
427 ff_gateway_queue[i+`NUM_SLOW_IRQS].enq(1);
428 plic.ifc_external_irq[i+`NUM_SLOW_IRQS].irq_frm_gateway(True);
437 def axi_slave_name(self
, name
, ifacenum
):
440 def axi_slave_idx(self
, idx
, name
, ifacenum
):
443 def axi_addr_map(self
, name
, ifacenum
):
446 def slowifdeclmux(self
):
447 return " method Action jtag_ms (Bit#(1) in);\n" + \
448 " method Bit#(1) jtag_di;\n" + \
449 " method Action jtag_do (Bit#(1) in);\n" + \
450 " method Action jtag_ck (Bit#(1) in);"
452 def slowifinstance(self
):
453 return jtag_method_template
# bit of a lazy hack this...
455 jtag_method_template
= """\
456 method Action jtag_ms (Bit#(1) in);
457 pinmux.peripheral_side.jtag_ms(in);
459 method Bit#(1) jtag_di=pinmux.peripheral_side.jtag_di;
460 method Action jtag_do (Bit#(1) in);
461 pinmux.peripheral_side.jtag_do(in);
463 method Action jtag_ck (Bit#(1) in);
464 pinmux.peripheral_side.jtag_ck(in);
470 def slowimport(self
):
471 return " import sdcard_dummy :: *;"
473 def slowifdecl(self
):
474 return " interface QSPI_out sd{0}_out;\n" + \
475 " method Bit#(1) sd{0}_isint;"
477 def num_axi_regs32(self
):
480 def mkslow_peripheral(self
):
481 return " Ifc_sdcard_dummy sd{0} <- mksdcard_dummy();"
483 def _mk_connection(self
, name
=None, count
=0):
486 def pinname_in(self
, pname
):
487 return "%s_in" % pname
489 def pinname_out(self
, pname
):
490 if pname
.startswith('d'):
491 return "%s_out" % pname
494 def pinname_outen(self
, pname
):
495 if pname
.startswith('d'):
496 return "%s_outen" % pname
501 def slowimport(self
):
502 return " import qspi :: *;"
504 def slowifdecl(self
):
505 return " interface QSPI_out spi{0}_out;\n" + \
506 " method Bit#(1) spi{0}_isint;"
508 def num_axi_regs32(self
):
511 def mkslow_peripheral(self
):
512 return " Ifc_qspi spi{0} <- mkqspi();"
514 def _mk_connection(self
, name
=None, count
=0):
515 return "spi{0}.slave"
517 def pinname_out(self
, pname
):
518 return {'clk': 'out.clk_o',
520 'mosi': 'out.io_o[0]',
521 'miso': 'out.io_o[1]',
524 def pinname_outen(self
, pname
):
527 'mosi': 'out.io_enable[0]',
528 'miso': 'out.io_enable[1]',
531 def mk_pincon(self
, name
, count
):
532 ret
= [PBase
.mk_pincon(self
, name
, count
)]
533 # special-case for gpio in, store in a temporary vector
534 plen
= len(self
.peripheral
.pinspecs
)
535 ret
.append(" // XXX NSS and CLK are hard-coded master")
536 ret
.append(" // TODO: must add spi slave-mode")
537 ret
.append(" // all ins done in one rule from 4-bitfield")
538 ret
.append(" rule con_%s%d_io_in;" % (name
, count
))
539 ret
.append(" {0}{1}.out.io_i({{".format(name
, count
))
540 for idx
, pname
in enumerate(['mosi', 'miso']):
541 sname
= self
.peripheral
.pname(pname
).format(count
)
542 ps
= "pinmux.peripheral_side.%s_in" % sname
543 ret
.append(" {0},".format(ps
))
544 ret
.append(" 1'b0,1'b0")
546 ret
.append(" endrule")
547 return '\n'.join(ret
)
549 def mk_ext_ifacedef(self
, iname
, inum
):
550 name
= self
.get_iname(inum
)
551 return " method {0}_isint = {0}.interrupts[5];".format(name
)
553 def slowifdeclmux(self
):
554 return " method Bit#(1) {1}{0}_isint;"
559 def slowimport(self
):
560 return " import qspi :: *;"
562 def slowifdecl(self
):
563 return " interface QSPI_out qspi{0}_out;\n" + \
564 " method Bit#(1) qspi{0}_isint;"
566 def num_axi_regs32(self
):
569 def mkslow_peripheral(self
, size
=0):
570 return " Ifc_qspi qspi{0} <- mkqspi();"
572 def _mk_connection(self
, name
=None, count
=0):
573 return "qspi{0}.slave"
575 def pinname_out(self
, pname
):
576 return {'ck': 'out.clk_o',
578 'io0': 'out.io_o[0]',
579 'io1': 'out.io_o[1]',
580 'io2': 'out.io_o[2]',
581 'io3': 'out.io_o[3]',
584 def pinname_outen(self
, pname
):
587 'io0': 'out.io_enable[0]',
588 'io1': 'out.io_enable[1]',
589 'io2': 'out.io_enable[2]',
590 'io3': 'out.io_enable[3]',
593 def mk_pincon(self
, name
, count
):
594 ret
= [PBase
.mk_pincon(self
, name
, count
)]
595 # special-case for gpio in, store in a temporary vector
596 plen
= len(self
.peripheral
.pinspecs
)
597 ret
.append(" // XXX NSS and CLK are hard-coded master")
598 ret
.append(" // TODO: must add qspi slave-mode")
599 ret
.append(" // all ins done in one rule from 4-bitfield")
600 ret
.append(" rule con_%s%d_io_in;" % (name
, count
))
601 ret
.append(" {0}{1}.out.io_i({{".format(name
, count
))
602 for i
, p
in enumerate(self
.peripheral
.pinspecs
):
605 if not pname
.startswith('io'):
609 sname
= self
.peripheral
.pname(pname
).format(count
)
610 ps
= "pinmux.peripheral_side.%s_in" % sname
611 comma
= '' if i
== 5 else ','
612 ret
.append(" {0}{1}".format(ps
, comma
))
614 ret
.append(" endrule")
615 return '\n'.join(ret
)
620 def plic_object(self
, pname
, idx
):
621 return "{0}.interrupts()[{1}]".format(pname
, idx
)
623 def mk_ext_ifacedef(self
, iname
, inum
):
624 name
= self
.get_iname(inum
)
625 return " method {0}_isint = {0}.interrupts[5];".format(name
)
627 def slowifdeclmux(self
):
628 return " method Bit#(1) {1}{0}_isint;"
634 def slowimport(self
):
635 return " import pwm::*;"
637 def slowifdecl(self
):
638 return " interface PWMIO pwm{0}_io;"
640 def num_axi_regs32(self
):
643 def mkslow_peripheral(self
, size
=0):
644 return " Ifc_PWM_bus pwm{0} <- mkPWM_bus(sp_clock);"
646 def _mk_connection(self
, name
=None, count
=0):
647 return "pwm{0}.axi4_slave"
649 def pinname_out(self
, pname
):
650 return {'out': 'pwm_io.pwm_o'}.get(pname
, '')
655 def slowimport(self
):
656 return " import pinmux::*;\n" + \
657 " import mux::*;\n" + \
660 def slowifdeclmux(self
):
661 size
= len(self
.peripheral
.pinspecs
)
662 return " interface GPIO_config#(%d) pad_config{0};" % size
664 def num_axi_regs32(self
):
667 def axi_slave_idx(self
, idx
, name
, ifacenum
):
668 """ generates AXI slave number definition, except
669 GPIO also has a muxer per bank
672 mname
= 'mux' + name
[4:]
673 mname
= mname
.upper()
674 print "AXIslavenum", name
, mname
675 (ret
, x
) = PBase
.axi_slave_idx(self
, idx
, name
, ifacenum
)
676 (ret2
, x
) = PBase
.axi_slave_idx(self
, idx
+ 1, mname
, ifacenum
)
677 return ("%s\n%s" % (ret
, ret2
), 2)
679 def mkslow_peripheral(self
, size
=0):
680 print "gpioslow", self
.peripheral
, dir(self
.peripheral
)
681 size
= len(self
.peripheral
.pinspecs
)
682 return " MUX#(%d) mux{0} <- mkmux();\n" % size
+ \
683 " GPIO#(%d) gpio{0} <- mkgpio();" % size
685 def mk_connection(self
, count
):
686 print "GPIO mk_conn", self
.name
, count
688 dname
= self
.mksuffix(self
.name
, count
)
689 for i
, n
in enumerate(['gpio' + dname
, 'mux' + dname
]):
690 res
.append(PBase
.mk_connection(self
, count
, n
))
691 return '\n'.join(res
)
693 def _mk_connection(self
, name
=None, count
=0):
694 n
= self
.mksuffix(name
, count
)
695 if name
.startswith('gpio'):
696 return "gpio{0}.axi_slave".format(n
)
697 if name
.startswith('mux'):
698 return "mux{0}.axi_slave".format(n
)
700 def mksuffix(self
, name
, i
):
701 if name
.startswith('mux'):
705 def mk_cellconn(self
, cellnum
, name
, count
):
707 bank
= self
.mksuffix(name
, count
)
708 txt
= " pinmux.mux_lines.cell{0}_mux(mux{1}.mux_config.mux[{2}]);"
709 for p
in self
.peripheral
.pinspecs
:
710 ret
.append(txt
.format(cellnum
, bank
, p
['name'][1:]))
712 return ("\n".join(ret
), cellnum
)
714 def pinname_out(self
, pname
):
715 return "func.gpio_out[{0}]".format(pname
[1:])
717 def pinname_outen(self
, pname
):
718 return "func.gpio_out_en[{0}]".format(pname
[1:])
720 def mk_pincon(self
, name
, count
):
721 ret
= [PBase
.mk_pincon(self
, name
, count
)]
722 # special-case for gpio in, store in a temporary vector
723 plen
= len(self
.peripheral
.pinspecs
)
724 ret
.append(" rule con_%s%d_in;" % (name
, count
))
725 ret
.append(" Vector#({0},Bit#(1)) temp;".format(plen
))
726 for p
in self
.peripheral
.pinspecs
:
731 sname
= self
.peripheral
.pname(pname
).format(count
)
732 ps
= "pinmux.peripheral_side.%s_in" % sname
733 ret
.append(" temp[{0}]={1};".format(idx
, ps
))
734 ret
.append(" {0}.func.gpio_in(temp);".format(name
))
735 ret
.append(" endrule")
736 return '\n'.join(ret
)
739 axi_slave_declarations
= """\
740 typedef 0 SlowMaster;
742 typedef TAdd#(LastGen_slave_num,`ifdef CLINT 1 `else 0 `endif )
744 typedef TAdd#(CLINT_slave_num ,`ifdef PLIC 1 `else 0 `endif )
746 typedef TAdd#(Plic_slave_num ,`ifdef AXIEXP 1 `else 0 `endif )
748 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
751 pinmux_cellrule
= """\
752 rule connect_select_lines_pinmux;
758 class CallFn(object):
759 def __init__(self
, peripheral
, name
):
760 self
.peripheral
= peripheral
763 def __call__(self
, *args
):
764 #print "__call__", self.name, self.peripheral.slow, args
765 if not self
.peripheral
.slow
:
767 return getattr(self
.peripheral
.slow
, self
.name
)(*args
[1:])
770 class PeripheralIface(object):
771 def __init__(self
, ifacename
):
773 slow
= slowfactory
.getcls(ifacename
)
774 print "Iface", ifacename
, slow
776 self
.slow
= slow(ifacename
)
777 self
.slow
.peripheral
= self
778 for fname
in ['slowimport',
779 'slowifinstance', 'slowifdecl', 'slowifdeclmux',
780 'mkslow_peripheral', 'mk_plic', 'mk_ext_ifacedef',
781 'mk_connection', 'mk_cellconn', 'mk_pincon']:
782 fn
= CallFn(self
, fname
)
783 setattr(self
, fname
, types
.MethodType(fn
, self
))
785 #print "PeripheralIface"
788 def mksuffix(self
, name
, i
):
789 if self
.slow
is None:
791 return self
.slow
.mksuffix(name
, i
)
793 def axi_reg_def(self
, start
, count
):
796 return self
.slow
.axi_reg_def(start
, self
.ifacename
, count
)
798 def axi_slave_idx(self
, start
, count
):
801 return self
.slow
.axi_slave_idx(start
, self
.ifacename
, count
)
803 def axi_addr_map(self
, count
):
806 return self
.slow
.axi_addr_map(self
.ifacename
, count
)
809 class PeripheralInterfaces(object):
813 def slowimport(self
, *args
):
815 for (name
, count
) in self
.ifacecount
:
816 #print "slowimport", name, self.data[name].slowimport
817 ret
.append(self
.data
[name
].slowimport())
818 return '\n'.join(list(filter(None, ret
)))
820 def slowifinstance(self
, *args
):
822 for (name
, count
) in self
.ifacecount
:
823 #print "slowimport", name, self.data[name].slowimport
824 ret
.append(self
.data
[name
].slowifinstance())
825 return '\n'.join(list(filter(None, ret
)))
827 def slowifdeclmux(self
, *args
):
829 for (name
, count
) in self
.ifacecount
:
830 for i
in range(count
):
831 ret
.append(self
.data
[name
].slowifdeclmux().format(i
, name
))
832 return '\n'.join(list(filter(None, ret
)))
834 def slowifdecl(self
, *args
):
836 for (name
, count
) in self
.ifacecount
:
837 for i
in range(count
):
838 ret
.append(self
.data
[name
].slowifdecl().format(i
, name
))
839 return '\n'.join(list(filter(None, ret
)))
841 def axi_reg_def(self
, *args
):
843 start
= 0x00011100 # start of AXI peripherals address
844 for (name
, count
) in self
.ifacecount
:
845 for i
in range(count
):
846 x
= self
.data
[name
].axi_reg_def(start
, i
)
847 #print ("ifc", name, x)
851 return '\n'.join(list(filter(None, ret
)))
853 def axi_slave_idx(self
, *args
):
856 for (name
, count
) in self
.ifacecount
:
857 for i
in range(count
):
858 (rdef
, offs
) = self
.data
[name
].axi_slave_idx(start
, i
)
859 #print ("ifc", name, rdef, offs)
862 ret
.append("typedef %d LastGen_slave_num;" % (start
- 1))
863 decls
= '\n'.join(list(filter(None, ret
)))
864 return axi_slave_declarations
.format(decls
)
866 def axi_addr_map(self
, *args
):
868 for (name
, count
) in self
.ifacecount
:
869 for i
in range(count
):
870 ret
.append(self
.data
[name
].axi_addr_map(i
))
871 return '\n'.join(list(filter(None, ret
)))
873 def mkslow_peripheral(self
, *args
):
875 for (name
, count
) in self
.ifacecount
:
876 for i
in range(count
):
877 print "mkslow", name
, count
878 x
= self
.data
[name
].mkslow_peripheral()
880 suffix
= self
.data
[name
].mksuffix(name
, i
)
881 ret
.append(x
.format(suffix
))
882 return '\n'.join(list(filter(None, ret
)))
884 def mk_connection(self
, *args
):
886 for (name
, count
) in self
.ifacecount
:
887 for i
in range(count
):
888 print "mk_conn", name
, i
889 txt
= self
.data
[name
].mk_connection(i
)
892 print self
.data
[name
].mk_connection
894 return '\n'.join(list(filter(None, ret
)))
896 def mk_cellconn(self
):
899 for (name
, count
) in self
.ifacecount
:
900 for i
in range(count
):
901 res
= self
.data
[name
].mk_cellconn(cellcount
, name
, i
)
904 (txt
, cellcount
) = res
906 ret
= '\n'.join(list(filter(None, ret
)))
907 return pinmux_cellrule
.format(ret
)
911 for (name
, count
) in self
.ifacecount
:
912 for i
in range(count
):
913 txt
= self
.data
[name
].mk_pincon(name
, i
)
915 return '\n'.join(list(filter(None, ret
)))
917 def mk_ext_ifacedef(self
):
919 for (name
, count
) in self
.ifacecount
:
920 for i
in range(count
):
921 txt
= self
.data
[name
].mk_ext_ifacedef(name
, i
)
923 return '\n'.join(list(filter(None, ret
)))
928 irq_offs
= 8 # XXX: DMA scovers 0-7?
929 for (name
, count
) in self
.ifacecount
:
930 for i
in range(count
):
931 res
= self
.data
[name
].mk_plic(i
, irq_offs
)
934 (txt
, irq_offs
) = res
936 self
.num_slow_irqs
= irq_offs
937 return '\n'.join(list(filter(None, ret
)))
939 def mk_sloirqsdef(self
):
940 return " `define NUM_SLOW_IRQS {0}".format(self
.num_slow_irqs
)
943 class PFactory(object):
944 def getcls(self
, name
):
945 for k
, v
in {'uart': uart
,
957 if name
.startswith(k
):
962 slowfactory
= PFactory()
964 if __name__
== '__main__':
968 i
= PeripheralIface('uart')
970 i
= PeripheralIface('gpioa')