6c49f5fec175af2318cb012643f9aa32174f4c56
2 from copy
import deepcopy
6 def __init__(self
, name
):
9 def slowifdeclmux(self
):
15 def axibase(self
, name
, ifacenum
):
17 return "%(name)s%(ifacenum)dBase" % locals()
19 def axiend(self
, name
, ifacenum
):
21 return "%(name)s%(ifacenum)dEnd" % locals()
23 def axi_reg_def(self
, start
, name
, ifacenum
):
25 offs
= self
.num_axi_regs32() * 4 * 16
26 end
= start
+ offs
- 1
27 bname
= self
.axibase(name
, ifacenum
)
28 bend
= self
.axiend(name
, ifacenum
)
29 comment
= "%d 32-bit regs" % self
.num_axi_regs32()
30 return (" `define %(bname)s 'h%(start)08X\n"
31 " `define %(bend)s 'h%(end)08X // %(comment)s" % locals(),
34 def axi_slave_name(self
, name
, ifacenum
):
36 return "{0}{1}_slave_num".format(name
, ifacenum
)
38 def axi_slave_idx(self
, idx
, name
, ifacenum
):
39 name
= self
.axi_slave_name(name
, ifacenum
)
40 return ("typedef {0} {1};".format(idx
, name
), 1)
42 def axi_addr_map(self
, name
, ifacenum
):
43 bname
= self
.axibase(name
, ifacenum
)
44 bend
= self
.axiend(name
, ifacenum
)
45 name
= self
.axi_slave_name(name
, ifacenum
)
47 if(addr>=`{0} && addr<=`{1})
48 return tuple2(True,fromInteger(valueOf({2})));
49 else""".format(bname
, bend
, name
)
51 def mk_pincon(self
, name
, count
):
52 # TODO: really should be using bsv.interface_decl.Interfaces
53 # pin-naming rules.... logic here is hard-coded to duplicate
54 # it (see Interface.__init__ outen)
56 for p
in self
.peripheral
.pinspecs
:
59 #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
60 n
= name
# "{0}{1}".format(self.name, self.mksuffix(name, count))
61 ret
.append(" //%s %s" % (n
, str(p
)))
62 sname
= self
.peripheral
.pname(pname
).format(count
)
63 ps
= "pinmux.peripheral_side.%s" % sname
64 if typ
== 'out' or typ
== 'inout':
65 ret
.append(" rule con_%s%d_%s_out;" % (name
, count
, pname
))
66 fname
= self
.pinname_out(pname
)
67 if not n
.startswith('gpio'): # XXX EURGH! horrible hack
68 n_
= "{0}{1}".format(n
, count
)
76 ret
.append(" {0}({1}.{2});".format(ps_
, n_
, fname
))
79 fname
= self
.pinname_outen(pname
)
81 if isinstance(fname
, str):
82 fname
= "{0}.{1}".format(n_
, fname
)
83 fname
= self
.pinname_tweak(pname
, 'outen', fname
)
84 ret
.append(" {0}_outen({1});".format(ps
, fname
))
85 ret
.append(" endrule")
86 if typ
== 'in' or typ
== 'inout':
87 fname
= self
.pinname_in(pname
)
94 " rule con_%s%d_%s_in;" %
96 n_
= "{0}{1}".format(n
, count
)
97 ret
.append(" {1}.{2}({0});".format(ps_
, n_
, fname
))
98 ret
.append(" endrule")
101 def mk_cellconn(self
, *args
):
104 def mkslow_peripheral(self
, size
=0):
107 def mksuffix(self
, name
, i
):
110 def __mk_connection(self
, con
, aname
):
111 txt
= " mkConnection (slow_fabric.v_to_slaves\n" + \
112 " [fromInteger(valueOf({1}))],\n" + \
115 print "PBase __mk_connection", self
.name
, aname
118 return txt
.format(con
, aname
)
120 def mk_connection(self
, count
, name
=None):
123 print "PBase mk_conn", self
.name
, count
124 aname
= self
.axi_slave_name(name
, count
)
125 #dname = self.mksuffix(name, count)
126 #dname = "{0}{1}".format(name, dname)
127 con
= self
._mk
_connection
(name
, count
).format(count
, aname
)
128 return self
.__mk
_connection
(con
, aname
)
130 def _mk_connection(self
, name
=None, count
=0):
133 def pinname_out(self
, pname
):
136 def pinname_in(self
, pname
):
139 def pinname_outen(self
, pname
):
142 def pinname_tweak(self
, pname
, typ
, txt
):
148 def slowimport(self
):
149 return " import Uart_bs :: *;\n" + \
150 " import RS232_modified::*;"
152 def slowifdecl(self
):
153 return " interface RS232 uart{0}_coe;\n" + \
154 " method Bit#(1) uart{0}_intr;"
156 def num_axi_regs32(self
):
159 def mkslow_peripheral(self
, size
=0):
160 return " Ifc_Uart_bs uart{0} <- \n" + \
161 " mkUart_bs(clocked_by sp_clock,\n" + \
162 " reset_by uart_reset, sp_clock, sp_reset);"
164 def _mk_connection(self
, name
=None, count
=0):
165 return "uart{0}.slave_axi_uart"
167 def pinname_out(self
, pname
):
168 return {'tx': 'coe_rs232.sout'}.get(pname
, '')
170 def pinname_in(self
, pname
):
171 return {'rx': 'coe_rs232.sin'}.get(pname
, '')
176 def slowimport(self
):
177 return " import Uart16550 :: *;"
179 def slowifdecl(self
):
180 return " interface RS232_PHY_Ifc uart{0}_coe;\n" + \
181 " method Bit#(1) uart{0}_intr;"
183 def num_axi_regs32(self
):
186 def mkslow_peripheral(self
, size
=0):
187 return " Uart16550_AXI4_Lite_Ifc uart{0} <- \n" + \
188 " mkUart16550(clocked_by sp_clock,\n" + \
189 " reset_by uart_reset, sp_clock, sp_reset);"
191 def _mk_connection(self
, name
=None, count
=0):
192 return "uart{0}.slave_axi_uart"
194 def pinname_out(self
, pname
):
195 return {'tx': 'coe_rs232.sout'}.get(pname
, '')
197 def pinname_in(self
, pname
):
198 return {'rx': 'coe_rs232.sin'}.get(pname
, '')
203 def slowimport(self
):
204 return " import Uart_bs::*;\n" + \
205 " import RS232_modified::*;"
207 def slowifdecl(self
):
208 return " interface RS232 uart{0}_coe;"
210 def num_axi_regs32(self
):
213 def mkslow_peripheral(self
, size
=0):
214 return " //Ifc_Uart_bs uart{0} <-" + \
215 " // mkUart_bs(clocked_by uart_clock,\n" + \
216 " // reset_by uart_reset,sp_clock, sp_reset);" +\
217 " Ifc_Uart_bs uart{0} <-" + \
218 " mkUart_bs(clocked_by sp_clock,\n" + \
219 " reset_by sp_reset, sp_clock, sp_reset);"
221 def _mk_connection(self
, name
=None, count
=0):
222 return "uart{0}.slave_axi_uart"
224 def pinname_out(self
, pname
):
225 return {'tx': 'coe_rs232.sout'}.get(pname
, '')
227 def pinname_in(self
, pname
):
228 return {'rx': 'coe_rs232.sin'}.get(pname
, '')
233 def slowimport(self
):
234 return " import I2C_top :: *;"
236 def slowifdecl(self
):
237 return " interface I2C_out twi{0}_out;\n" + \
238 " method Bit#(1) twi{0}_isint;"
240 def num_axi_regs32(self
):
243 def mkslow_peripheral(self
, size
=0):
244 return " I2C_IFC twi{0} <- mkI2CController();"
246 def _mk_connection(self
, name
=None, count
=0):
247 return "twi{0}.slave_i2c_axi"
249 def pinname_out(self
, pname
):
250 return {'sda': 'out.sda_out',
251 'scl': 'out.scl_out'}.get(pname
, '')
253 def pinname_in(self
, pname
):
254 return {'sda': 'out.sda_in',
255 'scl': 'out.scl_in'}.get(pname
, '')
257 def pinname_outen(self
, pname
):
258 return {'sda': 'out.sda_out_en',
259 'scl': 'out.scl_out_en'}.get(pname
, '')
261 def pinname_tweak(self
, pname
, typ
, txt
):
263 return "pack({0})".format(txt
)
269 def slowimport(self
):
270 return " import qspi :: *;"
272 def slowifdecl(self
):
273 return " interface QSPI_out spi{0}_out;\n" + \
274 " method Bit#(1) spi{0}_isint;"
276 def num_axi_regs32(self
):
279 def mkslow_peripheral(self
):
280 return " Ifc_qspi spi{0} <- mkqspi();"
282 def _mk_connection(self
, name
=None, count
=0):
283 return "spi{0}.slave"
285 def pinname_out(self
, pname
):
286 return {'clk': 'out.clk_o',
288 'mosi': 'out.io_o[0]',
289 'miso': 'out.io_o[1]',
292 def pinname_outen(self
, pname
):
295 'mosi': 'out.io_enable[0]',
296 'miso': 'out.io_enable[1]',
299 def mk_pincon(self
, name
, count
):
300 ret
= [PBase
.mk_pincon(self
, name
, count
)]
301 # special-case for gpio in, store in a temporary vector
302 plen
= len(self
.peripheral
.pinspecs
)
303 ret
.append(" // XXX NSS and CLK are hard-coded master")
304 ret
.append(" // TODO: must add spi slave-mode")
305 ret
.append(" // all ins done in one rule from 4-bitfield")
306 ret
.append(" rule con_%s%d_io_in;" % (name
, count
))
307 ret
.append(" {0}{1}.out.io_i({{".format(name
, count
))
308 for idx
, pname
in enumerate(['mosi', 'miso']):
309 sname
= self
.peripheral
.pname(pname
).format(count
)
310 ps
= "pinmux.peripheral_side.%s_in" % sname
311 ret
.append(" {0},".format(ps
))
312 ret
.append(" 1'b0,1'b0")
314 ret
.append(" endrule")
315 return '\n'.join(ret
)
320 def slowimport(self
):
321 return " import qspi :: *;"
323 def slowifdecl(self
):
324 return " interface QSPI_out qspi{0}_out;\n" + \
325 " method Bit#(1) qspi{0}_isint;"
327 def num_axi_regs32(self
):
330 def mkslow_peripheral(self
, size
=0):
331 return " Ifc_qspi qspi{0} <- mkqspi();"
333 def _mk_connection(self
, name
=None, count
=0):
334 return "qspi{0}.slave"
336 def pinname_out(self
, pname
):
337 return {'ck': 'out.clk_o',
339 'io0': 'out.io_o[0]',
340 'io1': 'out.io_o[1]',
341 'io2': 'out.io_o[2]',
342 'io3': 'out.io_o[3]',
345 def pinname_outen(self
, pname
):
348 'io0': 'out.io_enable[0]',
349 'io1': 'out.io_enable[1]',
350 'io2': 'out.io_enable[2]',
351 'io3': 'out.io_enable[3]',
354 def mk_pincon(self
, name
, count
):
355 ret
= [PBase
.mk_pincon(self
, name
, count
)]
356 # special-case for gpio in, store in a temporary vector
357 plen
= len(self
.peripheral
.pinspecs
)
358 ret
.append(" // XXX NSS and CLK are hard-coded master")
359 ret
.append(" // TODO: must add qspi slave-mode")
360 ret
.append(" // all ins done in one rule from 4-bitfield")
361 ret
.append(" rule con_%s%d_io_in;" % (name
, count
))
362 ret
.append(" {0}{1}.out.io_i({{".format(name
, count
))
363 for i
, p
in enumerate(self
.peripheral
.pinspecs
):
366 if not pname
.startswith('io'):
370 sname
= self
.peripheral
.pname(pname
).format(count
)
371 ps
= "pinmux.peripheral_side.%s_in" % sname
372 comma
= '' if i
== 5 else ','
373 ret
.append(" {0}{1}".format(ps
, comma
))
375 ret
.append(" endrule")
376 return '\n'.join(ret
)
381 def slowimport(self
):
382 return " import pwm::*;"
384 def slowifdecl(self
):
385 return " interface PWMIO pwm{0}_io;"
387 def num_axi_regs32(self
):
390 def mkslow_peripheral(self
, size
=0):
391 return " Ifc_PWM_bus pwm{0} <- mkPWM_bus(sp_clock);"
393 def _mk_connection(self
, name
=None, count
=0):
394 return "pwm{0}.axi4_slave"
396 def pinname_out(self
, pname
):
397 return {'out': 'pwm_io.pwm_o'}.get(pname
, '')
402 def slowimport(self
):
403 return " import pinmux::*;\n" + \
404 " import mux::*;\n" + \
407 def slowifdeclmux(self
):
408 size
= len(self
.peripheral
.pinspecs
)
409 return " interface GPIO_config#(%d) pad_config{0};" % size
411 def num_axi_regs32(self
):
414 def axi_slave_idx(self
, idx
, name
, ifacenum
):
415 """ generates AXI slave number definition, except
416 GPIO also has a muxer per bank
419 mname
= 'mux' + name
[4:]
420 mname
= mname
.upper()
421 print "AXIslavenum", name
, mname
422 (ret
, x
) = PBase
.axi_slave_idx(self
, idx
, name
, ifacenum
)
423 (ret2
, x
) = PBase
.axi_slave_idx(self
, idx
+1, mname
, ifacenum
)
424 return ("%s\n%s" % (ret
, ret2
), 2)
426 def mkslow_peripheral(self
, size
=0):
427 print "gpioslow", self
.peripheral
, dir(self
.peripheral
)
428 size
= len(self
.peripheral
.pinspecs
)
429 return " MUX#(%d) mux{0} <- mkmux();\n" % size
+ \
430 " GPIO#(%d) gpio{0} <- mkgpio();" % size
432 def mk_connection(self
, count
):
433 print "GPIO mk_conn", self
.name
, count
435 dname
= self
.mksuffix(self
.name
, count
)
436 for i
, n
in enumerate(['gpio' + dname
, 'mux' + dname
]):
437 res
.append(PBase
.mk_connection(self
, count
, n
))
438 return '\n'.join(res
)
440 def _mk_connection(self
, name
=None, count
=0):
441 n
= self
.mksuffix(name
, count
)
442 if name
.startswith('gpio'):
443 return "gpio{0}.axi_slave".format(n
)
444 if name
.startswith('mux'):
445 return "mux{0}.axi_slave".format(n
)
447 def mksuffix(self
, name
, i
):
448 if name
.startswith('mux'):
452 def mk_cellconn(self
, cellnum
, name
, count
):
454 bank
= self
.mksuffix(name
, count
)
455 txt
= " pinmux.mux_lines.cell{0}_mux(mux{1}.mux_config.mux[{2}]);"
456 for p
in self
.peripheral
.pinspecs
:
457 ret
.append(txt
.format(cellnum
, bank
, p
['name'][1:]))
459 return ("\n".join(ret
), cellnum
)
461 def pinname_out(self
, pname
):
462 return "func.gpio_out[{0}]".format(pname
[1:])
464 def pinname_outen(self
, pname
):
465 return "func.gpio_out_en[{0}]".format(pname
[1:])
467 def mk_pincon(self
, name
, count
):
468 ret
= [PBase
.mk_pincon(self
, name
, count
)]
469 # special-case for gpio in, store in a temporary vector
470 plen
= len(self
.peripheral
.pinspecs
)
471 ret
.append(" rule con_%s%d_in;" % (name
, count
))
472 ret
.append(" Vector#({0},Bit#(1)) temp;".format(plen
))
473 for p
in self
.peripheral
.pinspecs
:
478 sname
= self
.peripheral
.pname(pname
).format(count
)
479 ps
= "pinmux.peripheral_side.%s_in" % sname
480 ret
.append(" temp[{0}]={1};".format(idx
, ps
))
481 ret
.append(" {0}.func.gpio_in(temp);".format(name
))
482 ret
.append(" endrule")
483 return '\n'.join(ret
)
486 axi_slave_declarations
= """\
487 typedef 0 SlowMaster;
489 typedef TAdd#(LastGen_slave_num,`ifdef CLINT 1 `else 0 `endif )
491 typedef TAdd#(CLINT_slave_num ,`ifdef PLIC 1 `else 0 `endif )
493 typedef TAdd#(Plic_slave_num ,`ifdef AXIEXP 1 `else 0 `endif )
495 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
498 pinmux_cellrule
= """\
499 rule connect_select_lines_pinmux;
505 class CallFn(object):
506 def __init__(self
, peripheral
, name
):
507 self
.peripheral
= peripheral
510 def __call__(self
, *args
):
511 #print "__call__", self.name, self.peripheral.slow, args
512 if not self
.peripheral
.slow
:
514 return getattr(self
.peripheral
.slow
, self
.name
)(*args
[1:])
517 class PeripheralIface(object):
518 def __init__(self
, ifacename
):
520 slow
= slowfactory
.getcls(ifacename
)
521 print "Iface", ifacename
, slow
523 self
.slow
= slow(ifacename
)
524 self
.slow
.peripheral
= self
525 for fname
in ['slowimport', 'slowifdecl', 'slowifdeclmux',
527 'mk_connection', 'mk_cellconn', 'mk_pincon']:
528 fn
= CallFn(self
, fname
)
529 setattr(self
, fname
, types
.MethodType(fn
, self
))
531 #print "PeripheralIface"
534 def mksuffix(self
, name
, i
):
535 if self
.slow
is None:
537 return self
.slow
.mksuffix(name
, i
)
539 def axi_reg_def(self
, start
, count
):
542 return self
.slow
.axi_reg_def(start
, self
.ifacename
, count
)
544 def axi_slave_idx(self
, start
, count
):
547 return self
.slow
.axi_slave_idx(start
, self
.ifacename
, count
)
549 def axi_addr_map(self
, count
):
552 return self
.slow
.axi_addr_map(self
.ifacename
, count
)
555 class PeripheralInterfaces(object):
559 def slowimport(self
, *args
):
561 for (name
, count
) in self
.ifacecount
:
562 #print "slowimport", name, self.data[name].slowimport
563 ret
.append(self
.data
[name
].slowimport())
564 return '\n'.join(list(filter(None, ret
)))
566 def slowifdeclmux(self
, *args
):
568 for (name
, count
) in self
.ifacecount
:
569 for i
in range(count
):
570 ret
.append(self
.data
[name
].slowifdeclmux().format(i
, name
))
571 return '\n'.join(list(filter(None, ret
)))
573 def slowifdecl(self
, *args
):
575 for (name
, count
) in self
.ifacecount
:
576 for i
in range(count
):
577 ret
.append(self
.data
[name
].slowifdecl().format(i
, name
))
578 return '\n'.join(list(filter(None, ret
)))
580 def axi_reg_def(self
, *args
):
582 start
= 0x00011100 # start of AXI peripherals address
583 for (name
, count
) in self
.ifacecount
:
584 for i
in range(count
):
585 x
= self
.data
[name
].axi_reg_def(start
, i
)
586 #print ("ifc", name, x)
590 return '\n'.join(list(filter(None, ret
)))
592 def axi_slave_idx(self
, *args
):
595 for (name
, count
) in self
.ifacecount
:
596 for i
in range(count
):
597 (rdef
, offs
) = self
.data
[name
].axi_slave_idx(start
, i
)
598 #print ("ifc", name, rdef, offs)
601 ret
.append("typedef %d LastGen_slave_num;" % (start
- 1))
602 decls
= '\n'.join(list(filter(None, ret
)))
603 return axi_slave_declarations
.format(decls
)
605 def axi_addr_map(self
, *args
):
607 for (name
, count
) in self
.ifacecount
:
608 for i
in range(count
):
609 ret
.append(self
.data
[name
].axi_addr_map(i
))
610 return '\n'.join(list(filter(None, ret
)))
612 def mkslow_peripheral(self
, *args
):
614 for (name
, count
) in self
.ifacecount
:
615 for i
in range(count
):
616 print "mkslow", name
, count
617 x
= self
.data
[name
].mkslow_peripheral()
619 suffix
= self
.data
[name
].mksuffix(name
, i
)
620 ret
.append(x
.format(suffix
))
621 return '\n'.join(list(filter(None, ret
)))
623 def mk_connection(self
, *args
):
625 for (name
, count
) in self
.ifacecount
:
626 for i
in range(count
):
627 print "mk_conn", name
, i
628 txt
= self
.data
[name
].mk_connection(i
)
631 print self
.data
[name
].mk_connection
633 return '\n'.join(list(filter(None, ret
)))
635 def mk_cellconn(self
):
638 for (name
, count
) in self
.ifacecount
:
639 for i
in range(count
):
640 res
= self
.data
[name
].mk_cellconn(cellcount
, name
, i
)
643 (txt
, cellcount
) = res
645 ret
= '\n'.join(list(filter(None, ret
)))
646 return pinmux_cellrule
.format(ret
)
650 for (name
, count
) in self
.ifacecount
:
651 for i
in range(count
):
652 txt
= self
.data
[name
].mk_pincon(name
, i
)
654 return '\n'.join(list(filter(None, ret
)))
657 class PFactory(object):
658 def getcls(self
, name
):
659 for k
, v
in {'uart': uart
,
667 if name
.startswith(k
):
672 slowfactory
= PFactory()
674 if __name__
== '__main__':
678 i
= PeripheralIface('uart')
680 i
= PeripheralIface('gpioa')