2 Copyright (c) 2013, IIT Madras
5 Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
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9 * Neither the name of IIT Madras nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
11 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
12 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
14 Author Names : Neel Gala, Arjun Menon
15 Email ID : neelgala@gmail.com
19 This files contains all the types and structures that are used in any of the modules.
21 package defined_types;
23 `include "instance_defines.bsv"
25 typedef enum {Load, Store, Atomic, Fence} Access_type deriving (Bits,Eq,FShow);
26 typedef enum {User=2'd0,Supervisor=2'd1,Machine=2'd3} Privilege_mode deriving (Bits,Eq,FShow);
27 typedef enum {Idle,Stall,Handling_Request,Handling_Memory_Read, Handling_Memory_Write, Handle_Fence} Cache_State deriving (Bits,Eq,FShow);
28 typedef enum {Check_vd,Update_vd} Fence_state deriving (Bits,Eq);
29 typedef enum {AccessFlush,Fence,None} Flush_type deriving (Bits,Eq,FShow);
34 } RFType#(numeric type width) deriving(Bits,Eq,FShow);
39 Bit#(TLog#(`PRFDEPTH)) Specific;
40 }PRFFlush deriving(Bits, Eq, FShow);
45 Tuple2#(Register_type, Bit#(5)) Specific;
46 }RFFlush deriving(Bits, Eq, FShow);
50 Bit#(addr_width) address;
51 }From_Cpu#(numeric type addr_width) deriving(Bits,Eq);
54 Bit#(TMul#(word_size,8)) data_word;
56 Bit#(1) misaligned_error;
57 Bit#(addr_width) address;
58 }To_Cpu#(numeric type addr_width,numeric type word_size) deriving(Bits,Eq);
61 Bit#(addr_width) address;
64 Bit#(3) transfer_size;
65 }To_Memory#(numeric type addr_width) deriving(Bits,Eq);
68 Bit#(TMul#(word_size,8)) data_line;
71 }From_Memory#(numeric type word_size) deriving(Bits,Eq);
74 //Bit#(addr_width) address;
75 Access_type load_store;
76 Bit#(TMul#(word_size,8)) data;
77 Bit#(TLog#(TDiv#(addr_width, 8))) transfer_size; // 0 -8 bits, 1- 16 bits, 2 -32 bits 3 - 64-bits;
78 `ifdef atomic Bit#(5) atomic_op;`endif
80 }From_Cpu_D#(numeric type addr_width, numeric type word_size) deriving(Bits,Eq,FShow);
84 Bit#(TMul#(8,TMul#(word_size,block_size))) line;
85 Bit#(addr_width) address;
86 Bit#(TLog#(ways)) replace_block;
87 } Current_Store#(numeric type ways, numeric type addr_width, numeric type block_size, numeric type word_size) deriving(Bits,Eq);
90 Bit#(TMul#(word_size,8)) data_word;
92 Bit#(1) misaligned_error;
93 Bit#(addr_width) address;
94 Access_type load_store;
95 }To_Cpu_D#(numeric type addr_width,numeric type word_size) deriving(Bits,Eq);
101 Bit#(TLog#(TDiv#(`VADDR, 8))) transfer_size; // 0 -8 bits, 1- 16 bits, 2 -32 bits 3 - 64-bits;
102 Bit#(TMul#(`DCACHE_BLOCK_SIZE,TMul#(`DCACHE_WORD_SIZE,8))) data_line;
103 } To_Memory_Write deriving(Bits,Eq);
106 Bit#(TMul#(word_size,8)) data_line;
108 Bit#(1) misaligned_error;
109 Bit#(addr_width) address;
110 }From_Memory_D#(numeric type addr_width,numeric type word_size, numeric type block_size) deriving(Bits,Eq);
115 }Actual_jump deriving (Eq,Bits,FShow); // actual branch condition used in the branch execution unit.
118 // enum defining the prediction of the branch predictor for the current PC.
120 Predicted_taken,Predicted_notaken
121 }Prediction_type deriving (Eq,Bits,FShow); // output from the branch prediction unit.
123 // A typedef defining , if the prediction by the branch predictor was correct or wrong.
124 typedef union tagged{
125 Bit#(`VADDR) Mispredicted;
126 Bit#(`VADDR) Correct_prediction;
127 }Prediction_result deriving (Eq,Bits,FShow); // result of prediuction from the branch execution unit.
130 Bit#(addr_width) prog_counter_;
131 Prediction_type prediction_;
133 } Predictor_output#(numeric type addr_width) deriving(Bits, Eq); // the program counter from the branch prediction unit.
136 Bit#(`Reg_width) data_forward;
137 Bit#(TLog#(`PRFDEPTH)) pid;
138 }Operand_forwading_type deriving (Bits,Eq); // the data structure for operand forwarding from any stage
140 typedef union tagged{
141 Bit#(`Reg_width) Data;
142 Bit#(TLog#(`PRFDEPTH)) Pid;
143 } FromRf deriving (Bits,Eq,FShow);
146 Bit#(`Reg_width) rs1;
147 Bit#(`Reg_width) rs2;
148 `ifdef spfpu Bit#(`Reg_width) rs3;`endif
149 } Output_for_operand_fetch deriving (Bits,Eq); // output from the register file to the decode stage
152 ALU,MUL,DIV,MEMORY,BRANCH,JAL,JALR `ifdef spfpu ,DFLOATING,FLOATING `endif ,FENCE,FENCEI,SYSTEM_INSTR,NOP
153 }Instruction_type deriving(Bits, Eq,FShow); // the type of the decoded instruction.
155 // to distuingish between integer and floating point RF
156 typedef enum {IntegerRF `ifdef spfpu ,FloatingRF `endif } Register_type deriving(Bits,Eq,FShow);
157 typedef enum {IntegerRF `ifdef spfpu ,FloatingRF `endif , Immediate, PC} Operand_type deriving(Bits,Eq,FShow);
160 typedef union tagged{
162 Bit#(`Reg_width) Address;
163 Bit#(`Reg_width) Data;} TriggerType deriving(Bits,Eq,FShow);
167 Bit#(4) matchscheme;} TriggerData deriving(Bits,Eq,FShow);
169 // the data stucture for the pipeline FIFO between fetch and decode.
171 Bit#(`VADDR) program_counter;
172 Bit#(32) instruction;
176 Bit#(`PERFMONITORS) perfmonitors;
178 }IF_ID_type deriving (Bits,Eq);
181 Bit#(`Reg_width) rs1;
182 Bit#(`Reg_width) rs2;
184 Bit#(12) csr_address;
186 }CSRInputs deriving(Bits,Eq,FShow);
189 Instruction_type inst_type;
191 Bit#(`Reg_width) rs1;
192 Bit#(`Reg_width) rs2;
193 Bit#(`Reg_width) rs3_imm;
197 Operand_type rs1_type;
198 Operand_type rs2_type;
199 Operand_type rs3_type;
200 Bit#(`VADDR) program_counter;
202 Access_type mem_access;
203 Bit#(4) fn; // TODO Check is this can suffices for memaccess also
208 `ifdef spfpu Bool fcsr_rm; `endif
209 `ifdef simulate Bit#(32) instruction ;`endif
212 Bit#(`PERFMONITORS) perfmonitors;
214 }ID_IE_type deriving (Bits,Eq);
217 Bit#(`Reg_width) address;
218 Bit#(`Reg_width) memory_data; // data to be written in the memory
219 Bit#(TLog#(TDiv#(`VADDR, 8))) transfer_size; // 0 -8 bits, 1- 16 bits, 2 -32 bits 3 - 64-bits;
220 Bit#(1) signextend; // whether the loaded value has to be signextended
221 Access_type mem_type; // STORE or AMO or LOAD or FENCE
222 `ifdef atomic Bit#(5) atomic_op;`endif
224 }Memout deriving(Bits,Eq,FShow);
226 typedef union tagged{
227 Arithout RESULT; // 64+5
228 Memout MEMORY; // 64+64+3+1+3+5 = 140
229 CSRInputs SYSTEM; // 64+64+5+12+3 = 148
231 } Execution_output deriving(Bits,Eq,FShow);
234 // Bit#(`Reg_width) result_addr_rs1;
235 // Bit#(`Reg_width) data_rs2;
237 //} Execution_output deriving(Bits,Eq,FShow);
240 Execution_output execresult;
241 Bit#(`VADDR) program_counter;
244 Operand_type rd_type;
245 Bit#(TLog#(`PRFDEPTH)) index;
247 `ifdef simulate Bit#(32) instruction ;`endif
249 Bit#(`PERFMONITORS) perfmonitors;
251 }IE_IMEM_type deriving (Bits,Eq);
254 Bit#(`Reg_width) aluresult;
256 } Arithout deriving(Bits,Eq,FShow); // output struct from the alu.
259 Bit#(`Reg_width) address;
260 Bit#(3) transfer_size;
261 Access_type load_store;
262 }MemoryResponse deriving(Bits,Eq,FShow);
264 typedef union tagged{
267 } WriteBackType deriving(Bits,Eq);
270 WriteBackType commit_data;
272 Operand_type rd_type;
273 Bit#(TLog#(`PRFDEPTH)) index;
275 Bit#(`VADDR) program_counter;
277 `ifdef simulate Bit#(32) instruction ;`endif
279 Bit#(`PERFMONITORS) perfmonitors;
281 }IMEM_IWB_type deriving(Bits,Eq);
285 Bit#(TLog#(TDiv#(paddr,8))) transfer_size;
288 Bit#(TMul#(8, word_size)) write_data;
290 } UncachedMemReq#(numeric type paddr, numeric type word_size) deriving(Bits, Eq);
292 /************************** Interfaces in PLIC ******************************/
294 interface Ifc_global_interrupt;
295 method Action irq_frm_gateway(Bool ir);
298 interface Ifc_program_registers#(numeric type addr_width,numeric type word_size);
299 method ActionValue#(Bit#(TMul#(8,word_size))) prog_reg(UncachedMemReq#(addr_width, word_size) mem_req);
301 /****************************************************************************/
305 Bit#(addr_width) branch_address;
306 Bit#(2) state;} Training_data#(numeric type addr_width) deriving (Bits, Eq);
308 typedef enum {SWAP,ADD,XOR,AND,OR,MINU,MAXU,MIN,MAX} Atomic_funct deriving(Bits,Eq,FShow);
311 Bit#(width) final_result; // the final result for the operation
312 Bit#(5) fflags; // indicates if any exception is generated.
313 }Floating_output#(numeric type width) deriving(Bits,Eq); // data structure of the output FIFO.
316 Inst_addr_misaligned=0,
320 Load_addr_misaligned=4,
322 Store_addr_misaligned=6,
323 Store_access_fault=7,
325 Ecall_from_supervisor=9,
326 Ecall_from_machine=11,
330 `ifdef simulate ,Endsimulation =16 `endif
331 } Exception_cause deriving (Bits,Eq,FShow);
334 Bit#(TSub#(`VADDR,TAdd#(TLog#(`DCACHE_BLOCK_SIZE), TLog#(`DCACHE_WORD_SIZE)))) vtag;
335 Bit#(`DCACHE_TAG_BITS) ptag;
336 Bit#(TLog#(`DCACHE_WAYS)) writeblock;
339 } Linebuff_tag deriving (Bits, Eq, FShow);
341 /*==== Standard =============== */
343 Supervisor_soft_int=1,
346 Supervisor_timer_int=5,
349 Supervisor_external_int=9,
350 Machine_external_int=11,
351 /*=============================*/
352 /*===== Non Standard========= */
357 // Icache_cacheable =13,
358 // Icache_linereplace =14,
359 // Icache_tlbmiss =15,
360 // Icache_misaligned =16,
362 // Cond_branch_taken =18,
363 // Cond_branch_mispredicted =19,
364 // Taken_branch_mispredicted =20,
368 // Dcache_tlbmiss =24,
372 // Dcache_load_miss =28,
373 // Dcache_store_miss =29,
374 // Dcache_atomic_miss =30,
375 // Dcache_cacheable_load =31,
376 // Dcache_cacheable_store =32,
377 // Dcache_cacheable_atomic =33,
378 // Dcache_writebacks =34,
379 // Dcache_linereplace =35,
380 // Dcache_misaligned =36,
381 // Exceptions_taken =37,
382 // Interrupts_taken =38,
383 // Muldiv_instructions =39,
384 // System_instructions =40,
385 // Usermode_cycles =41,
386 // Supervisormode_cycles =42,
387 // Machinemode_cyles =43,
388 // Misprediction_stalls =44,
389 // Interrupt_stalls =45,
390 // Dfence_cycles =46,
391 // Ifence_cycles =47,
392 // Dcache_miss_cycles =48,
393 // Icache_miss_cycles =49,
394 // Fpbusy_cycles =50,
395 // Divisionbusy_cycles =51,
396 // Total_stall_cycles =52,
397 // Pagewalk_cycles =53,
398 // Corebus_cycles =54
399 } Interrupt_cause deriving (Bits,Eq,FShow);
401 typedef union tagged{
402 Exception_cause Exception;
403 Interrupt_cause Interrupt;
405 } Trap_type deriving(Bits,Eq,FShow);
407 function String event_name(Bit#(64) eventnum);
409 'h0000000000000001: return "ICACHE_MISS ";
410 'h0000000000000002: return "ICACHE_CACHEABLE ";
411 'h0000000000000004: return "ICACHE_LINEREPLACE ";
412 'h0000000000000008: return "ICACHE_TLBMISS ";
413 'h0000000000000010: return "ICACHE_MISALIGNED ";
414 'h0000000000000020: return "ICACHE_PREFETCHMISS ";
415 'h0000000000000040: return "COND_BRANCH ";
416 'h0000000000000080: return "COND_BRANCH_TAKEN ";
417 'h0000000000000100: return "COND_BRANCH_MISPREDICTED ";
418 'h0000000000000200: return "TAKEN_BRANCH_MISPREDICTED ";
419 'h0000000000000400: return "UNCOND_JUMPS ";
420 'h0000000000000800: return "SPFPU_INST ";
421 'h0000000000001000: return "DPFPU_INST ";
422 'h0000000000002000: return "DCACHE_TLBMISS ";
423 'h0000000000004000: return "TOTAL_LOADS ";
424 'h0000000000008000: return "TOTAL_STORES ";
425 'h0000000000010000: return "TOTAL_ATOMIC ";
426 'h0000000000020000: return "DCACHE_LOAD_MISS ";
427 'h0000000000040000: return "DCACHE_STORE_MISS ";
428 'h0000000000080000: return "DCACHE_ATOMIC_MISS ";
429 'h0000000000100000: return "DCACHE_CACHEABLE_LOAD ";
430 'h0000000000200000: return "DCACHE_CACHEABLE_STORE ";
431 'h0000000000400000: return "DCACHE_CACHEABLE_ATOMIC ";
432 'h0000000000800000: return "DCACHE_WRITEBACKS ";
433 'h0000000001000000: return "DCACHE_LINEREPLACE ";
434 'h0000000002000000: return "DCACHE_MISALIGNED ";
435 'h0000000004000000: return "EXCEPTIONS_TAKEN ";
436 'h0000000008000000: return "INTERRUPTS_TAKEN ";
437 'h0000000010000000: return "MULDIV_INSTRUCTIONS ";
438 'h0000000020000000: return "MEMORY_INSTRUCTIONS ";
439 'h0000000040000000: return "EXEC_FLUSHES ";
440 'h0000000080000000: return "WB_FLUSHES ";
441 default: return "NO EVENT";
445 /****************************** MMU TYPES *******************************/
453 } Chmod deriving(Bits, Eq);
458 bit w; //allow writes
459 bit x; //allow execute(instruction read)
460 bit u; //allow supervisor
462 bit a; //accessed already
464 } TLB_permissions deriving(Bits, Eq, FShow);
467 Bit#(TSub#(paddr,page_size)) ppn;
468 TLB_permissions tlb_perm;
469 Bit#(asid_width) asid;
471 } To_TLB#(numeric type paddr, numeric type page_size, numeric type asid_width) deriving(Bits,Eq);
474 Bit#(data_width) vaddr;
475 Access_type ld_st_atomic;
476 } DTLB_access#(numeric type data_width) deriving(Bits, Eq);
479 PTW_ready, Handling_PTW, Wait_for_memory, PTW_done, Send_to_memory} PTW_state deriving(Bits, Eq);
482 Load, Store, Execution} Translation_type deriving(Bits, Eq);
485 Translation_type page_type;
486 Bit#(TSub#(vaddr_width,page_offset)) vpn;
487 } Request_PPN_PTW#(numeric type vaddr_width, numeric type page_offset) deriving (Bits,Eq);
490 Translation_type page_type;
491 To_TLB#(paddr_width,page_offset,asid_width) tlb_packet;
492 } Response_PPN_TLB#(numeric type paddr_width, numeric type page_offset, numeric type asid_width) deriving (Bits,Eq);
496 Translation_type page_type;
497 Bit#(data_width) address;
498 } Request_PTE_memory#(numeric type data_width) deriving (Bits,Eq);
502 Bit#(data_width) address;
504 } From_TLB#(numeric type data_width) deriving (Bits, Eq);
507 Bit#(vaddr_width) rs1;
508 Bit#(vaddr_width) rs2;
509 } Fence_VMA_type#(numeric type vaddr_width) deriving (Bits, Eq);
512 Store_pf, Load_pf, Instruction_pf, None} Pf_exception_type deriving (Bits, Eq);
513 /*=============================================================================== */
515 /* =============================== Debug related types ========================== */
516 typedef enum {CPU_CONTINUE,CPU_STOPPED} CPU_State deriving(Bits,Eq,FShow);
526 deriving (Bits ,Eq, FShow);
528 /*======= AXI4 master/slave numbers ======*/
529 typedef 0 Sdram_slave_num;
530 typedef TAdd#(Sdram_slave_num ,`ifdef SDRAM 1 `else 0 `endif ) Sdram_cfg_slave_num;
531 typedef TAdd#(Sdram_cfg_slave_num,`ifdef BOOTROM 1 `else 0 `endif ) BootRom_slave_num ;
532 typedef TAdd#(BootRom_slave_num ,`ifdef Debug 1 `else 0 `endif ) Debug_slave_num ;
533 typedef TAdd#(Debug_slave_num , `ifdef TCMemory 1 `else 0 `endif ) TCM_slave_num;
534 typedef TAdd#(TCM_slave_num ,`ifdef DMA 1 `else 0 `endif ) Dma_slave_num;
535 typedef TAdd#(Dma_slave_num ,1 ) SlowPeripheral_slave_num;
536 typedef TAdd#(SlowPeripheral_slave_num,`ifdef VME 1 `else 0 `endif ) VME_slave_num;
537 typedef TAdd#(VME_slave_num,`ifdef FlexBus 1 `else 0 `endif ) FlexBus_slave_num;
538 typedef TAdd#(FlexBus_slave_num,1) Num_Slaves;
539 typedef 0 Dmem_master_num;
540 typedef 1 Imem_master_num;
541 typedef TAdd#(Imem_master_num , `ifdef Debug 1 `else 0 `endif ) Debug_master_num;
542 typedef TAdd#(Debug_master_num, `ifdef DMA 1 `else 0 `endif ) DMA_master_num;
543 typedef TAdd#(DMA_master_num,1) Num_Masters;
545 /*=============================================================================== */
547 /*===========================================*/