2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
32 #include "cpu/static_inst.hh"
36 #include "sim/core.hh"
40 static TheISA::ExtMachInst nopMachInst
;
42 class NopStaticInst
: public StaticInst
45 NopStaticInst() : StaticInst("gem5 nop", nopMachInst
, No_OpClass
)
49 execute(ExecContext
*xc
, Trace::InstRecord
*traceData
) const override
55 advancePC(TheISA::PCState
&pcState
) const override
61 generateDisassembly(Addr pc
, const SymbolTable
*symtab
) const override
71 StaticInstPtr
StaticInst::nullStaticInstPtr
;
72 StaticInstPtr
StaticInst::nopStaticInstPtr
= new NopStaticInst
;
76 StaticInst::~StaticInst()
78 if (cachedDisassembly
)
79 delete cachedDisassembly
;
83 StaticInst::hasBranchTarget(const TheISA::PCState
&pc
, ThreadContext
*tc
,
84 TheISA::PCState
&tgt
) const
87 tgt
= branchTarget(pc
);
91 if (isIndirectCtrl()) {
92 tgt
= branchTarget(tc
);
100 StaticInst::fetchMicroop(MicroPC upc
) const
102 panic("StaticInst::fetchMicroop() called on instruction "
103 "that is not microcoded.");
107 StaticInst::branchTarget(const TheISA::PCState
&pc
) const
109 panic("StaticInst::branchTarget() called on instruction "
110 "that is not a PC-relative branch.");
115 StaticInst::branchTarget(ThreadContext
*tc
) const
117 panic("StaticInst::branchTarget() called on instruction "
118 "that is not an indirect branch.");
123 StaticInst::disassemble(Addr pc
, const SymbolTable
*symtab
) const
125 if (!cachedDisassembly
)
126 cachedDisassembly
= new string(generateDisassembly(pc
, symtab
));
128 return *cachedDisassembly
;
132 StaticInst::printFlags(std::ostream
&outs
,
133 const std::string
&separator
) const
135 bool printed_a_flag
= false;
137 for (unsigned int flag
= IsNop
; flag
< Num_Flags
; flag
++) {
142 outs
<< FlagsStrings
[flag
];
143 printed_a_flag
= true;