src/decoder/power_decoder2.py

   1 """Power ISA Decoder second stage
   2
   3 based on Anton Blanchard microwatt decode2.vhdl
   4
   5 """
   6 from nmigen import Module, Elaboratable, Signal, Mux, Const
   7 from nmigen.cli import rtlil
   8
   9 from power_decoder import create_pdecode
  10 from power_enums import (InternalOp, CryIn, Function, LdstLen,
  11                          In1Sel, In2Sel, In3Sel, OutSel, SPR, RC)
  12
  13
  14 class DecodeA(Elaboratable):
  15     """DecodeA from instruction
  16
  17     decodes register RA, whether immediate-zero, implicit and
  18     explicit CSRs
  19     """
  20
  21     def __init__(self, dec):
  22         self.dec = dec
  23         self.sel_in = Signal(In1Sel, reset_less=True)
  24         self.insn_in = Signal(32, reset_less=True)
  25         self.reg_out = Data(5, name="reg_a")
  26         self.immz_out = Signal(reset_less=True)
  27         self.spr_out = Data(10, "spr_a")
  28
  29     def elaborate(self, platform):
  30         m = Module()
  31         comb = m.d.comb
  32
  33         # select Register A field
  34         with m.If((self.sel_in == In1Sel.RA) |
  35                   ((self.sel_in == In1Sel.RA_OR_ZERO) &
  36                    (self.reg_out.data != Const(0, 5)))):
  37             comb += self.reg_out.data.eq(self.dec.RA[0:-1])
  38             comb += self.reg_out.ok.eq(1)
  39
  40         # zero immediate requested
  41         with m.If((self.sel_in == In1Sel.RA_OR_ZERO) &
  42                    (self.reg_out.data == Const(0, 5))):
  43             comb += self.immz_out.eq(1)
  44
  45         # decode SPR1 based on instruction type
  46         op = self.dec.op
  47         # BC or BCREG: potential implicit register (CTR)
  48         with m.If((op.internal_op == InternalOp.OP_BC) |
  49                   (op.internal_op == InternalOp.OP_BCREG)):
  50             with m.If(~self.dec.BO[2]): # 3.0B p38 BO2=0, use CTR reg
  51                 comb += self.spr_out.data.eq(SPR.CTR) # constant: CTR
  52                 comb += self.spr_out.ok.eq(1)
  53         # MFSPR or MTSPR: move-from / move-to SPRs
  54         with m.If((op.internal_op == InternalOp.OP_MFSPR) |
  55                   (op.internal_op == InternalOp.OP_MTSPR)):
  56             comb += self.spr_out.data.eq(self.dec.SPR[0:-1]) # SPR field, XFX
  57             comb += self.spr_out.ok.eq(1)
  58
  59         return m
  60
  61 class Data:
  62
  63     def __init__(self, width, name):
  64
  65         self.data = Signal(width, name=name, reset_less=True)
  66         self.ok = Signal(name="%s_ok" % name, reset_less=True)
  67
  68     def eq(self, rhs):
  69         return [self.data.eq(rhs.data),
  70                 self.ok.eq(rhs.ok)]
  71
  72     def ports(self):
  73         return [self.data, self.ok]
  74
  75
  76 class DecodeB(Elaboratable):
  77     """DecodeB from instruction
  78
  79     decodes register RB, different forms of immediate (signed, unsigned),
  80     and implicit SPRs
  81     """
  82
  83     def __init__(self, dec):
  84         self.dec = dec
  85         self.sel_in = Signal(In2Sel, reset_less=True)
  86         self.insn_in = Signal(32, reset_less=True)
  87         self.reg_out = Data(5, "reg_b")
  88         self.imm_out = Data(64, "imm_b")
  89         self.spr_out = Data(10, "spr_b")
  90
  91     def elaborate(self, platform):
  92         m = Module()
  93         comb = m.d.comb
  94
  95         # select Register B field
  96         with m.Switch(self.sel_in):
  97             with m.Case(In2Sel.RB):
  98                 comb += self.reg_out.data.eq(self.dec.RB[0:-1])
  99                 comb += self.reg_out.ok.eq(1)
 100             with m.Case(In2Sel.CONST_UI):
 101                 comb += self.imm_out.data.eq(self.dec.UI[0:-1])
 102                 comb += self.imm_out.ok.eq(1)
 103             with m.Case(In2Sel.CONST_SI): # TODO: sign-extend here?
 104                 comb += self.imm_out.data.eq(self.dec.SI[0:-1])
 105                 comb += self.imm_out.ok.eq(1)
 106             with m.Case(In2Sel.CONST_UI_HI):
 107                 comb += self.imm_out.data.eq(self.dec.UI[0:-1]<<4)
 108                 comb += self.imm_out.ok.eq(1)
 109             with m.Case(In2Sel.CONST_SI_HI): # TODO: sign-extend here?
 110                 comb += self.imm_out.data.eq(self.dec.SI[0:-1]<<4)
 111                 comb += self.imm_out.ok.eq(1)
 112             with m.Case(In2Sel.CONST_LI):
 113                 comb += self.imm_out.data.eq(self.dec.LI[0:-1]<<2)
 114                 comb += self.imm_out.ok.eq(1)
 115             with m.Case(In2Sel.CONST_BD):
 116                 comb += self.imm_out.data.eq(self.dec.BD[0:-1]<<2)
 117                 comb += self.imm_out.ok.eq(1)
 118             with m.Case(In2Sel.CONST_DS):
 119                 comb += self.imm_out.data.eq(self.dec.DS[0:-1]<<2)
 120                 comb += self.imm_out.ok.eq(1)
 121             with m.Case(In2Sel.CONST_M1):
 122                 comb += self.imm_out.data.eq(~Const(0, 64)) # all 1s
 123                 comb += self.imm_out.ok.eq(1)
 124             with m.Case(In2Sel.CONST_SH):
 125                 comb += self.imm_out.data.eq(self.dec.sh[0:-1])
 126                 comb += self.imm_out.ok.eq(1)
 127             with m.Case(In2Sel.CONST_SH32):
 128                 comb += self.imm_out.data.eq(self.dec.SH32[0:-1])
 129                 comb += self.imm_out.ok.eq(1)
 130
 131         # decode SPR2 based on instruction type
 132         op = self.dec.op
 133         # BCREG implicitly uses CTR or LR for 2nd reg
 134         with m.If(op.internal_op == InternalOp.OP_BCREG):
 135             with m.If(self.dec.FormXL.XO[9]): # 3.0B p38 top bit of XO
 136                 comb += self.spr_out.data.eq(SPR.CTR)
 137             with m.Else():
 138                 comb += self.spr_out.data.eq(SPR.LR)
 139             comb += self.spr_out.ok.eq(1)
 140
 141         return m
 142
 143
 144 class DecodeC(Elaboratable):
 145     """DecodeC from instruction
 146
 147     decodes register RC
 148     """
 149
 150     def __init__(self, dec):
 151         self.dec = dec
 152         self.sel_in = Signal(In3Sel, reset_less=True)
 153         self.insn_in = Signal(32, reset_less=True)
 154         self.reg_out = Data(5, "reg_c")
 155
 156     def elaborate(self, platform):
 157         m = Module()
 158         comb = m.d.comb
 159
 160         # select Register C field
 161         with m.If(self.sel_in == In3Sel.RS):
 162             comb += self.reg_out.data.eq(self.dec.RS[0:-1])
 163             comb += self.reg_out.ok.eq(1)
 164
 165         return m
 166
 167
 168 class DecodeOut(Elaboratable):
 169     """DecodeOut from instruction
 170
 171     decodes output register RA, RT or SPR
 172     """
 173
 174     def __init__(self, dec):
 175         self.dec = dec
 176         self.sel_in = Signal(OutSel, reset_less=True)
 177         self.insn_in = Signal(32, reset_less=True)
 178         self.reg_out = Data(5, "reg_o")
 179         self.spr_out = Data(10, "spr_o")
 180
 181     def elaborate(self, platform):
 182         m = Module()
 183         comb = m.d.comb
 184
 185         # select Register out field
 186         with m.Switch(self.sel_in):
 187             with m.Case(OutSel.RT):
 188                 comb += self.reg_out.data.eq(self.dec.RT[0:-1])
 189                 comb += self.reg_out.ok.eq(1)
 190             with m.Case(OutSel.RA):
 191                 comb += self.reg_out.data.eq(self.dec.RA[0:-1])
 192                 comb += self.reg_out.ok.eq(1)
 193             with m.Case(OutSel.SPR):
 194                 comb += self.spr_out.data.eq(self.dec.SPR[0:-1]) # from XFX
 195                 comb += self.spr_out.ok.eq(1)
 196
 197         return m
 198
 199
 200 class DecodeRC(Elaboratable):
 201     """DecodeRc from instruction
 202
 203     decodes Record bit Rc
 204     """
 205     def __init__(self, dec):
 206         self.dec = dec
 207         self.sel_in = Signal(RC, reset_less=True)
 208         self.insn_in = Signal(32, reset_less=True)
 209         self.rc_out = Data(1, "rc")
 210
 211     def elaborate(self, platform):
 212         m = Module()
 213         comb = m.d.comb
 214
 215         # select Record bit out field
 216         with m.Switch(self.sel_in):
 217             with m.Case(RC.RC):
 218                 comb += self.rc_out.data.eq(self.dec.Rc[0:-1])
 219                 comb += self.rc_out.ok.eq(1)
 220             with m.Case(RC.ONE):
 221                 comb += self.rc_out.data.eq(1)
 222                 comb += self.rc_out.ok.eq(1)
 223             with m.Case(RC.NONE):
 224                 comb += self.rc_out.data.eq(0)
 225                 comb += self.rc_out.ok.eq(1)
 226
 227         return m
 228
 229
 230 class DecodeOE(Elaboratable):
 231     """DecodeOE from instruction
 232
 233     decodes OE field: uses RC decode detection which might not be good
 234
 235     -- For now, use "rc" in the decode table to decide whether oe exists.
 236     -- This is not entirely correct architecturally: For mulhd and
 237     -- mulhdu, the OE field is reserved. It remains to be seen what an
 238     -- actual POWER9 does if we set it on those instructions, for now we
 239     -- test that further down when assigning to the multiplier oe input.
 240     """
 241     def __init__(self, dec):
 242         self.dec = dec
 243         self.sel_in = Signal(RC, reset_less=True)
 244         self.insn_in = Signal(32, reset_less=True)
 245         self.oe_out = Data(1, "oe")
 246
 247     def elaborate(self, platform):
 248         m = Module()
 249         comb = m.d.comb
 250
 251         # select OE bit out field
 252         with m.Switch(self.sel_in):
 253             with m.Case(RC.RC):
 254                 comb += self.oe_out.data.eq(self.dec.OE[0:-1])
 255                 comb += self.oe_out.ok.eq(1)
 256
 257         return m
 258
 259
 260 class XerBits:
 261     def __init__(self):
 262         self.ca = Signal(reset_less=True)
 263         self.ca32 = Signal(reset_less=True)
 264         self.ov = Signal(reset_less=True)
 265         self.ov32 = Signal(reset_less=True)
 266         self.so = Signal(reset_less=True)
 267
 268     def ports(self):
 269         return [self.ca, self.ca32, self.ov, self.ov32, self.so, ]
 270
 271
 272 class Decode2ToExecute1Type:
 273
 274     def __init__(self):
 275
 276         self.valid = Signal(reset_less=True)
 277         self.insn_type = Signal(InternalOp, reset_less=True)
 278         self.nia = Signal(64, reset_less=True)
 279         self.write_reg = Data(5, name="rego")
 280         self.read_reg1 = Data(5, name="reg1")
 281         self.read_reg2 = Data(5, name="reg2")
 282         self.read_reg3 = Data(5, name="reg3")
 283         self.imm_data = Data(64, name="imm")
 284         self.write_spr = Data(10, name="spro")
 285         self.read_spr1 = Data(10, name="spr1")
 286         self.read_spr2 = Data(10, name="spr2")
 287         #self.read_data1 = Signal(64, reset_less=True)
 288         #self.read_data2 = Signal(64, reset_less=True)
 289         #self.read_data3 = Signal(64, reset_less=True)
 290         #self.cr = Signal(32, reset_less=True) # NO: this is from the CR SPR
 291         #self.xerc = XerBits() # NO: this is from the XER SPR
 292         self.lk = Signal(reset_less=True)
 293         self.rc = Data(1, "rc")
 294         self.oe = Data(1, "oe")
 295         self.invert_a = Signal(reset_less=True)
 296         self.invert_out = Signal(reset_less=True)
 297         self.input_carry = Signal(CryIn, reset_less=True)
 298         self.output_carry = Signal(reset_less=True)
 299         self.input_cr = Signal(reset_less=True)
 300         self.output_cr = Signal(reset_less=True)
 301         self.is_32bit = Signal(reset_less=True)
 302         self.is_signed = Signal(reset_less=True)
 303         self.insn = Signal(32, reset_less=True)
 304         self.data_len = Signal(4, reset_less=True) # bytes
 305         self.byte_reverse  = Signal(reset_less=True)
 306         self.sign_extend  = Signal(reset_less=True)# do we need this?
 307         self.update  = Signal(reset_less=True) # is this an update instruction?
 308
 309     def ports(self):
 310         return [self.valid, self.insn_type, self.nia,
 311                 #self.read_data1, self.read_data2, self.read_data3,
 312                 #self.cr,
 313                 self.lk,
 314                 self.invert_a, self.invert_out,
 315                 self.input_carry, self.output_carry,
 316                 self.input_cr, self.output_cr,
 317                 self.is_32bit, self.is_signed,
 318                 self.insn,
 319                 self.data_len, self.byte_reverse , self.sign_extend ,
 320                 self.update] + \
 321                 self.oe.ports() + \
 322                 self.rc.ports() + \
 323                 self.write_spr.ports() + \
 324                 self.read_spr1.ports() + \
 325                 self.read_spr2.ports() + \
 326                 self.write_reg.ports() + \
 327                 self.read_reg1.ports() + \
 328                 self.read_reg2.ports() + \
 329                 self.read_reg3.ports() + \
 330                 self.imm_data.ports()
 331                 # + self.xerc.ports()
 332
 333 class PowerDecode2(Elaboratable):
 334
 335     def __init__(self, dec):
 336
 337         self.dec = dec
 338         self.e = Decode2ToExecute1Type()
 339
 340     def ports(self):
 341         return self.dec.ports() + self.e.ports()
 342
 343     def elaborate(self, platform):
 344         m = Module()
 345         comb = m.d.comb
 346
 347         # set up submodule decoders
 348         m.submodules.dec = self.dec
 349         m.submodules.dec_a = dec_a = DecodeA(self.dec)
 350         m.submodules.dec_b = dec_b = DecodeB(self.dec)
 351         m.submodules.dec_c = dec_c = DecodeC(self.dec)
 352         m.submodules.dec_o = dec_o = DecodeOut(self.dec)
 353         m.submodules.dec_rc = dec_rc = DecodeRC(self.dec)
 354         m.submodules.dec_oe = dec_oe = DecodeOE(self.dec)
 355
 356         # copy instruction through...
 357         for i in [self.e.insn, dec_a.insn_in, dec_b.insn_in,
 358                   dec_c.insn_in, dec_o.insn_in, dec_rc.insn_in,
 359                   dec_oe.insn_in]:
 360             comb += i.eq(self.dec.opcode_in)
 361
 362         # ...and subdecoders' input fields
 363         comb += dec_a.sel_in.eq(self.dec.op.in1_sel)
 364         comb += dec_b.sel_in.eq(self.dec.op.in2_sel)
 365         comb += dec_c.sel_in.eq(self.dec.op.in3_sel)
 366         comb += dec_o.sel_in.eq(self.dec.op.out_sel)
 367         comb += dec_rc.sel_in.eq(self.dec.op.rc_sel)
 368         comb += dec_oe.sel_in.eq(self.dec.op.rc_sel) # XXX should be OE sel
 369
 370         # decode LD/ST length
 371         with m.Switch(self.dec.op.ldst_len):
 372             with m.Case(LdstLen.is1B):
 373                 comb += self.e.data_len.eq(1)
 374             with m.Case(LdstLen.is2B):
 375                 comb += self.e.data_len.eq(2)
 376             with m.Case(LdstLen.is4B):
 377                 comb += self.e.data_len.eq(4)
 378             with m.Case(LdstLen.is8B):
 379                 comb += self.e.data_len.eq(8)
 380
 381         #comb += self.e.nia.eq(self.dec.nia) # XXX TODO
 382         itype = Mux(self.dec.op.function_unit == Function.NONE,
 383                     InternalOp.OP_ILLEGAL,
 384                     self.dec.op.internal_op)
 385         comb += self.e.insn_type.eq(itype)
 386
 387         # registers a, b, c and out
 388         comb += self.e.read_reg1.eq(dec_a.reg_out)
 389         comb += self.e.read_reg2.eq(dec_b.reg_out)
 390         comb += self.e.read_reg3.eq(dec_c.reg_out)
 391         comb += self.e.write_reg.eq(dec_o.reg_out)
 392         comb += self.e.imm_data.eq(dec_b.imm_out)
 393
 394         # rc and oe out
 395         comb += self.e.rc.eq(dec_rc.rc_out)
 396         comb += self.e.oe.eq(dec_oe.oe_out)
 397
 398         # SPRs out
 399         comb += self.e.read_spr1.eq(dec_a.spr_out)
 400         comb += self.e.read_spr2.eq(dec_b.spr_out)
 401         comb += self.e.write_spr.eq(dec_o.spr_out)
 402
 403         # decoded/selected instruction flags
 404         comb += self.e.invert_a.eq(self.dec.op.inv_a)
 405         comb += self.e.invert_out.eq(self.dec.op.inv_out)
 406         comb += self.e.input_carry.eq(self.dec.op.cry_in)
 407         comb += self.e.output_carry.eq(self.dec.op.cry_out)
 408         comb += self.e.is_32bit.eq(self.dec.op.is_32b)
 409         comb += self.e.is_signed.eq(self.dec.op.sgn)
 410         with m.If(self.dec.op.lk):
 411             comb += self.e.lk.eq(self.dec.LK[0:-1]) # XXX TODO: accessor
 412
 413         comb += self.e.byte_reverse.eq(self.dec.op.br)
 414         comb += self.e.sign_extend.eq(self.dec.op.sgn_ext)
 415         comb += self.e.update.eq(self.dec.op.upd)
 416
 417         comb += self.e.input_cr.eq(self.dec.op.cr_in)
 418         comb += self.e.output_cr.eq(self.dec.op.cr_out)
 419
 420         return m
 421
 422
 423 if __name__ == '__main__':
 424     pdecode = create_pdecode()
 425     dec2 = PowerDecode2(pdecode)
 426     vl = rtlil.convert(dec2, ports=dec2.ports() + pdecode.ports())
 427     with open("dec2.il", "w") as f:
 428         f.write(vl)
 429