dd72ecd4bee3905cc4b960e7f6c6b779f0def711
1 from nmigen
.compat
.sim
import run_simulation
2 from nmigen
.cli
import verilog
, rtlil
3 from nmigen
import Module
, Signal
, Elaboratable
5 from nmutil
.latch
import SRLatch
8 class ComputationUnitNoDelay(Elaboratable
):
9 def __init__(self
, rwid
, opwid
, alu
):
13 self
.go_rd_i
= Signal(reset_less
=True) # go read in
14 self
.go_wr_i
= Signal(reset_less
=True) # go write in
15 self
.issue_i
= Signal(reset_less
=True) # fn issue in
17 self
.oper_i
= Signal(opwid
, reset_less
=True) # opcode in
18 self
.src1_i
= Signal(rwid
, reset_less
=True) # oper1 in
19 self
.src2_i
= Signal(rwid
, reset_less
=True) # oper2 in
21 self
.busy_o
= Signal(reset_less
=True) # fn busy out
22 self
.data_o
= Signal(rwid
, reset_less
=True) # Dest out
23 self
.req_rel_o
= Signal(reset_less
=True) # release request out (valid_o)
25 def elaborate(self
, platform
):
27 m
.submodules
.alu
= self
.alu
28 m
.submodules
.src_l
= src_l
= SRLatch(sync
=False)
29 m
.submodules
.opc_l
= opc_l
= SRLatch(sync
=False)
30 m
.submodules
.req_l
= req_l
= SRLatch(sync
=False)
32 # This is fascinating and very important to observe that this
33 # is in effect a "3-way revolving door". At no time may all 3
34 # latches be set at the same time.
36 # opcode latch (not using go_rd_i)
37 m
.d
.comb
+= opc_l
.s
.eq(self
.go_wr_i
)
38 m
.d
.comb
+= opc_l
.r
.eq(self
.issue_i
)
40 # src operand latch (not using go_wr_i)
41 m
.d
.comb
+= src_l
.s
.eq(self
.issue_i
)
42 m
.d
.comb
+= src_l
.r
.eq(self
.go_rd_i
)
44 # dest operand latch (not using issue_i)
45 m
.d
.comb
+= req_l
.s
.eq(self
.go_rd_i
)
46 m
.d
.comb
+= req_l
.r
.eq(self
.go_wr_i
)
49 m
.d
.comb
+= self
.busy_o
.eq(opc_l
.qn
) # busy out
50 m
.d
.comb
+= self
.req_rel_o
.eq(req_l
.qn
& opc_l
.q
) # request release out
53 m
.d
.comb
+= self
.alu
.a
.eq(self
.src1_i
)
54 m
.d
.comb
+= self
.alu
.b
.eq(self
.src2_i
)
57 m
.d
.comb
+= self
.alu
.op
.eq(self
.oper_i
)
60 m
.d
.comb
+= self
.data_o
.eq(self
.alu
.o
)
64 def scoreboard_sim(dut
):
65 yield dut
.dest_i
.eq(1)
66 yield dut
.issue_i
.eq(1)
68 yield dut
.issue_i
.eq(0)
70 yield dut
.src1_i
.eq(1)
71 yield dut
.issue_i
.eq(1)
75 yield dut
.issue_i
.eq(0)
77 yield dut
.go_read_i
.eq(1)
79 yield dut
.go_read_i
.eq(0)
81 yield dut
.go_write_i
.eq(1)
83 yield dut
.go_write_i
.eq(0)
86 def test_scoreboard():
87 dut
= Scoreboard(32, 8)
88 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
89 with
open("test_scoreboard.il", "w") as f
:
92 run_simulation(dut
, scoreboard_sim(dut
), vcd_name
='test_scoreboard.vcd')
94 if __name__
== '__main__':