1 from nmigen
.compat
.sim
import run_simulation
2 from nmigen
.cli
import verilog
, rtlil
3 from nmigen
import Module
, Const
, Signal
, Array
, Cat
, Elaboratable
5 from regfile
.regfile
import RegFileArray
, treereduce
6 from scoreboard
.fu_fu_matrix
import FUFUDepMatrix
7 from scoreboard
.fu_reg_matrix
import FURegDepMatrix
8 from scoreboard
.global_pending
import GlobalPending
9 from scoreboard
.group_picker
import GroupPicker
10 from scoreboard
.issue_unit
import IssueUnitGroup
, IssueUnitArray
, RegDecode
11 from scoreboard
.shadow
import ShadowMatrix
, BranchSpeculationRecord
12 from scoreboard
.instruction_q
import Instruction
, InstructionQ
14 from compalu
import ComputationUnitNoDelay
16 from alu_hier
import ALU
, BranchALU
17 from nmutil
.latch
import SRLatch
18 from nmutil
.nmoperator
import eq
20 from random
import randint
, seed
21 from copy
import deepcopy
25 class Memory(Elaboratable
):
26 def __init__(self
, regwid
, addrw
):
27 self
.ddepth
= regwid
/8
28 depth
= (1<<addrw
) / self
.ddepth
29 self
.adr
= Signal(addrw
)
30 self
.dat_r
= Signal(regwid
)
31 self
.dat_w
= Signal(regwid
)
33 self
.mem
= Memory(width
=regwid
, depth
=depth
, init
=range(0, depth
))
35 def elaborate(self
, platform
):
37 m
.submodules
.rdport
= rdport
= self
.mem
.read_port()
38 m
.submodules
.wrport
= wrport
= self
.mem
.write_port()
40 rdport
.addr
.eq(self
.adr
[self
.ddepth
:]), # ignore low bits
41 self
.dat_r
.eq(rdport
.data
),
42 wrport
.addr
.eq(self
.adr
),
43 wrport
.data
.eq(self
.dat_w
),
44 wrport
.en
.eq(self
.we
),
50 def __init__(self
, regwid
, addrw
):
52 self
.ddepth
= regwid
//8
53 depth
= (1<<addrw
) // self
.ddepth
54 self
.mem
= list(range(0, depth
))
57 return self
.mem
[addr
>>self
.ddepth
]
59 def st(self
, addr
, data
):
60 self
.mem
[addr
>>self
.ddepth
] = data
& ((1<<self
.regwid
)-1)
63 class CompUnitsBase(Elaboratable
):
64 """ Computation Unit Base class.
66 Amazingly, this class works recursively. It's supposed to just
67 look after some ALUs (that can handle the same operations),
68 grouping them together, however it turns out that the same code
69 can also group *groups* of Computation Units together as well.
71 Basically it was intended just to concatenate the ALU's issue,
72 go_rd etc. signals together, which start out as bits and become
73 sequences. Turns out that the same trick works just as well
76 So this class may be used recursively to present a top-level
77 sequential concatenation of all the signals in and out of
78 ALUs, whilst at the same time making it convenient to group
81 At the lower level, the intent is that groups of (identical)
82 ALUs may be passed the same operation. Even beyond that,
83 the intent is that that group of (identical) ALUs actually
84 share the *same pipeline* and as such become a "Concurrent
85 Computation Unit" as defined by Mitch Alsup (see section
88 def __init__(self
, rwid
, units
):
91 * :rwid: bit width of register file(s) - both FP and INT
92 * :units: sequence of ALUs (or CompUnitsBase derivatives)
97 if units
and isinstance(units
[0], CompUnitsBase
):
100 self
.n_units
+= u
.n_units
102 self
.n_units
= len(units
)
104 n_units
= self
.n_units
107 self
.issue_i
= Signal(n_units
, reset_less
=True)
108 self
.go_rd_i
= Signal(n_units
, reset_less
=True)
109 self
.go_wr_i
= Signal(n_units
, reset_less
=True)
110 self
.shadown_i
= Signal(n_units
, reset_less
=True)
111 self
.go_die_i
= Signal(n_units
, reset_less
=True)
114 self
.busy_o
= Signal(n_units
, reset_less
=True)
115 self
.rd_rel_o
= Signal(n_units
, reset_less
=True)
116 self
.req_rel_o
= Signal(n_units
, reset_less
=True)
118 # in/out register data (note: not register#, actual data)
119 self
.data_o
= Signal(rwid
, reset_less
=True)
120 self
.src1_i
= Signal(rwid
, reset_less
=True)
121 self
.src2_i
= Signal(rwid
, reset_less
=True)
124 def elaborate(self
, platform
):
128 for i
, alu
in enumerate(self
.units
):
129 setattr(m
.submodules
, "comp%d" % i
, alu
)
139 for alu
in self
.units
:
140 req_rel_l
.append(alu
.req_rel_o
)
141 rd_rel_l
.append(alu
.rd_rel_o
)
142 shadow_l
.append(alu
.shadown_i
)
143 godie_l
.append(alu
.go_die_i
)
144 go_wr_l
.append(alu
.go_wr_i
)
145 go_rd_l
.append(alu
.go_rd_i
)
146 issue_l
.append(alu
.issue_i
)
147 busy_l
.append(alu
.busy_o
)
148 comb
+= self
.rd_rel_o
.eq(Cat(*rd_rel_l
))
149 comb
+= self
.req_rel_o
.eq(Cat(*req_rel_l
))
150 comb
+= self
.busy_o
.eq(Cat(*busy_l
))
151 comb
+= Cat(*godie_l
).eq(self
.go_die_i
)
152 comb
+= Cat(*shadow_l
).eq(self
.shadown_i
)
153 comb
+= Cat(*go_wr_l
).eq(self
.go_wr_i
)
154 comb
+= Cat(*go_rd_l
).eq(self
.go_rd_i
)
155 comb
+= Cat(*issue_l
).eq(self
.issue_i
)
157 # connect data register input/output
159 # merge (OR) all integer FU / ALU outputs to a single value
160 # bit of a hack: treereduce needs a list with an item named "data_o"
162 data_o
= treereduce(self
.units
)
163 comb
+= self
.data_o
.eq(data_o
)
165 for i
, alu
in enumerate(self
.units
):
166 comb
+= alu
.src1_i
.eq(self
.src1_i
)
167 comb
+= alu
.src2_i
.eq(self
.src2_i
)
172 class CompUnitALUs(CompUnitsBase
):
174 def __init__(self
, rwid
, opwid
):
177 * :rwid: bit width of register file(s) - both FP and INT
178 * :opwid: operand bit width
183 self
.oper_i
= Signal(opwid
, reset_less
=True)
184 self
.imm_i
= Signal(rwid
, reset_less
=True)
193 for alu
in [add
, sub
, mul
, shf
]:
194 aluopwid
= 3 # extra bit for immediate mode
195 units
.append(ComputationUnitNoDelay(rwid
, aluopwid
, alu
))
197 CompUnitsBase
.__init
__(self
, rwid
, units
)
199 def elaborate(self
, platform
):
200 m
= CompUnitsBase
.elaborate(self
, platform
)
203 # hand the same operation to all units, only lower 2 bits though
204 for alu
in self
.units
:
205 comb
+= alu
.oper_i
[0:3].eq(self
.oper_i
)
206 comb
+= alu
.imm_i
.eq(self
.imm_i
)
211 class CompUnitBR(CompUnitsBase
):
213 def __init__(self
, rwid
, opwid
):
216 * :rwid: bit width of register file(s) - both FP and INT
217 * :opwid: operand bit width
219 Note: bgt unit is returned so that a shadow unit can be created
225 self
.oper_i
= Signal(opwid
, reset_less
=True)
228 self
.bgt
= BranchALU(rwid
)
229 self
.br1
= ComputationUnitNoDelay(rwid
, 3, self
.bgt
)
230 CompUnitsBase
.__init
__(self
, rwid
, [self
.br1
])
232 def elaborate(self
, platform
):
233 m
= CompUnitsBase
.elaborate(self
, platform
)
236 # hand the same operation to all units
237 for alu
in self
.units
:
238 comb
+= alu
.oper_i
.eq(self
.oper_i
)
243 class FunctionUnits(Elaboratable
):
245 def __init__(self
, n_regs
, n_int_alus
):
247 self
.n_int_alus
= n_int_alus
249 self
.dest_i
= Signal(n_regs
, reset_less
=True) # Dest R# in
250 self
.src1_i
= Signal(n_regs
, reset_less
=True) # oper1 R# in
251 self
.src2_i
= Signal(n_regs
, reset_less
=True) # oper2 R# in
253 self
.g_int_rd_pend_o
= Signal(n_regs
, reset_less
=True)
254 self
.g_int_wr_pend_o
= Signal(n_regs
, reset_less
=True)
256 self
.dest_rsel_o
= Signal(n_regs
, reset_less
=True) # dest reg (bot)
257 self
.src1_rsel_o
= Signal(n_regs
, reset_less
=True) # src1 reg (bot)
258 self
.src2_rsel_o
= Signal(n_regs
, reset_less
=True) # src2 reg (bot)
260 self
.req_rel_i
= Signal(n_int_alus
, reset_less
= True)
261 self
.readable_o
= Signal(n_int_alus
, reset_less
=True)
262 self
.writable_o
= Signal(n_int_alus
, reset_less
=True)
264 self
.go_rd_i
= Signal(n_int_alus
, reset_less
=True)
265 self
.go_wr_i
= Signal(n_int_alus
, reset_less
=True)
266 self
.go_die_i
= Signal(n_int_alus
, reset_less
=True)
267 self
.req_rel_o
= Signal(n_int_alus
, reset_less
=True)
268 self
.fn_issue_i
= Signal(n_int_alus
, reset_less
=True)
270 # Note: FURegs wr_pend_o is also outputted from here, for use in WaWGrid
272 def elaborate(self
, platform
):
277 n_intfus
= self
.n_int_alus
279 # Integer FU-FU Dep Matrix
280 intfudeps
= FUFUDepMatrix(n_intfus
, n_intfus
)
281 m
.submodules
.intfudeps
= intfudeps
282 # Integer FU-Reg Dep Matrix
283 intregdeps
= FURegDepMatrix(n_intfus
, self
.n_regs
)
284 m
.submodules
.intregdeps
= intregdeps
286 comb
+= self
.g_int_rd_pend_o
.eq(intregdeps
.rd_rsel_o
)
287 comb
+= self
.g_int_wr_pend_o
.eq(intregdeps
.wr_rsel_o
)
289 comb
+= intregdeps
.rd_pend_i
.eq(intregdeps
.rd_rsel_o
)
290 comb
+= intregdeps
.wr_pend_i
.eq(intregdeps
.wr_rsel_o
)
292 comb
+= intfudeps
.rd_pend_i
.eq(intregdeps
.rd_pend_o
)
293 comb
+= intfudeps
.wr_pend_i
.eq(intregdeps
.wr_pend_o
)
294 self
.wr_pend_o
= intregdeps
.wr_pend_o
# also output for use in WaWGrid
296 comb
+= intfudeps
.issue_i
.eq(self
.fn_issue_i
)
297 comb
+= intfudeps
.go_rd_i
.eq(self
.go_rd_i
)
298 comb
+= intfudeps
.go_wr_i
.eq(self
.go_wr_i
)
299 comb
+= intfudeps
.go_die_i
.eq(self
.go_die_i
)
300 comb
+= self
.readable_o
.eq(intfudeps
.readable_o
)
301 comb
+= self
.writable_o
.eq(intfudeps
.writable_o
)
303 # Connect function issue / arrays, and dest/src1/src2
304 comb
+= intregdeps
.dest_i
.eq(self
.dest_i
)
305 comb
+= intregdeps
.src1_i
.eq(self
.src1_i
)
306 comb
+= intregdeps
.src2_i
.eq(self
.src2_i
)
308 comb
+= intregdeps
.go_rd_i
.eq(self
.go_rd_i
)
309 comb
+= intregdeps
.go_wr_i
.eq(self
.go_wr_i
)
310 comb
+= intregdeps
.go_die_i
.eq(self
.go_die_i
)
311 comb
+= intregdeps
.issue_i
.eq(self
.fn_issue_i
)
313 comb
+= self
.dest_rsel_o
.eq(intregdeps
.dest_rsel_o
)
314 comb
+= self
.src1_rsel_o
.eq(intregdeps
.src1_rsel_o
)
315 comb
+= self
.src2_rsel_o
.eq(intregdeps
.src2_rsel_o
)
320 class Scoreboard(Elaboratable
):
321 def __init__(self
, rwid
, n_regs
):
324 * :rwid: bit width of register file(s) - both FP and INT
325 * :n_regs: depth of register file(s) - number of FP and INT regs
331 self
.intregs
= RegFileArray(rwid
, n_regs
)
332 self
.fpregs
= RegFileArray(rwid
, n_regs
)
334 # issue q needs to get at these
335 self
.aluissue
= IssueUnitGroup(4)
336 self
.brissue
= IssueUnitGroup(1)
338 self
.alu_oper_i
= Signal(4, reset_less
=True)
339 self
.alu_imm_i
= Signal(rwid
, reset_less
=True)
340 self
.br_oper_i
= Signal(4, reset_less
=True)
343 self
.int_dest_i
= Signal(max=n_regs
, reset_less
=True) # Dest R# in
344 self
.int_src1_i
= Signal(max=n_regs
, reset_less
=True) # oper1 R# in
345 self
.int_src2_i
= Signal(max=n_regs
, reset_less
=True) # oper2 R# in
346 self
.reg_enable_i
= Signal(reset_less
=True) # enable reg decode
349 self
.issue_o
= Signal(reset_less
=True) # instruction was accepted
350 self
.busy_o
= Signal(reset_less
=True) # at least one CU is busy
352 # for branch speculation experiment. branch_direction = 0 if
353 # the branch hasn't been met yet. 1 indicates "success", 2 is "fail"
354 # branch_succ and branch_fail are requests to have the current
355 # instruction be dependent on the branch unit "shadow" capability.
356 self
.branch_succ_i
= Signal(reset_less
=True)
357 self
.branch_fail_i
= Signal(reset_less
=True)
358 self
.branch_direction_o
= Signal(2, reset_less
=True)
360 def elaborate(self
, platform
):
365 m
.submodules
.intregs
= self
.intregs
366 m
.submodules
.fpregs
= self
.fpregs
369 int_dest
= self
.intregs
.write_port("dest")
370 int_src1
= self
.intregs
.read_port("src1")
371 int_src2
= self
.intregs
.read_port("src2")
373 fp_dest
= self
.fpregs
.write_port("dest")
374 fp_src1
= self
.fpregs
.read_port("src1")
375 fp_src2
= self
.fpregs
.read_port("src2")
377 # Int ALUs and Comp Units
379 cua
= CompUnitALUs(self
.rwid
, 3)
380 cub
= CompUnitBR(self
.rwid
, 2)
381 m
.submodules
.cu
= cu
= CompUnitsBase(self
.rwid
, [cua
, cub
])
382 bgt
= cub
.bgt
# get at the branch computation unit
386 m
.submodules
.intfus
= intfus
= FunctionUnits(self
.n_regs
, n_int_alus
)
388 # Count of number of FUs
389 n_intfus
= n_int_alus
390 n_fp_fus
= 0 # for now
392 # Integer Priority Picker 1: Adder + Subtractor
393 intpick1
= GroupPicker(n_intfus
) # picks between add, sub, mul and shf
394 m
.submodules
.intpick1
= intpick1
397 regdecode
= RegDecode(self
.n_regs
)
398 m
.submodules
.regdecode
= regdecode
399 issueunit
= IssueUnitArray([self
.aluissue
, self
.brissue
])
400 m
.submodules
.issueunit
= issueunit
402 # Shadow Matrix. currently n_intfus shadows, to be used for
403 # write-after-write hazards. NOTE: there is one extra for branches,
404 # so the shadow width is increased by 1
405 m
.submodules
.shadows
= shadows
= ShadowMatrix(n_intfus
, n_intfus
, True)
406 m
.submodules
.bshadow
= bshadow
= ShadowMatrix(n_intfus
, 1, False)
408 # record previous instruction to cast shadow on current instruction
409 prev_shadow
= Signal(n_intfus
)
411 # Branch Speculation recorder. tracks the success/fail state as
412 # each instruction is issued, so that when the branch occurs the
413 # allow/cancel can be issued as appropriate.
414 m
.submodules
.specrec
= bspec
= BranchSpeculationRecord(n_intfus
)
417 # ok start wiring things together...
418 # "now hear de word of de looord... dem bones dem bones dem dryy bones"
419 # https://www.youtube.com/watch?v=pYb8Wm6-QfA
423 # Issue Unit is where it starts. set up some in/outs for this module
425 comb
+= [ regdecode
.dest_i
.eq(self
.int_dest_i
),
426 regdecode
.src1_i
.eq(self
.int_src1_i
),
427 regdecode
.src2_i
.eq(self
.int_src2_i
),
428 regdecode
.enable_i
.eq(self
.reg_enable_i
),
429 self
.issue_o
.eq(issueunit
.issue_o
)
432 # take these to outside (issue needs them)
433 comb
+= cua
.oper_i
.eq(self
.alu_oper_i
)
434 comb
+= cua
.imm_i
.eq(self
.alu_imm_i
)
435 comb
+= cub
.oper_i
.eq(self
.br_oper_i
)
437 # TODO: issueunit.f (FP)
439 # and int function issue / busy arrays, and dest/src1/src2
440 comb
+= intfus
.dest_i
.eq(regdecode
.dest_o
)
441 comb
+= intfus
.src1_i
.eq(regdecode
.src1_o
)
442 comb
+= intfus
.src2_i
.eq(regdecode
.src2_o
)
444 fn_issue_o
= issueunit
.fn_issue_o
446 comb
+= intfus
.fn_issue_i
.eq(fn_issue_o
)
447 comb
+= issueunit
.busy_i
.eq(cu
.busy_o
)
448 comb
+= self
.busy_o
.eq(cu
.busy_o
.bool())
451 # merge shadow matrices outputs
454 # these are explained in ShadowMatrix docstring, and are to be
455 # connected to the FUReg and FUFU Matrices, to get them to reset
456 anydie
= Signal(n_intfus
, reset_less
=True)
457 allshadown
= Signal(n_intfus
, reset_less
=True)
458 shreset
= Signal(n_intfus
, reset_less
=True)
459 comb
+= allshadown
.eq(shadows
.shadown_o
& bshadow
.shadown_o
)
460 comb
+= anydie
.eq(shadows
.go_die_o | bshadow
.go_die_o
)
461 comb
+= shreset
.eq(bspec
.match_g_o | bspec
.match_f_o
)
464 # connect fu-fu matrix
467 # Group Picker... done manually for now.
468 go_rd_o
= intpick1
.go_rd_o
469 go_wr_o
= intpick1
.go_wr_o
470 go_rd_i
= intfus
.go_rd_i
471 go_wr_i
= intfus
.go_wr_i
472 go_die_i
= intfus
.go_die_i
473 # NOTE: connect to the shadowed versions so that they can "die" (reset)
474 comb
+= go_rd_i
[0:n_intfus
].eq(go_rd_o
[0:n_intfus
]) # rd
475 comb
+= go_wr_i
[0:n_intfus
].eq(go_wr_o
[0:n_intfus
]) # wr
476 comb
+= go_die_i
[0:n_intfus
].eq(anydie
[0:n_intfus
]) # die
480 comb
+= intpick1
.rd_rel_i
[0:n_intfus
].eq(cu
.rd_rel_o
[0:n_intfus
])
481 comb
+= intpick1
.req_rel_i
[0:n_intfus
].eq(cu
.req_rel_o
[0:n_intfus
])
482 int_rd_o
= intfus
.readable_o
483 int_wr_o
= intfus
.writable_o
484 comb
+= intpick1
.readable_i
[0:n_intfus
].eq(int_rd_o
[0:n_intfus
])
485 comb
+= intpick1
.writable_i
[0:n_intfus
].eq(int_wr_o
[0:n_intfus
])
491 comb
+= shadows
.issue_i
.eq(fn_issue_o
)
492 #comb += shadows.reset_i[0:n_intfus].eq(bshadow.go_die_o[0:n_intfus])
493 comb
+= shadows
.reset_i
[0:n_intfus
].eq(bshadow
.go_die_o
[0:n_intfus
])
495 # NOTE; this setup is for the instruction order preservation...
497 # connect shadows / go_dies to Computation Units
498 comb
+= cu
.shadown_i
[0:n_intfus
].eq(allshadown
)
499 comb
+= cu
.go_die_i
[0:n_intfus
].eq(anydie
)
501 # ok connect first n_int_fu shadows to busy lines, to create an
502 # instruction-order linked-list-like arrangement, using a bit-matrix
503 # (instead of e.g. a ring buffer).
506 # when written, the shadow can be cancelled (and was good)
507 for i
in range(n_intfus
):
508 comb
+= shadows
.s_good_i
[i
][0:n_intfus
].eq(go_wr_o
[0:n_intfus
])
510 # *previous* instruction shadows *current* instruction, and, obviously,
511 # if the previous is completed (!busy) don't cast the shadow!
512 comb
+= prev_shadow
.eq(~fn_issue_o
& cu
.busy_o
)
513 for i
in range(n_intfus
):
514 comb
+= shadows
.shadow_i
[i
][0:n_intfus
].eq(prev_shadow
)
517 # ... and this is for branch speculation. it uses the extra bit
518 # tacked onto the ShadowMatrix (hence shadow_wid=n_intfus+1)
519 # only needs to set shadow_i, s_fail_i and s_good_i
521 # issue captures shadow_i (if enabled)
522 comb
+= bshadow
.reset_i
[0:n_intfus
].eq(shreset
[0:n_intfus
])
524 bactive
= Signal(reset_less
=True)
525 comb
+= bactive
.eq((bspec
.active_i | br1
.issue_i
) & ~br1
.go_wr_i
)
527 # instruction being issued (fn_issue_o) has a shadow cast by the branch
528 with m
.If(bactive
& (self
.branch_succ_i | self
.branch_fail_i
)):
529 comb
+= bshadow
.issue_i
.eq(fn_issue_o
)
530 for i
in range(n_intfus
):
531 with m
.If(fn_issue_o
& (Const(1<<i
))):
532 comb
+= bshadow
.shadow_i
[i
][0].eq(1)
534 # finally, we need an indicator to the test infrastructure as to
535 # whether the branch succeeded or failed, plus, link up to the
536 # "recorder" of whether the instruction was under shadow or not
538 with m
.If(br1
.issue_i
):
539 sync
+= bspec
.active_i
.eq(1)
540 with m
.If(self
.branch_succ_i
):
541 comb
+= bspec
.good_i
.eq(fn_issue_o
& 0x1f)
542 with m
.If(self
.branch_fail_i
):
543 comb
+= bspec
.fail_i
.eq(fn_issue_o
& 0x1f)
545 # branch is active (TODO: a better signal: this is over-using the
546 # go_write signal - actually the branch should not be "writing")
547 with m
.If(br1
.go_wr_i
):
548 sync
+= self
.branch_direction_o
.eq(br1
.data_o
+Const(1, 2))
549 sync
+= bspec
.active_i
.eq(0)
550 comb
+= bspec
.br_i
.eq(1)
551 # branch occurs if data == 1, failed if data == 0
552 comb
+= bspec
.br_ok_i
.eq(br1
.data_o
== 1)
553 for i
in range(n_intfus
):
554 # *expected* direction of the branch matched against *actual*
555 comb
+= bshadow
.s_good_i
[i
][0].eq(bspec
.match_g_o
[i
])
557 comb
+= bshadow
.s_fail_i
[i
][0].eq(bspec
.match_f_o
[i
])
560 # Connect Register File(s)
562 comb
+= int_dest
.wen
.eq(intfus
.dest_rsel_o
)
563 comb
+= int_src1
.ren
.eq(intfus
.src1_rsel_o
)
564 comb
+= int_src2
.ren
.eq(intfus
.src2_rsel_o
)
566 # connect ALUs to regfule
567 comb
+= int_dest
.data_i
.eq(cu
.data_o
)
568 comb
+= cu
.src1_i
.eq(int_src1
.data_o
)
569 comb
+= cu
.src2_i
.eq(int_src2
.data_o
)
571 # connect ALU Computation Units
572 comb
+= cu
.go_rd_i
[0:n_intfus
].eq(go_rd_o
[0:n_intfus
])
573 comb
+= cu
.go_wr_i
[0:n_intfus
].eq(go_wr_o
[0:n_intfus
])
574 comb
+= cu
.issue_i
[0:n_intfus
].eq(fn_issue_o
[0:n_intfus
])
579 yield from self
.intregs
580 yield from self
.fpregs
581 yield self
.int_dest_i
582 yield self
.int_src1_i
583 yield self
.int_src2_i
585 yield self
.branch_succ_i
586 yield self
.branch_fail_i
587 yield self
.branch_direction_o
593 class IssueToScoreboard(Elaboratable
):
595 def __init__(self
, qlen
, n_in
, n_out
, rwid
, opwid
, n_regs
):
603 mqbits
= (int(log(qlen
) / log(2))+2, False)
604 self
.p_add_i
= Signal(mqbits
) # instructions to add (from data_i)
605 self
.p_ready_o
= Signal() # instructions were added
606 self
.data_i
= Instruction
.nq(n_in
, "data_i", rwid
, opwid
)
608 self
.busy_o
= Signal(reset_less
=True) # at least one CU is busy
609 self
.qlen_o
= Signal(mqbits
, reset_less
=True)
611 def elaborate(self
, platform
):
616 iq
= InstructionQ(self
.rwid
, self
.opw
, self
.qlen
, self
.n_in
, self
.n_out
)
617 sc
= Scoreboard(self
.rwid
, self
.n_regs
)
621 # get at the regfile for testing
622 self
.intregs
= sc
.intregs
624 # and the "busy" signal and instruction queue length
625 comb
+= self
.busy_o
.eq(sc
.busy_o
)
626 comb
+= self
.qlen_o
.eq(iq
.qlen_o
)
628 # link up instruction queue
629 comb
+= iq
.p_add_i
.eq(self
.p_add_i
)
630 comb
+= self
.p_ready_o
.eq(iq
.p_ready_o
)
631 for i
in range(self
.n_in
):
632 comb
+= eq(iq
.data_i
[i
], self
.data_i
[i
])
634 # take instruction and process it. note that it's possible to
635 # "inspect" the queue contents *without* actually removing the
636 # items. items are only removed when the
639 wait_issue_br
= Signal()
640 wait_issue_alu
= Signal()
642 with m
.If(wait_issue_br | wait_issue_alu
):
643 # set instruction pop length to 1 if the unit accepted
644 with m
.If(wait_issue_br
& (sc
.brissue
.fn_issue_o
!= 0)):
645 with m
.If(iq
.qlen_o
!= 0):
646 comb
+= iq
.n_sub_i
.eq(1)
647 with m
.If(wait_issue_alu
& (sc
.aluissue
.fn_issue_o
!= 0)):
648 with m
.If(iq
.qlen_o
!= 0):
649 comb
+= iq
.n_sub_i
.eq(1)
651 # see if some instruction(s) are here. note that this is
652 # "inspecting" the in-place queue. note also that on the
653 # cycle following "waiting" for fn_issue_o to be set, the
654 # "resetting" done above (insn_i=0) could be re-ASSERTed.
655 with m
.If(iq
.qlen_o
!= 0):
656 # get the operands and operation
657 imm
= iq
.data_o
[0].imm_i
658 dest
= iq
.data_o
[0].dest_i
659 src1
= iq
.data_o
[0].src1_i
660 src2
= iq
.data_o
[0].src2_i
661 op
= iq
.data_o
[0].oper_i
662 opi
= iq
.data_o
[0].opim_i
# immediate set
664 # set the src/dest regs
665 comb
+= sc
.int_dest_i
.eq(dest
)
666 comb
+= sc
.int_src1_i
.eq(src1
)
667 comb
+= sc
.int_src2_i
.eq(src2
)
668 comb
+= sc
.reg_enable_i
.eq(1) # enable the regfile
670 # choose a Function-Unit-Group
671 with m
.If((op
& (0x3<<2)) != 0): # branch
672 comb
+= sc
.brissue
.insn_i
.eq(1)
673 comb
+= sc
.br_oper_i
.eq(op
& 0x3)
674 comb
+= wait_issue_br
.eq(1)
676 comb
+= sc
.aluissue
.insn_i
.eq(1)
677 comb
+= sc
.alu_oper_i
.eq(Cat(op
[0:2], opi
))
678 comb
+= sc
.alu_imm_i
.eq(imm
)
679 comb
+= wait_issue_alu
.eq(1)
682 # these indicate that the instruction is to be made
683 # shadow-dependent on
684 # (either) branch success or branch fail
685 #yield sc.branch_fail_i.eq(branch_fail)
686 #yield sc.branch_succ_i.eq(branch_success)
692 for o
in self
.data_i
:
710 def __init__(self
, rwidth
, nregs
):
712 self
.regs
= [0] * nregs
714 def op(self
, op
, op_imm
, imm
, src1
, src2
, dest
):
715 maxbits
= (1 << self
.rwidth
) - 1
716 src1
= self
.regs
[src1
] & maxbits
720 src2
= self
.regs
[src2
] & maxbits
728 val
= src1
>> (src2
& maxbits
)
730 val
= int(src1
> src2
)
732 val
= int(src1
< src2
)
734 val
= int(src1
== src2
)
736 val
= int(src1
!= src2
)
738 self
.setval(dest
, val
)
741 def setval(self
, dest
, val
):
742 print ("sim setval", dest
, hex(val
))
743 self
.regs
[dest
] = val
746 for i
, val
in enumerate(self
.regs
):
747 reg
= yield dut
.intregs
.regs
[i
].reg
748 okstr
= "OK" if reg
== val
else "!ok"
749 print("reg %d expected %x received %x %s" % (i
, val
, reg
, okstr
))
751 def check(self
, dut
):
752 for i
, val
in enumerate(self
.regs
):
753 reg
= yield dut
.intregs
.regs
[i
].reg
755 print("reg %d expected %x received %x\n" % (i
, val
, reg
))
756 yield from self
.dump(dut
)
759 def instr_q(dut
, op
, op_imm
, imm
, src1
, src2
, dest
,
760 branch_success
, branch_fail
):
761 instrs
= [{'oper_i': op
, 'dest_i': dest
, 'imm_i': imm
, 'opim_i': op_imm
,
762 'src1_i': src1
, 'src2_i': src2
}]
765 for idx
in range(sendlen
):
766 yield from eq(dut
.data_i
[idx
], instrs
[idx
])
767 di
= yield dut
.data_i
[idx
]
768 print ("senddata %d %x" % (idx
, di
))
769 yield dut
.p_add_i
.eq(sendlen
)
771 o_p_ready
= yield dut
.p_ready_o
774 o_p_ready
= yield dut
.p_ready_o
776 yield dut
.p_add_i
.eq(0)
779 def int_instr(dut
, op
, imm
, src1
, src2
, dest
, branch_success
, branch_fail
):
780 yield from disable_issue(dut
)
781 yield dut
.int_dest_i
.eq(dest
)
782 yield dut
.int_src1_i
.eq(src1
)
783 yield dut
.int_src2_i
.eq(src2
)
784 if (op
& (0x3<<2)) != 0: # branch
785 yield dut
.brissue
.insn_i
.eq(1)
786 yield dut
.br_oper_i
.eq(Const(op
& 0x3, 2))
787 dut_issue
= dut
.brissue
789 yield dut
.aluissue
.insn_i
.eq(1)
790 yield dut
.alu_oper_i
.eq(Const(op
& 0x3, 2))
791 yield dut
.alu_imm_i
.eq(imm
)
792 dut_issue
= dut
.aluissue
793 yield dut
.reg_enable_i
.eq(1)
795 # these indicate that the instruction is to be made shadow-dependent on
796 # (either) branch success or branch fail
797 yield dut
.branch_fail_i
.eq(branch_fail
)
798 yield dut
.branch_succ_i
.eq(branch_success
)
801 yield from wait_for_issue(dut
, dut_issue
)
804 def print_reg(dut
, rnums
):
807 reg
= yield dut
.intregs
.regs
[rnum
].reg
808 rs
.append("%x" % reg
)
809 rnums
= map(str, rnums
)
810 print ("reg %s: %s" % (','.join(rnums
), ','.join(rs
)))
813 def create_random_ops(dut
, n_ops
, shadowing
=False, max_opnums
=3):
815 for i
in range(n_ops
):
816 src1
= randint(1, dut
.n_regs
-1)
817 src2
= randint(1, dut
.n_regs
-1)
818 imm
= randint(1, (1<<dut
.rwid
)-1)
819 dest
= randint(1, dut
.n_regs
-1)
820 op
= randint(0, max_opnums
)
821 opi
= 0 if randint(0, 2) else 1 # set true if random is nonzero
824 insts
.append((src1
, src2
, dest
, op
, opi
, imm
, (0, 0)))
826 insts
.append((src1
, src2
, dest
, op
, opi
, imm
))
830 def wait_for_busy_clear(dut
):
832 busy_o
= yield dut
.busy_o
838 def disable_issue(dut
):
839 yield dut
.aluissue
.insn_i
.eq(0)
840 yield dut
.brissue
.insn_i
.eq(0)
843 def wait_for_issue(dut
, dut_issue
):
845 issue_o
= yield dut_issue
.fn_issue_o
847 yield from disable_issue(dut
)
848 yield dut
.reg_enable_i
.eq(0)
851 #yield from print_reg(dut, [1,2,3])
853 #yield from print_reg(dut, [1,2,3])
855 def scoreboard_branch_sim(dut
, alusim
):
861 print ("rseed", iseed
)
865 yield dut
.branch_direction_o
.eq(0)
867 # set random values in the registers
868 for i
in range(1, dut
.n_regs
):
870 val
= randint(0, (1<<alusim
.rwidth
)-1)
871 yield dut
.intregs
.regs
[i
].reg
.eq(val
)
872 alusim
.setval(i
, val
)
875 # create some instructions: branches create a tree
876 insts
= create_random_ops(dut
, 1, True, 1)
877 #insts.append((6, 6, 1, 2, (0, 0)))
878 #insts.append((4, 3, 3, 0, (0, 0)))
880 src1
= randint(1, dut
.n_regs
-1)
881 src2
= randint(1, dut
.n_regs
-1)
883 op
= 4 # only BGT at the moment
885 branch_ok
= create_random_ops(dut
, 1, True, 1)
886 branch_fail
= create_random_ops(dut
, 1, True, 1)
888 insts
.append((src1
, src2
, (branch_ok
, branch_fail
), op
, (0, 0)))
892 insts
.append( (3, 5, 2, 0, (0, 0)) )
895 #branch_ok.append ( (5, 7, 5, 1, (1, 0)) )
896 branch_ok
.append( None )
897 branch_fail
.append( (1, 1, 2, 0, (0, 1)) )
898 #branch_fail.append( None )
899 insts
.append( (6, 4, (branch_ok
, branch_fail
), 4, (0, 0)) )
901 siminsts
= deepcopy(insts
)
903 # issue instruction(s)
911 branch_direction
= yield dut
.branch_direction_o
# way branch went
912 (src1
, src2
, dest
, op
, (shadow_on
, shadow_off
)) = insts
.pop(0)
913 if branch_direction
== 1 and shadow_on
:
914 print ("skip", i
, src1
, src2
, dest
, op
, shadow_on
, shadow_off
)
915 continue # branch was "success" and this is a "failed"... skip
916 if branch_direction
== 2 and shadow_off
:
917 print ("skip", i
, src1
, src2
, dest
, op
, shadow_on
, shadow_off
)
918 continue # branch was "fail" and this is a "success"... skip
919 if branch_direction
!= 0:
924 branch_ok
, branch_fail
= dest
926 # ok zip up the branch success / fail instructions and
927 # drop them into the queue, one marked "to have branch success"
928 # the other to be marked shadow branch "fail".
929 # one out of each of these will be cancelled
930 for ok
, fl
in zip(branch_ok
, branch_fail
):
932 instrs
.append((ok
[0], ok
[1], ok
[2], ok
[3], (1, 0)))
934 instrs
.append((fl
[0], fl
[1], fl
[2], fl
[3], (0, 1)))
935 print ("instr %d: (%d, %d, %d, %d, (%d, %d))" % \
936 (i
, src1
, src2
, dest
, op
, shadow_on
, shadow_off
))
937 yield from int_instr(dut
, op
, src1
, src2
, dest
,
938 shadow_on
, shadow_off
)
940 # wait for all instructions to stop before checking
942 yield from wait_for_busy_clear(dut
)
946 instr
= siminsts
.pop(0)
949 (src1
, src2
, dest
, op
, (shadow_on
, shadow_off
)) = instr
953 branch_ok
, branch_fail
= dest
955 print ("sim %d: (%d, %d, %d, %d, (%d, %d))" % \
956 (i
, src1
, src2
, dest
, op
, shadow_on
, shadow_off
))
957 branch_res
= alusim
.op(op
, src1
, src2
, dest
)
960 siminsts
+= branch_ok
962 siminsts
+= branch_fail
965 yield from alusim
.check(dut
)
966 yield from alusim
.dump(dut
)
969 def scoreboard_sim(dut
, alusim
):
975 # set random values in the registers
976 for i
in range(1, dut
.n_regs
):
977 val
= randint(0, (1<<alusim
.rwidth
)-1)
980 yield dut
.intregs
.regs
[i
].reg
.eq(val
)
981 alusim
.setval(i
, val
)
983 # create some instructions (some random, some regression tests)
986 instrs
= create_random_ops(dut
, 15, True, 4)
989 instrs
.append( (1, 2, 2, 1, 1, 20, (0, 0)) )
992 instrs
.append( (7, 3, 2, 4, (0, 0)) )
993 instrs
.append( (7, 6, 6, 2, (0, 0)) )
994 instrs
.append( (1, 7, 2, 2, (0, 0)) )
997 instrs
.append((2, 3, 3, 0, 0, 0, (0, 0)))
998 instrs
.append((5, 3, 3, 1, 0, 0, (0, 0)))
999 instrs
.append((3, 5, 5, 2, 0, 0, (0, 0)))
1000 instrs
.append((5, 3, 3, 3, 0, 0, (0, 0)))
1001 instrs
.append((3, 5, 5, 0, 0, 0, (0, 0)))
1004 instrs
.append( (3, 3, 4, 0, 0, 13979, (0, 0)))
1005 instrs
.append( (6, 4, 1, 2, 0, 40976, (0, 0)))
1006 instrs
.append( (1, 4, 7, 4, 1, 23652, (0, 0)))
1009 instrs
.append((5, 6, 2, 1))
1010 instrs
.append((2, 2, 4, 0))
1011 #instrs.append((2, 2, 3, 1))
1014 instrs
.append((2, 1, 2, 3))
1017 instrs
.append((2, 6, 2, 1))
1018 instrs
.append((2, 1, 2, 0))
1021 instrs
.append((1, 2, 7, 2))
1022 instrs
.append((7, 1, 5, 0))
1023 instrs
.append((4, 4, 1, 1))
1026 instrs
.append((5, 6, 2, 2))
1027 instrs
.append((1, 1, 4, 1))
1028 instrs
.append((6, 5, 3, 0))
1031 # Write-after-Write Hazard
1032 instrs
.append( (3, 6, 7, 2) )
1033 instrs
.append( (4, 4, 7, 1) )
1036 # self-read/write-after-write followed by Read-after-Write
1037 instrs
.append((1, 1, 1, 1))
1038 instrs
.append((1, 5, 3, 0))
1041 # Read-after-Write followed by self-read-after-write
1042 instrs
.append((5, 6, 1, 2))
1043 instrs
.append((1, 1, 1, 1))
1046 # self-read-write sandwich
1047 instrs
.append((5, 6, 1, 2))
1048 instrs
.append((1, 1, 1, 1))
1049 instrs
.append((1, 5, 3, 0))
1052 # very weird failure
1053 instrs
.append( (5, 2, 5, 2) )
1054 instrs
.append( (2, 6, 3, 0) )
1055 instrs
.append( (4, 2, 2, 1) )
1059 yield dut
.intregs
.regs
[5].reg
.eq(v1
)
1060 alusim
.setval(5, v1
)
1061 yield dut
.intregs
.regs
[3].reg
.eq(5)
1063 instrs
.append((5, 3, 3, 4, (0, 0)))
1064 instrs
.append((4, 2, 1, 2, (0, 1)))
1068 yield dut
.intregs
.regs
[5].reg
.eq(v1
)
1069 alusim
.setval(5, v1
)
1070 yield dut
.intregs
.regs
[3].reg
.eq(5)
1072 instrs
.append((5, 3, 3, 4, (0, 0)))
1073 instrs
.append((4, 2, 1, 2, (1, 0)))
1076 instrs
.append( (4, 3, 5, 1, 0, (0, 0)) )
1077 instrs
.append( (5, 2, 3, 1, 0, (0, 0)) )
1078 instrs
.append( (7, 1, 5, 2, 0, (0, 0)) )
1079 instrs
.append( (5, 6, 6, 4, 0, (0, 0)) )
1080 instrs
.append( (7, 5, 2, 2, 0, (1, 0)) )
1081 instrs
.append( (1, 7, 5, 0, 0, (0, 1)) )
1082 instrs
.append( (1, 6, 1, 2, 0, (1, 0)) )
1083 instrs
.append( (1, 6, 7, 3, 0, (0, 0)) )
1084 instrs
.append( (6, 7, 7, 0, 0, (0, 0)) )
1086 # issue instruction(s), wait for issue to be free before proceeding
1087 for i
, instr
in enumerate(instrs
):
1088 src1
, src2
, dest
, op
, opi
, imm
, (br_ok
, br_fail
) = instr
1090 print ("instr %d: (%d, %d, %d, %d, %d, %d)" % \
1091 (i
, src1
, src2
, dest
, op
, opi
, imm
))
1092 alusim
.op(op
, opi
, imm
, src1
, src2
, dest
)
1093 yield from instr_q(dut
, op
, opi
, imm
, src1
, src2
, dest
,
1096 # wait for all instructions to stop before checking
1098 iqlen
= yield dut
.qlen_o
1106 yield from wait_for_busy_clear(dut
)
1109 yield from alusim
.check(dut
)
1110 yield from alusim
.dump(dut
)
1113 def test_scoreboard():
1114 dut
= IssueToScoreboard(2, 1, 1, 16, 8, 8)
1115 alusim
= RegSim(16, 8)
1116 memsim
= MemSim(16, 16)
1117 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
1118 with
open("test_scoreboard6600.il", "w") as f
:
1121 run_simulation(dut
, scoreboard_sim(dut
, alusim
),
1122 vcd_name
='test_scoreboard6600.vcd')
1124 #run_simulation(dut, scoreboard_branch_sim(dut, alusim),
1125 # vcd_name='test_scoreboard6600.vcd')
1128 if __name__
== '__main__':