2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
28 #include "util/debug.h"
29 #include "util/u_math.h"
32 #include "ir3_compiler.h"
33 #include "ir3_shader.h"
35 static void ir3_setup_const_state(struct ir3_shader
*shader
, nir_shader
*nir
);
37 static const nir_shader_compiler_options options
= {
47 .lower_uadd_carry
= true,
48 .lower_mul_high
= true,
50 .vertex_id_zero_based
= true,
51 .lower_extract_byte
= true,
52 .lower_extract_word
= true,
53 .lower_all_io_to_elements
= true,
54 .lower_helper_invocation
= true,
55 .lower_bitfield_insert_to_shifts
= true,
56 .lower_bitfield_extract_to_shifts
= true,
57 .use_interpolated_input_intrinsics
= true,
61 /* we don't want to lower vertex_id to _zero_based on newer gpus: */
62 static const nir_shader_compiler_options options_a6xx
= {
72 .lower_uadd_carry
= true,
73 .lower_mul_high
= true,
75 .vertex_id_zero_based
= false,
76 .lower_extract_byte
= true,
77 .lower_extract_word
= true,
78 .lower_all_io_to_elements
= true,
79 .lower_helper_invocation
= true,
80 .lower_bitfield_insert_to_shifts
= true,
81 .lower_bitfield_extract_to_shifts
= true,
82 .use_interpolated_input_intrinsics
= true,
87 const nir_shader_compiler_options
*
88 ir3_get_compiler_options(struct ir3_compiler
*compiler
)
90 if (compiler
->gpu_id
>= 600)
95 /* for given shader key, are any steps handled in nir? */
97 ir3_key_lowers_nir(const struct ir3_shader_key
*key
)
99 return key
->fsaturate_s
| key
->fsaturate_t
| key
->fsaturate_r
|
100 key
->vsaturate_s
| key
->vsaturate_t
| key
->vsaturate_r
|
101 key
->ucp_enables
| key
->color_two_side
|
102 key
->fclamp_color
| key
->vclamp_color
;
105 #define OPT(nir, pass, ...) ({ \
106 bool this_progress = false; \
107 NIR_PASS(this_progress, nir, pass, ##__VA_ARGS__); \
111 #define OPT_V(nir, pass, ...) NIR_PASS_V(nir, pass, ##__VA_ARGS__)
114 ir3_optimize_loop(nir_shader
*s
)
117 unsigned lower_flrp
=
118 (s
->options
->lower_flrp16
? 16 : 0) |
119 (s
->options
->lower_flrp32
? 32 : 0) |
120 (s
->options
->lower_flrp64
? 64 : 0);
125 OPT_V(s
, nir_lower_vars_to_ssa
);
126 progress
|= OPT(s
, nir_opt_copy_prop_vars
);
127 progress
|= OPT(s
, nir_opt_dead_write_vars
);
128 progress
|= OPT(s
, nir_lower_alu_to_scalar
, NULL
, NULL
);
129 progress
|= OPT(s
, nir_lower_phis_to_scalar
);
131 progress
|= OPT(s
, nir_copy_prop
);
132 progress
|= OPT(s
, nir_opt_dce
);
133 progress
|= OPT(s
, nir_opt_cse
);
136 gcm
= env_var_as_unsigned("GCM", 0);
138 progress
|= OPT(s
, nir_opt_gcm
, true);
140 progress
|= OPT(s
, nir_opt_gcm
, false);
141 progress
|= OPT(s
, nir_opt_peephole_select
, 16, true, true);
142 progress
|= OPT(s
, nir_opt_intrinsics
);
143 progress
|= OPT(s
, nir_opt_algebraic
);
144 progress
|= OPT(s
, nir_opt_constant_folding
);
146 if (lower_flrp
!= 0) {
147 if (OPT(s
, nir_lower_flrp
,
149 false /* always_precise */,
150 s
->options
->lower_ffma
)) {
151 OPT(s
, nir_opt_constant_folding
);
155 /* Nothing should rematerialize any flrps, so we only
156 * need to do this lowering once.
161 progress
|= OPT(s
, nir_opt_dead_cf
);
162 if (OPT(s
, nir_opt_trivial_continues
)) {
164 /* If nir_opt_trivial_continues makes progress, then we need to clean
165 * things up if we want any hope of nir_opt_if or nir_opt_loop_unroll
168 OPT(s
, nir_copy_prop
);
171 progress
|= OPT(s
, nir_opt_if
, false);
172 progress
|= OPT(s
, nir_opt_remove_phis
);
173 progress
|= OPT(s
, nir_opt_undef
);
179 ir3_optimize_nir(struct ir3_shader
*shader
, nir_shader
*s
,
180 const struct ir3_shader_key
*key
)
182 struct nir_lower_tex_options tex_options
= {
184 .lower_tg4_offsets
= true,
188 switch (shader
->type
) {
189 case MESA_SHADER_FRAGMENT
:
190 tex_options
.saturate_s
= key
->fsaturate_s
;
191 tex_options
.saturate_t
= key
->fsaturate_t
;
192 tex_options
.saturate_r
= key
->fsaturate_r
;
194 case MESA_SHADER_VERTEX
:
195 tex_options
.saturate_s
= key
->vsaturate_s
;
196 tex_options
.saturate_t
= key
->vsaturate_t
;
197 tex_options
.saturate_r
= key
->vsaturate_r
;
205 if (shader
->compiler
->gpu_id
>= 400) {
206 /* a4xx seems to have *no* sam.p */
207 tex_options
.lower_txp
= ~0; /* lower all txp */
209 /* a3xx just needs to avoid sam.p for 3d tex */
210 tex_options
.lower_txp
= (1 << GLSL_SAMPLER_DIM_3D
);
213 if (ir3_shader_debug
& IR3_DBG_DISASM
) {
214 debug_printf("----------------------\n");
215 nir_print_shader(s
, stdout
);
216 debug_printf("----------------------\n");
219 OPT_V(s
, nir_lower_regs_to_ssa
);
220 OPT_V(s
, ir3_nir_lower_io_offsets
);
223 if (s
->info
.stage
== MESA_SHADER_VERTEX
) {
224 OPT_V(s
, nir_lower_clip_vs
, key
->ucp_enables
, false);
225 if (key
->vclamp_color
)
226 OPT_V(s
, nir_lower_clamp_color_outputs
);
227 } else if (s
->info
.stage
== MESA_SHADER_FRAGMENT
) {
228 OPT_V(s
, nir_lower_clip_fs
, key
->ucp_enables
);
229 if (key
->fclamp_color
)
230 OPT_V(s
, nir_lower_clamp_color_outputs
);
232 if (key
->color_two_side
) {
233 OPT_V(s
, nir_lower_two_sided_color
);
236 /* only want to do this the first time (when key is null)
237 * and not again on any potential 2nd variant lowering pass:
239 OPT_V(s
, ir3_nir_apply_trig_workarounds
);
241 /* This wouldn't hurt to run multiple times, but there is
244 if (shader
->type
== MESA_SHADER_FRAGMENT
)
245 OPT_V(s
, nir_lower_fb_read
);
248 OPT_V(s
, nir_lower_tex
, &tex_options
);
249 OPT_V(s
, nir_lower_load_const_to_scalar
);
250 if (shader
->compiler
->gpu_id
< 500)
251 OPT_V(s
, ir3_nir_lower_tg4_to_tex
);
253 ir3_optimize_loop(s
);
255 /* do ubo load and idiv lowering after first opt loop to get a chance to
256 * propagate constants for divide by immed power-of-two and constant ubo
259 * NOTE that UBO analysis pass should only be done once, before variants
261 const bool ubo_progress
= !key
&& OPT(s
, ir3_nir_analyze_ubo_ranges
, shader
);
262 const bool idiv_progress
= OPT(s
, nir_lower_idiv
);
263 if (ubo_progress
|| idiv_progress
)
264 ir3_optimize_loop(s
);
266 OPT_V(s
, nir_remove_dead_variables
, nir_var_function_temp
);
268 OPT_V(s
, nir_opt_sink
, nir_move_const_undef
);
270 if (ir3_shader_debug
& IR3_DBG_DISASM
) {
271 debug_printf("----------------------\n");
272 nir_print_shader(s
, stdout
);
273 debug_printf("----------------------\n");
278 /* The first time thru, when not creating variant, do the one-time
279 * const_state layout setup. This should be done after ubo range
283 ir3_setup_const_state(shader
, s
);
288 ir3_nir_scan_driver_consts(nir_shader
*shader
,
289 struct ir3_const_state
*layout
)
291 nir_foreach_function(function
, shader
) {
295 nir_foreach_block(block
, function
->impl
) {
296 nir_foreach_instr(instr
, block
) {
297 if (instr
->type
!= nir_instr_type_intrinsic
)
300 nir_intrinsic_instr
*intr
=
301 nir_instr_as_intrinsic(instr
);
304 switch (intr
->intrinsic
) {
305 case nir_intrinsic_get_buffer_size
:
306 idx
= nir_src_as_uint(intr
->src
[0]);
307 if (layout
->ssbo_size
.mask
& (1 << idx
))
309 layout
->ssbo_size
.mask
|= (1 << idx
);
310 layout
->ssbo_size
.off
[idx
] =
311 layout
->ssbo_size
.count
;
312 layout
->ssbo_size
.count
+= 1; /* one const per */
314 case nir_intrinsic_image_deref_atomic_add
:
315 case nir_intrinsic_image_deref_atomic_imin
:
316 case nir_intrinsic_image_deref_atomic_umin
:
317 case nir_intrinsic_image_deref_atomic_imax
:
318 case nir_intrinsic_image_deref_atomic_umax
:
319 case nir_intrinsic_image_deref_atomic_and
:
320 case nir_intrinsic_image_deref_atomic_or
:
321 case nir_intrinsic_image_deref_atomic_xor
:
322 case nir_intrinsic_image_deref_atomic_exchange
:
323 case nir_intrinsic_image_deref_atomic_comp_swap
:
324 case nir_intrinsic_image_deref_store
:
325 case nir_intrinsic_image_deref_size
:
326 idx
= nir_intrinsic_get_var(intr
, 0)->data
.driver_location
;
327 if (layout
->image_dims
.mask
& (1 << idx
))
329 layout
->image_dims
.mask
|= (1 << idx
);
330 layout
->image_dims
.off
[idx
] =
331 layout
->image_dims
.count
;
332 layout
->image_dims
.count
+= 3; /* three const per */
334 case nir_intrinsic_load_ubo
:
335 if (nir_src_is_const(intr
->src
[0])) {
336 layout
->num_ubos
= MAX2(layout
->num_ubos
,
337 nir_src_as_uint(intr
->src
[0]) + 1);
339 layout
->num_ubos
= shader
->info
.num_ubos
;
342 case nir_intrinsic_load_base_vertex
:
343 case nir_intrinsic_load_first_vertex
:
344 layout
->num_driver_params
=
345 MAX2(layout
->num_driver_params
, IR3_DP_VTXID_BASE
+ 1);
347 case nir_intrinsic_load_user_clip_plane
:
348 layout
->num_driver_params
=
349 MAX2(layout
->num_driver_params
, IR3_DP_UCP7_W
+ 1);
351 case nir_intrinsic_load_num_work_groups
:
352 layout
->num_driver_params
=
353 MAX2(layout
->num_driver_params
, IR3_DP_NUM_WORK_GROUPS_Z
+ 1);
355 case nir_intrinsic_load_local_group_size
:
356 layout
->num_driver_params
=
357 MAX2(layout
->num_driver_params
, IR3_DP_LOCAL_GROUP_SIZE_Z
+ 1);
368 ir3_setup_const_state(struct ir3_shader
*shader
, nir_shader
*nir
)
370 struct ir3_compiler
*compiler
= shader
->compiler
;
371 struct ir3_const_state
*const_state
= &shader
->const_state
;
373 memset(&const_state
->offsets
, ~0, sizeof(const_state
->offsets
));
375 ir3_nir_scan_driver_consts(nir
, const_state
);
377 if ((compiler
->gpu_id
< 500) &&
378 (shader
->stream_output
.num_outputs
> 0)) {
379 const_state
->num_driver_params
=
380 MAX2(const_state
->num_driver_params
, IR3_DP_VTXCNT_MAX
+ 1);
383 /* num_driver_params is scalar, align to vec4: */
384 const_state
->num_driver_params
= align(const_state
->num_driver_params
, 4);
386 debug_assert((shader
->ubo_state
.size
% 16) == 0);
387 unsigned constoff
= align(shader
->ubo_state
.size
/ 16, 8);
388 unsigned ptrsz
= ir3_pointer_size(compiler
);
390 if (const_state
->num_ubos
> 0) {
391 const_state
->offsets
.ubo
= constoff
;
392 constoff
+= align(nir
->info
.num_ubos
* ptrsz
, 4) / 4;
395 if (const_state
->ssbo_size
.count
> 0) {
396 unsigned cnt
= const_state
->ssbo_size
.count
;
397 const_state
->offsets
.ssbo_sizes
= constoff
;
398 constoff
+= align(cnt
, 4) / 4;
401 if (const_state
->image_dims
.count
> 0) {
402 unsigned cnt
= const_state
->image_dims
.count
;
403 const_state
->offsets
.image_dims
= constoff
;
404 constoff
+= align(cnt
, 4) / 4;
407 if (const_state
->num_driver_params
> 0)
408 const_state
->offsets
.driver_param
= constoff
;
409 constoff
+= const_state
->num_driver_params
/ 4;
411 if ((shader
->type
== MESA_SHADER_VERTEX
) &&
412 (compiler
->gpu_id
< 500) &&
413 shader
->stream_output
.num_outputs
> 0) {
414 const_state
->offsets
.tfbo
= constoff
;
415 constoff
+= align(IR3_MAX_SO_BUFFERS
* ptrsz
, 4) / 4;
418 const_state
->offsets
.immediate
= constoff
;