2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
28 #include "util/debug.h"
29 #include "util/u_math.h"
32 #include "ir3_compiler.h"
33 #include "ir3_shader.h"
35 static const nir_shader_compiler_options options
= {
46 .lower_uadd_carry
= true,
47 .lower_usub_borrow
= true,
48 .lower_mul_high
= true,
49 .lower_mul_2x32_64
= true,
51 .vertex_id_zero_based
= true,
52 .lower_extract_byte
= true,
53 .lower_extract_word
= true,
54 .lower_all_io_to_elements
= true,
55 .lower_helper_invocation
= true,
56 .lower_bitfield_insert_to_shifts
= true,
57 .lower_bitfield_extract_to_shifts
= true,
58 .lower_pack_half_2x16
= true,
59 .lower_pack_snorm_4x8
= true,
60 .lower_pack_snorm_2x16
= true,
61 .lower_pack_unorm_4x8
= true,
62 .lower_pack_unorm_2x16
= true,
63 .lower_unpack_half_2x16
= true,
64 .lower_unpack_snorm_4x8
= true,
65 .lower_unpack_snorm_2x16
= true,
66 .lower_unpack_unorm_4x8
= true,
67 .lower_unpack_unorm_2x16
= true,
68 .lower_pack_split
= true,
69 .use_interpolated_input_intrinsics
= true,
71 .lower_to_scalar
= true,
75 /* we don't want to lower vertex_id to _zero_based on newer gpus: */
76 static const nir_shader_compiler_options options_a6xx
= {
87 .lower_uadd_carry
= true,
88 .lower_usub_borrow
= true,
89 .lower_mul_high
= true,
90 .lower_mul_2x32_64
= true,
92 .vertex_id_zero_based
= false,
93 .lower_extract_byte
= true,
94 .lower_extract_word
= true,
95 .lower_all_io_to_elements
= true,
96 .lower_helper_invocation
= true,
97 .lower_bitfield_insert_to_shifts
= true,
98 .lower_bitfield_extract_to_shifts
= true,
99 .lower_pack_half_2x16
= true,
100 .lower_pack_snorm_4x8
= true,
101 .lower_pack_snorm_2x16
= true,
102 .lower_pack_unorm_4x8
= true,
103 .lower_pack_unorm_2x16
= true,
104 .lower_unpack_half_2x16
= true,
105 .lower_unpack_snorm_4x8
= true,
106 .lower_unpack_snorm_2x16
= true,
107 .lower_unpack_unorm_4x8
= true,
108 .lower_unpack_unorm_2x16
= true,
109 .lower_pack_split
= true,
110 .use_interpolated_input_intrinsics
= true,
111 .lower_rotate
= true,
112 .vectorize_io
= true,
113 .lower_to_scalar
= true,
115 .max_unroll_iterations
= 32,
118 const nir_shader_compiler_options
*
119 ir3_get_compiler_options(struct ir3_compiler
*compiler
)
121 if (compiler
->gpu_id
>= 600)
122 return &options_a6xx
;
126 #define OPT(nir, pass, ...) ({ \
127 bool this_progress = false; \
128 NIR_PASS(this_progress, nir, pass, ##__VA_ARGS__); \
132 #define OPT_V(nir, pass, ...) NIR_PASS_V(nir, pass, ##__VA_ARGS__)
135 ir3_optimize_loop(nir_shader
*s
)
138 unsigned lower_flrp
=
139 (s
->options
->lower_flrp16
? 16 : 0) |
140 (s
->options
->lower_flrp32
? 32 : 0) |
141 (s
->options
->lower_flrp64
? 64 : 0);
146 OPT_V(s
, nir_lower_vars_to_ssa
);
147 progress
|= OPT(s
, nir_opt_copy_prop_vars
);
148 progress
|= OPT(s
, nir_opt_dead_write_vars
);
149 progress
|= OPT(s
, nir_lower_alu_to_scalar
, NULL
, NULL
);
150 progress
|= OPT(s
, nir_lower_phis_to_scalar
);
152 progress
|= OPT(s
, nir_copy_prop
);
153 progress
|= OPT(s
, nir_opt_dce
);
154 progress
|= OPT(s
, nir_opt_cse
);
157 gcm
= env_var_as_unsigned("GCM", 0);
159 progress
|= OPT(s
, nir_opt_gcm
, true);
161 progress
|= OPT(s
, nir_opt_gcm
, false);
162 progress
|= OPT(s
, nir_opt_peephole_select
, 16, true, true);
163 progress
|= OPT(s
, nir_opt_intrinsics
);
164 progress
|= OPT(s
, nir_opt_algebraic
);
165 progress
|= OPT(s
, nir_lower_alu
);
166 progress
|= OPT(s
, nir_lower_pack
);
167 progress
|= OPT(s
, nir_opt_constant_folding
);
169 if (lower_flrp
!= 0) {
170 if (OPT(s
, nir_lower_flrp
,
172 false /* always_precise */,
173 s
->options
->lower_ffma
)) {
174 OPT(s
, nir_opt_constant_folding
);
178 /* Nothing should rematerialize any flrps, so we only
179 * need to do this lowering once.
184 progress
|= OPT(s
, nir_opt_dead_cf
);
185 if (OPT(s
, nir_opt_trivial_continues
)) {
187 /* If nir_opt_trivial_continues makes progress, then we need to clean
188 * things up if we want any hope of nir_opt_if or nir_opt_loop_unroll
191 OPT(s
, nir_copy_prop
);
194 progress
|= OPT(s
, nir_opt_if
, false);
195 progress
|= OPT(s
, nir_opt_remove_phis
);
196 progress
|= OPT(s
, nir_opt_undef
);
201 should_split_wrmask(const nir_instr
*instr
, const void *data
)
203 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
205 switch (intr
->intrinsic
) {
206 case nir_intrinsic_store_ssbo
:
207 case nir_intrinsic_store_shared
:
208 case nir_intrinsic_store_global
:
216 ir3_optimize_nir(struct ir3_shader
*shader
, nir_shader
*s
)
218 struct nir_lower_tex_options tex_options
= {
220 .lower_tg4_offsets
= true,
223 if (shader
->compiler
->gpu_id
>= 400) {
224 /* a4xx seems to have *no* sam.p */
225 tex_options
.lower_txp
= ~0; /* lower all txp */
227 /* a3xx just needs to avoid sam.p for 3d tex */
228 tex_options
.lower_txp
= (1 << GLSL_SAMPLER_DIM_3D
);
231 if (ir3_shader_debug
& IR3_DBG_DISASM
) {
232 debug_printf("----------------------\n");
233 nir_print_shader(s
, stdout
);
234 debug_printf("----------------------\n");
237 OPT_V(s
, nir_lower_regs_to_ssa
);
238 OPT_V(s
, nir_lower_wrmasks
, should_split_wrmask
, s
);
240 OPT_V(s
, ir3_nir_apply_trig_workarounds
);
242 if (shader
->type
== MESA_SHADER_FRAGMENT
)
243 OPT_V(s
, nir_lower_fb_read
);
245 OPT_V(s
, nir_lower_tex
, &tex_options
);
246 OPT_V(s
, nir_lower_load_const_to_scalar
);
247 if (shader
->compiler
->gpu_id
< 500)
248 OPT_V(s
, ir3_nir_lower_tg4_to_tex
);
250 ir3_optimize_loop(s
);
252 /* do ubo load and idiv lowering after first opt loop to get a chance to
253 * propagate constants for divide by immed power-of-two and constant ubo
256 * NOTE that UBO analysis pass should only be done once, before variants
258 const bool ubo_progress
= OPT(s
, ir3_nir_analyze_ubo_ranges
, shader
);
259 const bool idiv_progress
= OPT(s
, nir_lower_idiv
, nir_lower_idiv_fast
);
260 /* UBO offset lowering has to come after we've decided what will be left as load_ubo */
261 OPT_V(s
, ir3_nir_lower_io_offsets
, shader
->compiler
->gpu_id
);
263 if (ubo_progress
|| idiv_progress
)
264 ir3_optimize_loop(s
);
266 OPT_V(s
, nir_remove_dead_variables
, nir_var_function_temp
, NULL
);
268 if (ir3_shader_debug
& IR3_DBG_DISASM
) {
269 debug_printf("----------------------\n");
270 nir_print_shader(s
, stdout
);
271 debug_printf("----------------------\n");
276 /* The first time thru, when not creating variant, do the one-time
277 * const_state layout setup. This should be done after ubo range
280 ir3_setup_const_state(shader
, s
, &shader
->const_state
);
284 ir3_nir_lower_variant(struct ir3_shader_variant
*so
, nir_shader
*s
)
286 if (ir3_shader_debug
& IR3_DBG_DISASM
) {
287 debug_printf("----------------------\n");
288 nir_print_shader(s
, stdout
);
289 debug_printf("----------------------\n");
292 bool progress
= false;
294 if (so
->key
.has_gs
|| so
->key
.tessellation
) {
295 switch (so
->shader
->type
) {
296 case MESA_SHADER_VERTEX
:
297 NIR_PASS_V(s
, ir3_nir_lower_to_explicit_output
, so
->shader
, so
->key
.tessellation
);
300 case MESA_SHADER_TESS_CTRL
:
301 NIR_PASS_V(s
, ir3_nir_lower_tess_ctrl
, so
->shader
, so
->key
.tessellation
);
302 NIR_PASS_V(s
, ir3_nir_lower_to_explicit_input
);
305 case MESA_SHADER_TESS_EVAL
:
306 NIR_PASS_V(s
, ir3_nir_lower_tess_eval
, so
->key
.tessellation
);
308 NIR_PASS_V(s
, ir3_nir_lower_to_explicit_output
, so
->shader
, so
->key
.tessellation
);
311 case MESA_SHADER_GEOMETRY
:
312 NIR_PASS_V(s
, ir3_nir_lower_to_explicit_input
);
320 if (s
->info
.stage
== MESA_SHADER_VERTEX
) {
321 if (so
->key
.ucp_enables
)
322 progress
|= OPT(s
, nir_lower_clip_vs
, so
->key
.ucp_enables
, false, false, NULL
);
323 if (so
->key
.vclamp_color
)
324 progress
|= OPT(s
, nir_lower_clamp_color_outputs
);
325 } else if (s
->info
.stage
== MESA_SHADER_FRAGMENT
) {
326 if (so
->key
.ucp_enables
)
327 progress
|= OPT(s
, nir_lower_clip_fs
, so
->key
.ucp_enables
, false);
328 if (so
->key
.fclamp_color
)
329 progress
|= OPT(s
, nir_lower_clamp_color_outputs
);
331 if (so
->key
.color_two_side
) {
332 OPT_V(s
, nir_lower_two_sided_color
);
336 struct nir_lower_tex_options tex_options
= { };
338 switch (so
->shader
->type
) {
339 case MESA_SHADER_FRAGMENT
:
340 tex_options
.saturate_s
= so
->key
.fsaturate_s
;
341 tex_options
.saturate_t
= so
->key
.fsaturate_t
;
342 tex_options
.saturate_r
= so
->key
.fsaturate_r
;
344 case MESA_SHADER_VERTEX
:
345 tex_options
.saturate_s
= so
->key
.vsaturate_s
;
346 tex_options
.saturate_t
= so
->key
.vsaturate_t
;
347 tex_options
.saturate_r
= so
->key
.vsaturate_r
;
354 if (tex_options
.saturate_s
|| tex_options
.saturate_t
||
355 tex_options
.saturate_r
) {
356 progress
|= OPT(s
, nir_lower_tex
, &tex_options
);
360 ir3_optimize_loop(s
);
362 /* Do late algebraic optimization to turn add(a, neg(b)) back into
363 * subs, then the mandatory cleanup after algebraic. Note that it may
364 * produce fnegs, and if so then we need to keep running to squash
367 bool more_late_algebraic
= true;
368 while (more_late_algebraic
) {
369 more_late_algebraic
= OPT(s
, nir_opt_algebraic_late
);
370 OPT_V(s
, nir_opt_constant_folding
);
371 OPT_V(s
, nir_copy_prop
);
372 OPT_V(s
, nir_opt_dce
);
373 OPT_V(s
, nir_opt_cse
);
376 OPT_V(s
, nir_opt_sink
, nir_move_const_undef
);
378 if (ir3_shader_debug
& IR3_DBG_DISASM
) {
379 debug_printf("----------------------\n");
380 nir_print_shader(s
, stdout
);
381 debug_printf("----------------------\n");
388 ir3_nir_scan_driver_consts(nir_shader
*shader
,
389 struct ir3_const_state
*layout
)
391 nir_foreach_function (function
, shader
) {
395 nir_foreach_block (block
, function
->impl
) {
396 nir_foreach_instr (instr
, block
) {
397 if (instr
->type
!= nir_instr_type_intrinsic
)
400 nir_intrinsic_instr
*intr
=
401 nir_instr_as_intrinsic(instr
);
404 switch (intr
->intrinsic
) {
405 case nir_intrinsic_get_buffer_size
:
406 idx
= nir_src_as_uint(intr
->src
[0]);
407 if (layout
->ssbo_size
.mask
& (1 << idx
))
409 layout
->ssbo_size
.mask
|= (1 << idx
);
410 layout
->ssbo_size
.off
[idx
] =
411 layout
->ssbo_size
.count
;
412 layout
->ssbo_size
.count
+= 1; /* one const per */
414 case nir_intrinsic_image_atomic_add
:
415 case nir_intrinsic_image_atomic_imin
:
416 case nir_intrinsic_image_atomic_umin
:
417 case nir_intrinsic_image_atomic_imax
:
418 case nir_intrinsic_image_atomic_umax
:
419 case nir_intrinsic_image_atomic_and
:
420 case nir_intrinsic_image_atomic_or
:
421 case nir_intrinsic_image_atomic_xor
:
422 case nir_intrinsic_image_atomic_exchange
:
423 case nir_intrinsic_image_atomic_comp_swap
:
424 case nir_intrinsic_image_store
:
425 case nir_intrinsic_image_size
:
426 idx
= nir_src_as_uint(intr
->src
[0]);
427 if (layout
->image_dims
.mask
& (1 << idx
))
429 layout
->image_dims
.mask
|= (1 << idx
);
430 layout
->image_dims
.off
[idx
] =
431 layout
->image_dims
.count
;
432 layout
->image_dims
.count
+= 3; /* three const per */
434 case nir_intrinsic_load_base_vertex
:
435 case nir_intrinsic_load_first_vertex
:
436 layout
->num_driver_params
=
437 MAX2(layout
->num_driver_params
, IR3_DP_VTXID_BASE
+ 1);
439 case nir_intrinsic_load_base_instance
:
440 layout
->num_driver_params
=
441 MAX2(layout
->num_driver_params
, IR3_DP_INSTID_BASE
+ 1);
443 case nir_intrinsic_load_user_clip_plane
:
444 layout
->num_driver_params
=
445 MAX2(layout
->num_driver_params
, IR3_DP_UCP7_W
+ 1);
447 case nir_intrinsic_load_num_work_groups
:
448 layout
->num_driver_params
=
449 MAX2(layout
->num_driver_params
, IR3_DP_NUM_WORK_GROUPS_Z
+ 1);
451 case nir_intrinsic_load_local_group_size
:
452 layout
->num_driver_params
=
453 MAX2(layout
->num_driver_params
, IR3_DP_LOCAL_GROUP_SIZE_Z
+ 1);
463 /* Sets up the non-variant-dependent constant state for the ir3_shader. Note
464 * that it is also used from ir3_nir_analyze_ubo_ranges() to figure out the
465 * maximum number of driver params that would eventually be used, to leave
466 * space for this function to allocate the driver params.
469 ir3_setup_const_state(struct ir3_shader
*shader
, nir_shader
*nir
,
470 struct ir3_const_state
*const_state
)
472 struct ir3_compiler
*compiler
= shader
->compiler
;
474 memset(&const_state
->offsets
, ~0, sizeof(const_state
->offsets
));
476 ir3_nir_scan_driver_consts(nir
, const_state
);
478 if ((compiler
->gpu_id
< 500) &&
479 (shader
->stream_output
.num_outputs
> 0)) {
480 const_state
->num_driver_params
=
481 MAX2(const_state
->num_driver_params
, IR3_DP_VTXCNT_MAX
+ 1);
484 const_state
->num_ubos
= nir
->info
.num_ubos
;
486 /* num_driver_params is scalar, align to vec4: */
487 const_state
->num_driver_params
= align(const_state
->num_driver_params
, 4);
489 debug_assert((const_state
->ubo_state
.size
% 16) == 0);
490 unsigned constoff
= const_state
->ubo_state
.size
/ 16;
491 unsigned ptrsz
= ir3_pointer_size(compiler
);
493 if (const_state
->num_ubos
> 0) {
494 const_state
->offsets
.ubo
= constoff
;
495 constoff
+= align(const_state
->num_ubos
* ptrsz
, 4) / 4;
498 if (const_state
->ssbo_size
.count
> 0) {
499 unsigned cnt
= const_state
->ssbo_size
.count
;
500 const_state
->offsets
.ssbo_sizes
= constoff
;
501 constoff
+= align(cnt
, 4) / 4;
504 if (const_state
->image_dims
.count
> 0) {
505 unsigned cnt
= const_state
->image_dims
.count
;
506 const_state
->offsets
.image_dims
= constoff
;
507 constoff
+= align(cnt
, 4) / 4;
510 if (const_state
->num_driver_params
> 0)
511 const_state
->offsets
.driver_param
= constoff
;
512 constoff
+= const_state
->num_driver_params
/ 4;
514 if ((shader
->type
== MESA_SHADER_VERTEX
) &&
515 (compiler
->gpu_id
< 500) &&
516 shader
->stream_output
.num_outputs
> 0) {
517 const_state
->offsets
.tfbo
= constoff
;
518 constoff
+= align(IR3_MAX_SO_BUFFERS
* ptrsz
, 4) / 4;
521 switch (shader
->type
) {
522 case MESA_SHADER_VERTEX
:
523 const_state
->offsets
.primitive_param
= constoff
;
526 case MESA_SHADER_TESS_CTRL
:
527 case MESA_SHADER_TESS_EVAL
:
528 constoff
= align(constoff
- 1, 4) + 3;
529 const_state
->offsets
.primitive_param
= constoff
;
530 const_state
->offsets
.primitive_map
= constoff
+ 5;
531 constoff
+= 5 + DIV_ROUND_UP(nir
->num_inputs
, 4);
533 case MESA_SHADER_GEOMETRY
:
534 const_state
->offsets
.primitive_param
= constoff
;
535 const_state
->offsets
.primitive_map
= constoff
+ 1;
536 constoff
+= 1 + DIV_ROUND_UP(nir
->num_inputs
, 4);
542 const_state
->offsets
.immediate
= constoff
;
544 assert(constoff
<= compiler
->max_const
);