src/freedreno/ir3/ir3_nir.c

   1 /*
   2  * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27
  28 #include "util/debug.h"
  29 #include "util/u_math.h"
  30
  31 #include "ir3_nir.h"
  32 #include "ir3_compiler.h"
  33 #include "ir3_shader.h"
  34
  35 static const nir_shader_compiler_options options = {
  36                 .lower_fpow = true,
  37                 .lower_scmp = true,
  38                 .lower_flrp16 = true,
  39                 .lower_flrp32 = true,
  40                 .lower_flrp64 = true,
  41                 .lower_ffract = true,
  42                 .lower_fmod = true,
  43                 .lower_fdiv = true,
  44                 .lower_isign = true,
  45                 .lower_ldexp = true,
  46                 .lower_uadd_carry = true,
  47                 .lower_usub_borrow = true,
  48                 .lower_mul_high = true,
  49                 .lower_mul_2x32_64 = true,
  50                 .fuse_ffma = true,
  51                 .vertex_id_zero_based = true,
  52                 .lower_extract_byte = true,
  53                 .lower_extract_word = true,
  54                 .lower_all_io_to_elements = true,
  55                 .lower_helper_invocation = true,
  56                 .lower_bitfield_insert_to_shifts = true,
  57                 .lower_bitfield_extract_to_shifts = true,
  58                 .lower_pack_half_2x16 = true,
  59                 .lower_pack_snorm_4x8 = true,
  60                 .lower_pack_snorm_2x16 = true,
  61                 .lower_pack_unorm_4x8 = true,
  62                 .lower_pack_unorm_2x16 = true,
  63                 .lower_unpack_half_2x16 = true,
  64                 .lower_unpack_snorm_4x8 = true,
  65                 .lower_unpack_snorm_2x16 = true,
  66                 .lower_unpack_unorm_4x8 = true,
  67                 .lower_unpack_unorm_2x16 = true,
  68                 .lower_pack_split = true,
  69                 .use_interpolated_input_intrinsics = true,
  70                 .lower_rotate = true,
  71                 .lower_to_scalar = true,
  72                 .has_imul24 = true,
  73 };
  74
  75 /* we don't want to lower vertex_id to _zero_based on newer gpus: */
  76 static const nir_shader_compiler_options options_a6xx = {
  77                 .lower_fpow = true,
  78                 .lower_scmp = true,
  79                 .lower_flrp16 = true,
  80                 .lower_flrp32 = true,
  81                 .lower_flrp64 = true,
  82                 .lower_ffract = true,
  83                 .lower_fmod = true,
  84                 .lower_fdiv = true,
  85                 .lower_isign = true,
  86                 .lower_ldexp = true,
  87                 .lower_uadd_carry = true,
  88                 .lower_usub_borrow = true,
  89                 .lower_mul_high = true,
  90                 .lower_mul_2x32_64 = true,
  91                 .fuse_ffma = true,
  92                 .vertex_id_zero_based = false,
  93                 .lower_extract_byte = true,
  94                 .lower_extract_word = true,
  95                 .lower_all_io_to_elements = true,
  96                 .lower_helper_invocation = true,
  97                 .lower_bitfield_insert_to_shifts = true,
  98                 .lower_bitfield_extract_to_shifts = true,
  99                 .lower_pack_half_2x16 = true,
 100                 .lower_pack_snorm_4x8 = true,
 101                 .lower_pack_snorm_2x16 = true,
 102                 .lower_pack_unorm_4x8 = true,
 103                 .lower_pack_unorm_2x16 = true,
 104                 .lower_unpack_half_2x16 = true,
 105                 .lower_unpack_snorm_4x8 = true,
 106                 .lower_unpack_snorm_2x16 = true,
 107                 .lower_unpack_unorm_4x8 = true,
 108                 .lower_unpack_unorm_2x16 = true,
 109                 .lower_pack_split = true,
 110                 .use_interpolated_input_intrinsics = true,
 111                 .lower_rotate = true,
 112                 .vectorize_io = true,
 113                 .lower_to_scalar = true,
 114                 .has_imul24 = true,
 115                 .max_unroll_iterations = 32,
 116 };
 117
 118 const nir_shader_compiler_options *
 119 ir3_get_compiler_options(struct ir3_compiler *compiler)
 120 {
 121         if (compiler->gpu_id >= 600)
 122                 return &options_a6xx;
 123         return &options;
 124 }
 125
 126 /* for given shader key, are any steps handled in nir? */
 127 bool
 128 ir3_key_lowers_nir(const struct ir3_shader_key *key)
 129 {
 130         return key->fsaturate_s | key->fsaturate_t | key->fsaturate_r |
 131                         key->vsaturate_s | key->vsaturate_t | key->vsaturate_r |
 132                         key->ucp_enables | key->color_two_side |
 133                         key->fclamp_color | key->vclamp_color |
 134                         key->tessellation | key->has_gs;
 135 }
 136
 137 #define OPT(nir, pass, ...) ({                             \
 138    bool this_progress = false;                             \
 139    NIR_PASS(this_progress, nir, pass, ##__VA_ARGS__);      \
 140    this_progress;                                          \
 141 })
 142
 143 #define OPT_V(nir, pass, ...) NIR_PASS_V(nir, pass, ##__VA_ARGS__)
 144
 145 static void
 146 ir3_optimize_loop(nir_shader *s)
 147 {
 148         bool progress;
 149         unsigned lower_flrp =
 150                 (s->options->lower_flrp16 ? 16 : 0) |
 151                 (s->options->lower_flrp32 ? 32 : 0) |
 152                 (s->options->lower_flrp64 ? 64 : 0);
 153
 154         do {
 155                 progress = false;
 156
 157                 OPT_V(s, nir_lower_vars_to_ssa);
 158                 progress |= OPT(s, nir_opt_copy_prop_vars);
 159                 progress |= OPT(s, nir_opt_dead_write_vars);
 160                 progress |= OPT(s, nir_lower_alu_to_scalar, NULL, NULL);
 161                 progress |= OPT(s, nir_lower_phis_to_scalar);
 162
 163                 progress |= OPT(s, nir_copy_prop);
 164                 progress |= OPT(s, nir_opt_dce);
 165                 progress |= OPT(s, nir_opt_cse);
 166                 static int gcm = -1;
 167                 if (gcm == -1)
 168                         gcm = env_var_as_unsigned("GCM", 0);
 169                 if (gcm == 1)
 170                         progress |= OPT(s, nir_opt_gcm, true);
 171                 else if (gcm == 2)
 172                         progress |= OPT(s, nir_opt_gcm, false);
 173                 progress |= OPT(s, nir_opt_peephole_select, 16, true, true);
 174                 progress |= OPT(s, nir_opt_intrinsics);
 175                 progress |= OPT(s, nir_opt_algebraic);
 176                 progress |= OPT(s, nir_lower_alu);
 177                 progress |= OPT(s, nir_lower_pack);
 178                 progress |= OPT(s, nir_opt_constant_folding);
 179
 180                 if (lower_flrp != 0) {
 181                         if (OPT(s, nir_lower_flrp,
 182                                         lower_flrp,
 183                                         false /* always_precise */,
 184                                         s->options->lower_ffma)) {
 185                                 OPT(s, nir_opt_constant_folding);
 186                                 progress = true;
 187                         }
 188
 189                         /* Nothing should rematerialize any flrps, so we only
 190                          * need to do this lowering once.
 191                          */
 192                         lower_flrp = 0;
 193                 }
 194
 195                 progress |= OPT(s, nir_opt_dead_cf);
 196                 if (OPT(s, nir_opt_trivial_continues)) {
 197                         progress |= true;
 198                         /* If nir_opt_trivial_continues makes progress, then we need to clean
 199                          * things up if we want any hope of nir_opt_if or nir_opt_loop_unroll
 200                          * to make progress.
 201                          */
 202                         OPT(s, nir_copy_prop);
 203                         OPT(s, nir_opt_dce);
 204                 }
 205                 progress |= OPT(s, nir_opt_if, false);
 206                 progress |= OPT(s, nir_opt_remove_phis);
 207                 progress |= OPT(s, nir_opt_undef);
 208         } while (progress);
 209 }
 210
 211 static bool
 212 should_split_wrmask(const nir_instr *instr, const void *data)
 213 {
 214         nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
 215
 216         switch (intr->intrinsic) {
 217         case nir_intrinsic_store_ssbo:
 218         case nir_intrinsic_store_shared:
 219         case nir_intrinsic_store_global:
 220                 return true;
 221         default:
 222                 return false;
 223         }
 224 }
 225
 226 void
 227 ir3_optimize_nir(struct ir3_shader *shader, nir_shader *s,
 228                 const struct ir3_shader_key *key)
 229 {
 230         struct nir_lower_tex_options tex_options = {
 231                         .lower_rect = 0,
 232                         .lower_tg4_offsets = true,
 233         };
 234
 235         if (key && (key->has_gs || key->tessellation)) {
 236                 switch (shader->type) {
 237                 case MESA_SHADER_VERTEX:
 238                         NIR_PASS_V(s, ir3_nir_lower_to_explicit_output, shader, key->tessellation);
 239                         break;
 240                 case MESA_SHADER_TESS_CTRL:
 241                         NIR_PASS_V(s, ir3_nir_lower_tess_ctrl, shader, key->tessellation);
 242                         NIR_PASS_V(s, ir3_nir_lower_to_explicit_input);
 243                         break;
 244                 case MESA_SHADER_TESS_EVAL:
 245                         NIR_PASS_V(s, ir3_nir_lower_tess_eval, key->tessellation);
 246                         if (key->has_gs)
 247                                 NIR_PASS_V(s, ir3_nir_lower_to_explicit_output, shader, key->tessellation);
 248                         break;
 249                 case MESA_SHADER_GEOMETRY:
 250                         NIR_PASS_V(s, ir3_nir_lower_to_explicit_input);
 251                         break;
 252                 default:
 253                         break;
 254                 }
 255         }
 256
 257         if (key) {
 258                 switch (shader->type) {
 259                 case MESA_SHADER_FRAGMENT:
 260                         tex_options.saturate_s = key->fsaturate_s;
 261                         tex_options.saturate_t = key->fsaturate_t;
 262                         tex_options.saturate_r = key->fsaturate_r;
 263                         break;
 264                 case MESA_SHADER_VERTEX:
 265                         tex_options.saturate_s = key->vsaturate_s;
 266                         tex_options.saturate_t = key->vsaturate_t;
 267                         tex_options.saturate_r = key->vsaturate_r;
 268                         break;
 269                 default:
 270                         /* TODO */
 271                         break;
 272                 }
 273         }
 274
 275         if (shader->compiler->gpu_id >= 400) {
 276                 /* a4xx seems to have *no* sam.p */
 277                 tex_options.lower_txp = ~0;  /* lower all txp */
 278         } else {
 279                 /* a3xx just needs to avoid sam.p for 3d tex */
 280                 tex_options.lower_txp = (1 << GLSL_SAMPLER_DIM_3D);
 281         }
 282
 283         if (ir3_shader_debug & IR3_DBG_DISASM) {
 284                 debug_printf("----------------------\n");
 285                 nir_print_shader(s, stdout);
 286                 debug_printf("----------------------\n");
 287         }
 288
 289         OPT_V(s, nir_lower_regs_to_ssa);
 290         OPT_V(s, nir_lower_wrmasks, should_split_wrmask, s);
 291
 292         if (key) {
 293                 if (s->info.stage == MESA_SHADER_VERTEX) {
 294                         OPT_V(s, nir_lower_clip_vs, key->ucp_enables, false, false, NULL);
 295                         if (key->vclamp_color)
 296                                 OPT_V(s, nir_lower_clamp_color_outputs);
 297                 } else if (s->info.stage == MESA_SHADER_FRAGMENT) {
 298                         OPT_V(s, nir_lower_clip_fs, key->ucp_enables, false);
 299                         if (key->fclamp_color)
 300                                 OPT_V(s, nir_lower_clamp_color_outputs);
 301                 }
 302                 if (key->color_two_side) {
 303                         OPT_V(s, nir_lower_two_sided_color);
 304                 }
 305         } else {
 306                 /* only want to do this the first time (when key is null)
 307                  * and not again on any potential 2nd variant lowering pass:
 308                  */
 309                 OPT_V(s, ir3_nir_apply_trig_workarounds);
 310
 311                 /* This wouldn't hurt to run multiple times, but there is
 312                  * no need to:
 313                  */
 314                 if (shader->type == MESA_SHADER_FRAGMENT)
 315                         OPT_V(s, nir_lower_fb_read);
 316         }
 317
 318         OPT_V(s, nir_lower_tex, &tex_options);
 319         OPT_V(s, nir_lower_load_const_to_scalar);
 320         if (shader->compiler->gpu_id < 500)
 321                 OPT_V(s, ir3_nir_lower_tg4_to_tex);
 322
 323         ir3_optimize_loop(s);
 324
 325         /* do ubo load and idiv lowering after first opt loop to get a chance to
 326          * propagate constants for divide by immed power-of-two and constant ubo
 327          * block/offsets:
 328          *
 329          * NOTE that UBO analysis pass should only be done once, before variants
 330          */
 331         const bool ubo_progress = !key && OPT(s, ir3_nir_analyze_ubo_ranges, shader);
 332         const bool idiv_progress = OPT(s, nir_lower_idiv, nir_lower_idiv_fast);
 333         /* UBO offset lowering has to come after we've decided what will be left as load_ubo */
 334         OPT_V(s, ir3_nir_lower_io_offsets, shader->compiler->gpu_id);
 335
 336         if (ubo_progress || idiv_progress)
 337                 ir3_optimize_loop(s);
 338
 339         /* Do late algebraic optimization to turn add(a, neg(b)) back into
 340         * subs, then the mandatory cleanup after algebraic.  Note that it may
 341         * produce fnegs, and if so then we need to keep running to squash
 342         * fneg(fneg(a)).
 343         */
 344         bool more_late_algebraic = true;
 345         while (more_late_algebraic) {
 346                 more_late_algebraic = OPT(s, nir_opt_algebraic_late);
 347                 OPT_V(s, nir_opt_constant_folding);
 348                 OPT_V(s, nir_copy_prop);
 349                 OPT_V(s, nir_opt_dce);
 350                 OPT_V(s, nir_opt_cse);
 351         }
 352
 353         OPT_V(s, nir_remove_dead_variables, nir_var_function_temp, NULL);
 354
 355         OPT_V(s, nir_opt_sink, nir_move_const_undef);
 356
 357         if (ir3_shader_debug & IR3_DBG_DISASM) {
 358                 debug_printf("----------------------\n");
 359                 nir_print_shader(s, stdout);
 360                 debug_printf("----------------------\n");
 361         }
 362
 363         nir_sweep(s);
 364
 365         /* The first time thru, when not creating variant, do the one-time
 366          * const_state layout setup.  This should be done after ubo range
 367          * analysis.
 368          */
 369         if (!key) {
 370                 ir3_setup_const_state(shader, s, &shader->const_state);
 371         }
 372 }
 373
 374 static void
 375 ir3_nir_scan_driver_consts(nir_shader *shader,
 376                 struct ir3_const_state *layout)
 377 {
 378         nir_foreach_function (function, shader) {
 379                 if (!function->impl)
 380                         continue;
 381
 382                 nir_foreach_block (block, function->impl) {
 383                         nir_foreach_instr (instr, block) {
 384                                 if (instr->type != nir_instr_type_intrinsic)
 385                                         continue;
 386
 387                                 nir_intrinsic_instr *intr =
 388                                         nir_instr_as_intrinsic(instr);
 389                                 unsigned idx;
 390
 391                                 switch (intr->intrinsic) {
 392                                 case nir_intrinsic_get_buffer_size:
 393                                         idx = nir_src_as_uint(intr->src[0]);
 394                                         if (layout->ssbo_size.mask & (1 << idx))
 395                                                 break;
 396                                         layout->ssbo_size.mask |= (1 << idx);
 397                                         layout->ssbo_size.off[idx] =
 398                                                 layout->ssbo_size.count;
 399                                         layout->ssbo_size.count += 1; /* one const per */
 400                                         break;
 401                                 case nir_intrinsic_image_atomic_add:
 402                                 case nir_intrinsic_image_atomic_imin:
 403                                 case nir_intrinsic_image_atomic_umin:
 404                                 case nir_intrinsic_image_atomic_imax:
 405                                 case nir_intrinsic_image_atomic_umax:
 406                                 case nir_intrinsic_image_atomic_and:
 407                                 case nir_intrinsic_image_atomic_or:
 408                                 case nir_intrinsic_image_atomic_xor:
 409                                 case nir_intrinsic_image_atomic_exchange:
 410                                 case nir_intrinsic_image_atomic_comp_swap:
 411                                 case nir_intrinsic_image_store:
 412                                 case nir_intrinsic_image_size:
 413                                         idx = nir_src_as_uint(intr->src[0]);
 414                                         if (layout->image_dims.mask & (1 << idx))
 415                                                 break;
 416                                         layout->image_dims.mask |= (1 << idx);
 417                                         layout->image_dims.off[idx] =
 418                                                 layout->image_dims.count;
 419                                         layout->image_dims.count += 3; /* three const per */
 420                                         break;
 421                                 case nir_intrinsic_load_base_vertex:
 422                                 case nir_intrinsic_load_first_vertex:
 423                                         layout->num_driver_params =
 424                                                 MAX2(layout->num_driver_params, IR3_DP_VTXID_BASE + 1);
 425                                         break;
 426                                 case nir_intrinsic_load_base_instance:
 427                                         layout->num_driver_params =
 428                                                 MAX2(layout->num_driver_params, IR3_DP_INSTID_BASE + 1);
 429                                         break;
 430                                 case nir_intrinsic_load_user_clip_plane:
 431                                         layout->num_driver_params =
 432                                                 MAX2(layout->num_driver_params, IR3_DP_UCP7_W + 1);
 433                                         break;
 434                                 case nir_intrinsic_load_num_work_groups:
 435                                         layout->num_driver_params =
 436                                                 MAX2(layout->num_driver_params, IR3_DP_NUM_WORK_GROUPS_Z + 1);
 437                                         break;
 438                                 case nir_intrinsic_load_local_group_size:
 439                                         layout->num_driver_params =
 440                                                 MAX2(layout->num_driver_params, IR3_DP_LOCAL_GROUP_SIZE_Z + 1);
 441                                         break;
 442                                 default:
 443                                         break;
 444                                 }
 445                         }
 446                 }
 447         }
 448 }
 449
 450 /* Sets up the non-variant-dependent constant state for the ir3_shader.  Note
 451  * that it is also used from ir3_nir_analyze_ubo_ranges() to figure out the
 452  * maximum number of driver params that would eventually be used, to leave
 453  * space for this function to allocate the driver params.
 454  */
 455 void
 456 ir3_setup_const_state(struct ir3_shader *shader, nir_shader *nir,
 457         struct ir3_const_state *const_state)
 458 {
 459         struct ir3_compiler *compiler = shader->compiler;
 460
 461         memset(&const_state->offsets, ~0, sizeof(const_state->offsets));
 462
 463         ir3_nir_scan_driver_consts(nir, const_state);
 464
 465         if ((compiler->gpu_id < 500) &&
 466                         (shader->stream_output.num_outputs > 0)) {
 467                 const_state->num_driver_params =
 468                         MAX2(const_state->num_driver_params, IR3_DP_VTXCNT_MAX + 1);
 469         }
 470
 471         /* On a6xx, we use UBO descriptors and LDC instead of UBO pointers in the
 472          * constbuf.
 473          */
 474         if (compiler->gpu_id >= 600)
 475                 shader->num_ubos = nir->info.num_ubos;
 476         else
 477                 const_state->num_ubos = nir->info.num_ubos;
 478
 479         /* num_driver_params is scalar, align to vec4: */
 480         const_state->num_driver_params = align(const_state->num_driver_params, 4);
 481
 482         debug_assert((shader->ubo_state.size % 16) == 0);
 483         unsigned constoff = shader->ubo_state.size / 16;
 484         unsigned ptrsz = ir3_pointer_size(compiler);
 485
 486         if (const_state->num_ubos > 0) {
 487                 const_state->offsets.ubo = constoff;
 488                 constoff += align(const_state->num_ubos * ptrsz, 4) / 4;
 489         }
 490
 491         if (const_state->ssbo_size.count > 0) {
 492                 unsigned cnt = const_state->ssbo_size.count;
 493                 const_state->offsets.ssbo_sizes = constoff;
 494                 constoff += align(cnt, 4) / 4;
 495         }
 496
 497         if (const_state->image_dims.count > 0) {
 498                 unsigned cnt = const_state->image_dims.count;
 499                 const_state->offsets.image_dims = constoff;
 500                 constoff += align(cnt, 4) / 4;
 501         }
 502
 503         if (const_state->num_driver_params > 0)
 504                 const_state->offsets.driver_param = constoff;
 505         constoff += const_state->num_driver_params / 4;
 506
 507         if ((shader->type == MESA_SHADER_VERTEX) &&
 508                         (compiler->gpu_id < 500) &&
 509                         shader->stream_output.num_outputs > 0) {
 510                 const_state->offsets.tfbo = constoff;
 511                 constoff += align(IR3_MAX_SO_BUFFERS * ptrsz, 4) / 4;
 512         }
 513
 514         switch (shader->type) {
 515         case MESA_SHADER_VERTEX:
 516                 const_state->offsets.primitive_param = constoff;
 517                 constoff += 1;
 518                 break;
 519         case MESA_SHADER_TESS_CTRL:
 520         case MESA_SHADER_TESS_EVAL:
 521                 constoff = align(constoff - 1, 4) + 3;
 522                 const_state->offsets.primitive_param = constoff;
 523                 const_state->offsets.primitive_map = constoff + 5;
 524                 constoff += 5 + DIV_ROUND_UP(nir->num_inputs, 4);
 525                 break;
 526         case MESA_SHADER_GEOMETRY:
 527                 const_state->offsets.primitive_param = constoff;
 528                 const_state->offsets.primitive_map = constoff + 1;
 529                 constoff += 1 + DIV_ROUND_UP(nir->num_inputs, 4);
 530                 break;
 531         default:
 532                 break;
 533         }
 534
 535         const_state->offsets.immediate = constoff;
 536
 537         assert(constoff <= compiler->max_const);
 538 }