src/freedreno/ir3/ir3_nir.c

   1 /*
   2  * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27
  28 #include "util/debug.h"
  29 #include "util/u_math.h"
  30
  31 #include "ir3_nir.h"
  32 #include "ir3_compiler.h"
  33 #include "ir3_shader.h"
  34
  35 static void ir3_setup_const_state(struct ir3_shader *shader, nir_shader *nir);
  36
  37 static const nir_shader_compiler_options options = {
  38                 .lower_fpow = true,
  39                 .lower_scmp = true,
  40                 .lower_flrp32 = true,
  41                 .lower_flrp64 = true,
  42                 .lower_ffract = true,
  43                 .lower_fmod = true,
  44                 .lower_fdiv = true,
  45                 .lower_isign = true,
  46                 .lower_ldexp = true,
  47                 .lower_uadd_carry = true,
  48                 .lower_mul_high = true,
  49                 .fuse_ffma = true,
  50                 .vertex_id_zero_based = true,
  51                 .lower_extract_byte = true,
  52                 .lower_extract_word = true,
  53                 .lower_all_io_to_elements = true,
  54                 .lower_helper_invocation = true,
  55                 .lower_bitfield_insert_to_shifts = true,
  56                 .lower_bitfield_extract_to_shifts = true,
  57                 .use_interpolated_input_intrinsics = true,
  58                 .lower_rotate = true,
  59 };
  60
  61 /* we don't want to lower vertex_id to _zero_based on newer gpus: */
  62 static const nir_shader_compiler_options options_a6xx = {
  63                 .lower_fpow = true,
  64                 .lower_scmp = true,
  65                 .lower_flrp32 = true,
  66                 .lower_flrp64 = true,
  67                 .lower_ffract = true,
  68                 .lower_fmod = true,
  69                 .lower_fdiv = true,
  70                 .lower_isign = true,
  71                 .lower_ldexp = true,
  72                 .lower_uadd_carry = true,
  73                 .lower_mul_high = true,
  74                 .fuse_ffma = true,
  75                 .vertex_id_zero_based = false,
  76                 .lower_extract_byte = true,
  77                 .lower_extract_word = true,
  78                 .lower_all_io_to_elements = true,
  79                 .lower_helper_invocation = true,
  80                 .lower_bitfield_insert_to_shifts = true,
  81                 .lower_bitfield_extract_to_shifts = true,
  82                 .use_interpolated_input_intrinsics = true,
  83                 .lower_rotate = true,
  84                 .vectorize_io = true,
  85 };
  86
  87 const nir_shader_compiler_options *
  88 ir3_get_compiler_options(struct ir3_compiler *compiler)
  89 {
  90         if (compiler->gpu_id >= 600)
  91                 return &options_a6xx;
  92         return &options;
  93 }
  94
  95 /* for given shader key, are any steps handled in nir? */
  96 bool
  97 ir3_key_lowers_nir(const struct ir3_shader_key *key)
  98 {
  99         return key->fsaturate_s | key->fsaturate_t | key->fsaturate_r |
 100                         key->vsaturate_s | key->vsaturate_t | key->vsaturate_r |
 101                         key->ucp_enables | key->color_two_side |
 102                         key->fclamp_color | key->vclamp_color;
 103 }
 104
 105 #define OPT(nir, pass, ...) ({                             \
 106    bool this_progress = false;                             \
 107    NIR_PASS(this_progress, nir, pass, ##__VA_ARGS__);      \
 108    this_progress;                                          \
 109 })
 110
 111 #define OPT_V(nir, pass, ...) NIR_PASS_V(nir, pass, ##__VA_ARGS__)
 112
 113 static void
 114 ir3_optimize_loop(nir_shader *s)
 115 {
 116         bool progress;
 117         unsigned lower_flrp =
 118                 (s->options->lower_flrp16 ? 16 : 0) |
 119                 (s->options->lower_flrp32 ? 32 : 0) |
 120                 (s->options->lower_flrp64 ? 64 : 0);
 121
 122         do {
 123                 progress = false;
 124
 125                 OPT_V(s, nir_lower_vars_to_ssa);
 126                 progress |= OPT(s, nir_opt_copy_prop_vars);
 127                 progress |= OPT(s, nir_opt_dead_write_vars);
 128                 progress |= OPT(s, nir_lower_alu_to_scalar, NULL, NULL);
 129                 progress |= OPT(s, nir_lower_phis_to_scalar);
 130
 131                 progress |= OPT(s, nir_copy_prop);
 132                 progress |= OPT(s, nir_opt_dce);
 133                 progress |= OPT(s, nir_opt_cse);
 134                 static int gcm = -1;
 135                 if (gcm == -1)
 136                         gcm = env_var_as_unsigned("GCM", 0);
 137                 if (gcm == 1)
 138                         progress |= OPT(s, nir_opt_gcm, true);
 139                 else if (gcm == 2)
 140                         progress |= OPT(s, nir_opt_gcm, false);
 141                 progress |= OPT(s, nir_opt_peephole_select, 16, true, true);
 142                 progress |= OPT(s, nir_opt_intrinsics);
 143                 progress |= OPT(s, nir_opt_algebraic);
 144                 progress |= OPT(s, nir_opt_constant_folding);
 145
 146                 if (lower_flrp != 0) {
 147                         if (OPT(s, nir_lower_flrp,
 148                                         lower_flrp,
 149                                         false /* always_precise */,
 150                                         s->options->lower_ffma)) {
 151                                 OPT(s, nir_opt_constant_folding);
 152                                 progress = true;
 153                         }
 154
 155                         /* Nothing should rematerialize any flrps, so we only
 156                          * need to do this lowering once.
 157                          */
 158                         lower_flrp = 0;
 159                 }
 160
 161                 progress |= OPT(s, nir_opt_dead_cf);
 162                 if (OPT(s, nir_opt_trivial_continues)) {
 163                         progress |= true;
 164                         /* If nir_opt_trivial_continues makes progress, then we need to clean
 165                          * things up if we want any hope of nir_opt_if or nir_opt_loop_unroll
 166                          * to make progress.
 167                          */
 168                         OPT(s, nir_copy_prop);
 169                         OPT(s, nir_opt_dce);
 170                 }
 171                 progress |= OPT(s, nir_opt_if, false);
 172                 progress |= OPT(s, nir_opt_remove_phis);
 173                 progress |= OPT(s, nir_opt_undef);
 174
 175         } while (progress);
 176 }
 177
 178 void
 179 ir3_optimize_nir(struct ir3_shader *shader, nir_shader *s,
 180                 const struct ir3_shader_key *key)
 181 {
 182         struct nir_lower_tex_options tex_options = {
 183                         .lower_rect = 0,
 184                         .lower_tg4_offsets = true,
 185         };
 186
 187         if (key) {
 188                 switch (shader->type) {
 189                 case MESA_SHADER_FRAGMENT:
 190                         tex_options.saturate_s = key->fsaturate_s;
 191                         tex_options.saturate_t = key->fsaturate_t;
 192                         tex_options.saturate_r = key->fsaturate_r;
 193                         break;
 194                 case MESA_SHADER_VERTEX:
 195                         tex_options.saturate_s = key->vsaturate_s;
 196                         tex_options.saturate_t = key->vsaturate_t;
 197                         tex_options.saturate_r = key->vsaturate_r;
 198                         break;
 199                 default:
 200                         /* TODO */
 201                         break;
 202                 }
 203         }
 204
 205         if (shader->compiler->gpu_id >= 400) {
 206                 /* a4xx seems to have *no* sam.p */
 207                 tex_options.lower_txp = ~0;  /* lower all txp */
 208         } else {
 209                 /* a3xx just needs to avoid sam.p for 3d tex */
 210                 tex_options.lower_txp = (1 << GLSL_SAMPLER_DIM_3D);
 211         }
 212
 213         if (ir3_shader_debug & IR3_DBG_DISASM) {
 214                 debug_printf("----------------------\n");
 215                 nir_print_shader(s, stdout);
 216                 debug_printf("----------------------\n");
 217         }
 218
 219         OPT_V(s, nir_lower_regs_to_ssa);
 220         OPT_V(s, ir3_nir_lower_io_offsets);
 221
 222         if (key) {
 223                 if (s->info.stage == MESA_SHADER_VERTEX) {
 224                         OPT_V(s, nir_lower_clip_vs, key->ucp_enables, false);
 225                         if (key->vclamp_color)
 226                                 OPT_V(s, nir_lower_clamp_color_outputs);
 227                 } else if (s->info.stage == MESA_SHADER_FRAGMENT) {
 228                         OPT_V(s, nir_lower_clip_fs, key->ucp_enables);
 229                         if (key->fclamp_color)
 230                                 OPT_V(s, nir_lower_clamp_color_outputs);
 231                 }
 232                 if (key->color_two_side) {
 233                         OPT_V(s, nir_lower_two_sided_color);
 234                 }
 235         } else {
 236                 /* only want to do this the first time (when key is null)
 237                  * and not again on any potential 2nd variant lowering pass:
 238                  */
 239                 OPT_V(s, ir3_nir_apply_trig_workarounds);
 240
 241                 /* This wouldn't hurt to run multiple times, but there is
 242                  * no need to:
 243                  */
 244                 if (shader->type == MESA_SHADER_FRAGMENT)
 245                         OPT_V(s, nir_lower_fb_read);
 246         }
 247
 248         OPT_V(s, nir_lower_tex, &tex_options);
 249         OPT_V(s, nir_lower_load_const_to_scalar);
 250         if (shader->compiler->gpu_id < 500)
 251                 OPT_V(s, ir3_nir_lower_tg4_to_tex);
 252
 253         ir3_optimize_loop(s);
 254
 255         /* do ubo load and idiv lowering after first opt loop to get a chance to
 256          * propagate constants for divide by immed power-of-two and constant ubo
 257          * block/offsets:
 258          *
 259          * NOTE that UBO analysis pass should only be done once, before variants
 260          */
 261         const bool ubo_progress = !key && OPT(s, ir3_nir_analyze_ubo_ranges, shader);
 262         const bool idiv_progress = OPT(s, nir_lower_idiv);
 263         if (ubo_progress || idiv_progress)
 264                 ir3_optimize_loop(s);
 265
 266         /* Do late algebraic optimization to turn add(a, neg(b)) back into
 267         * subs, then the mandatory cleanup after algebraic.  Note that it may
 268         * produce fnegs, and if so then we need to keep running to squash
 269         * fneg(fneg(a)).
 270         */
 271         bool more_late_algebraic = true;
 272         while (more_late_algebraic) {
 273                 more_late_algebraic = OPT(s, nir_opt_algebraic_late);
 274                 OPT_V(s, nir_opt_constant_folding);
 275                 OPT_V(s, nir_copy_prop);
 276                 OPT_V(s, nir_opt_dce);
 277                 OPT_V(s, nir_opt_cse);
 278         }
 279
 280         OPT_V(s, nir_remove_dead_variables, nir_var_function_temp);
 281
 282         OPT_V(s, nir_opt_sink, nir_move_const_undef);
 283
 284         if (ir3_shader_debug & IR3_DBG_DISASM) {
 285                 debug_printf("----------------------\n");
 286                 nir_print_shader(s, stdout);
 287                 debug_printf("----------------------\n");
 288         }
 289
 290         nir_sweep(s);
 291
 292         /* The first time thru, when not creating variant, do the one-time
 293          * const_state layout setup.  This should be done after ubo range
 294          * analysis.
 295          */
 296         if (!key) {
 297                 ir3_setup_const_state(shader, s);
 298         }
 299 }
 300
 301 static void
 302 ir3_nir_scan_driver_consts(nir_shader *shader,
 303                 struct ir3_const_state *layout)
 304 {
 305         nir_foreach_function(function, shader) {
 306                 if (!function->impl)
 307                         continue;
 308
 309                 nir_foreach_block(block, function->impl) {
 310                         nir_foreach_instr(instr, block) {
 311                                 if (instr->type != nir_instr_type_intrinsic)
 312                                         continue;
 313
 314                                 nir_intrinsic_instr *intr =
 315                                         nir_instr_as_intrinsic(instr);
 316                                 unsigned idx;
 317
 318                                 switch (intr->intrinsic) {
 319                                 case nir_intrinsic_get_buffer_size:
 320                                         idx = nir_src_as_uint(intr->src[0]);
 321                                         if (layout->ssbo_size.mask & (1 << idx))
 322                                                 break;
 323                                         layout->ssbo_size.mask |= (1 << idx);
 324                                         layout->ssbo_size.off[idx] =
 325                                                 layout->ssbo_size.count;
 326                                         layout->ssbo_size.count += 1; /* one const per */
 327                                         break;
 328                                 case nir_intrinsic_image_deref_atomic_add:
 329                                 case nir_intrinsic_image_deref_atomic_imin:
 330                                 case nir_intrinsic_image_deref_atomic_umin:
 331                                 case nir_intrinsic_image_deref_atomic_imax:
 332                                 case nir_intrinsic_image_deref_atomic_umax:
 333                                 case nir_intrinsic_image_deref_atomic_and:
 334                                 case nir_intrinsic_image_deref_atomic_or:
 335                                 case nir_intrinsic_image_deref_atomic_xor:
 336                                 case nir_intrinsic_image_deref_atomic_exchange:
 337                                 case nir_intrinsic_image_deref_atomic_comp_swap:
 338                                 case nir_intrinsic_image_deref_store:
 339                                 case nir_intrinsic_image_deref_size:
 340                                         idx = nir_intrinsic_get_var(intr, 0)->data.driver_location;
 341                                         if (layout->image_dims.mask & (1 << idx))
 342                                                 break;
 343                                         layout->image_dims.mask |= (1 << idx);
 344                                         layout->image_dims.off[idx] =
 345                                                 layout->image_dims.count;
 346                                         layout->image_dims.count += 3; /* three const per */
 347                                         break;
 348                                 case nir_intrinsic_load_ubo:
 349                                         if (nir_src_is_const(intr->src[0])) {
 350                                                 layout->num_ubos = MAX2(layout->num_ubos,
 351                                                                 nir_src_as_uint(intr->src[0]) + 1);
 352                                         } else {
 353                                                 layout->num_ubos = shader->info.num_ubos;
 354                                         }
 355                                         break;
 356                                 case nir_intrinsic_load_base_vertex:
 357                                 case nir_intrinsic_load_first_vertex:
 358                                         layout->num_driver_params =
 359                                                 MAX2(layout->num_driver_params, IR3_DP_VTXID_BASE + 1);
 360                                         break;
 361                                 case nir_intrinsic_load_user_clip_plane:
 362                                         layout->num_driver_params =
 363                                                 MAX2(layout->num_driver_params, IR3_DP_UCP7_W + 1);
 364                                         break;
 365                                 case nir_intrinsic_load_num_work_groups:
 366                                         layout->num_driver_params =
 367                                                 MAX2(layout->num_driver_params, IR3_DP_NUM_WORK_GROUPS_Z + 1);
 368                                         break;
 369                                 case nir_intrinsic_load_local_group_size:
 370                                         layout->num_driver_params =
 371                                                 MAX2(layout->num_driver_params, IR3_DP_LOCAL_GROUP_SIZE_Z + 1);
 372                                         break;
 373                                 default:
 374                                         break;
 375                                 }
 376                         }
 377                 }
 378         }
 379 }
 380
 381 static void
 382 ir3_setup_const_state(struct ir3_shader *shader, nir_shader *nir)
 383 {
 384         struct ir3_compiler *compiler = shader->compiler;
 385         struct ir3_const_state *const_state = &shader->const_state;
 386
 387         memset(&const_state->offsets, ~0, sizeof(const_state->offsets));
 388
 389         ir3_nir_scan_driver_consts(nir, const_state);
 390
 391         if ((compiler->gpu_id < 500) &&
 392                         (shader->stream_output.num_outputs > 0)) {
 393                 const_state->num_driver_params =
 394                         MAX2(const_state->num_driver_params, IR3_DP_VTXCNT_MAX + 1);
 395         }
 396
 397         /* num_driver_params is scalar, align to vec4: */
 398         const_state->num_driver_params = align(const_state->num_driver_params, 4);
 399
 400         debug_assert((shader->ubo_state.size % 16) == 0);
 401         unsigned constoff = align(shader->ubo_state.size / 16, 8);
 402         unsigned ptrsz = ir3_pointer_size(compiler);
 403
 404         if (const_state->num_ubos > 0) {
 405                 const_state->offsets.ubo = constoff;
 406                 constoff += align(nir->info.num_ubos * ptrsz, 4) / 4;
 407         }
 408
 409         if (const_state->ssbo_size.count > 0) {
 410                 unsigned cnt = const_state->ssbo_size.count;
 411                 const_state->offsets.ssbo_sizes = constoff;
 412                 constoff += align(cnt, 4) / 4;
 413         }
 414
 415         if (const_state->image_dims.count > 0) {
 416                 unsigned cnt = const_state->image_dims.count;
 417                 const_state->offsets.image_dims = constoff;
 418                 constoff += align(cnt, 4) / 4;
 419         }
 420
 421         if (const_state->num_driver_params > 0)
 422                 const_state->offsets.driver_param = constoff;
 423         constoff += const_state->num_driver_params / 4;
 424
 425         if ((shader->type == MESA_SHADER_VERTEX) &&
 426                         (compiler->gpu_id < 500) &&
 427                         shader->stream_output.num_outputs > 0) {
 428                 const_state->offsets.tfbo = constoff;
 429                 constoff += align(IR3_MAX_SO_BUFFERS * ptrsz, 4) / 4;
 430         }
 431
 432         const_state->offsets.immediate = constoff;
 433 }