src/freedreno/ir3/ir3_nir.c

   1 /*
   2  * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27
  28 #include "util/debug.h"
  29 #include "util/u_math.h"
  30
  31 #include "ir3_nir.h"
  32 #include "ir3_compiler.h"
  33 #include "ir3_shader.h"
  34
  35 static const nir_shader_compiler_options options = {
  36                 .lower_fpow = true,
  37                 .lower_scmp = true,
  38                 .lower_flrp16 = true,
  39                 .lower_flrp32 = true,
  40                 .lower_flrp64 = true,
  41                 .lower_ffract = true,
  42                 .lower_fmod = true,
  43                 .lower_fdiv = true,
  44                 .lower_isign = true,
  45                 .lower_ldexp = true,
  46                 .lower_uadd_carry = true,
  47                 .lower_usub_borrow = true,
  48                 .lower_mul_high = true,
  49                 .lower_mul_2x32_64 = true,
  50                 .fuse_ffma = true,
  51                 .vertex_id_zero_based = true,
  52                 .lower_extract_byte = true,
  53                 .lower_extract_word = true,
  54                 .lower_all_io_to_elements = true,
  55                 .lower_helper_invocation = true,
  56                 .lower_bitfield_insert_to_shifts = true,
  57                 .lower_bitfield_extract_to_shifts = true,
  58                 .lower_pack_half_2x16 = true,
  59                 .lower_pack_snorm_4x8 = true,
  60                 .lower_pack_snorm_2x16 = true,
  61                 .lower_pack_unorm_4x8 = true,
  62                 .lower_pack_unorm_2x16 = true,
  63                 .lower_unpack_half_2x16 = true,
  64                 .lower_unpack_snorm_4x8 = true,
  65                 .lower_unpack_snorm_2x16 = true,
  66                 .lower_unpack_unorm_4x8 = true,
  67                 .lower_unpack_unorm_2x16 = true,
  68                 .lower_pack_split = true,
  69                 .use_interpolated_input_intrinsics = true,
  70                 .lower_rotate = true,
  71                 .lower_to_scalar = true,
  72                 .has_imul24 = true,
  73 };
  74
  75 /* we don't want to lower vertex_id to _zero_based on newer gpus: */
  76 static const nir_shader_compiler_options options_a6xx = {
  77                 .lower_fpow = true,
  78                 .lower_scmp = true,
  79                 .lower_flrp16 = true,
  80                 .lower_flrp32 = true,
  81                 .lower_flrp64 = true,
  82                 .lower_ffract = true,
  83                 .lower_fmod = true,
  84                 .lower_fdiv = true,
  85                 .lower_isign = true,
  86                 .lower_ldexp = true,
  87                 .lower_uadd_carry = true,
  88                 .lower_usub_borrow = true,
  89                 .lower_mul_high = true,
  90                 .lower_mul_2x32_64 = true,
  91                 .fuse_ffma = true,
  92                 .vertex_id_zero_based = false,
  93                 .lower_extract_byte = true,
  94                 .lower_extract_word = true,
  95                 .lower_all_io_to_elements = true,
  96                 .lower_helper_invocation = true,
  97                 .lower_bitfield_insert_to_shifts = true,
  98                 .lower_bitfield_extract_to_shifts = true,
  99                 .lower_pack_half_2x16 = true,
 100                 .lower_pack_snorm_4x8 = true,
 101                 .lower_pack_snorm_2x16 = true,
 102                 .lower_pack_unorm_4x8 = true,
 103                 .lower_pack_unorm_2x16 = true,
 104                 .lower_unpack_half_2x16 = true,
 105                 .lower_unpack_snorm_4x8 = true,
 106                 .lower_unpack_snorm_2x16 = true,
 107                 .lower_unpack_unorm_4x8 = true,
 108                 .lower_unpack_unorm_2x16 = true,
 109                 .lower_pack_split = true,
 110                 .use_interpolated_input_intrinsics = true,
 111                 .lower_rotate = true,
 112                 .vectorize_io = true,
 113                 .lower_to_scalar = true,
 114                 .has_imul24 = true,
 115                 .max_unroll_iterations = 32,
 116 };
 117
 118 const nir_shader_compiler_options *
 119 ir3_get_compiler_options(struct ir3_compiler *compiler)
 120 {
 121         if (compiler->gpu_id >= 600)
 122                 return &options_a6xx;
 123         return &options;
 124 }
 125
 126 #define OPT(nir, pass, ...) ({                             \
 127    bool this_progress = false;                             \
 128    NIR_PASS(this_progress, nir, pass, ##__VA_ARGS__);      \
 129    this_progress;                                          \
 130 })
 131
 132 #define OPT_V(nir, pass, ...) NIR_PASS_V(nir, pass, ##__VA_ARGS__)
 133
 134 static void
 135 ir3_optimize_loop(nir_shader *s)
 136 {
 137         bool progress;
 138         unsigned lower_flrp =
 139                 (s->options->lower_flrp16 ? 16 : 0) |
 140                 (s->options->lower_flrp32 ? 32 : 0) |
 141                 (s->options->lower_flrp64 ? 64 : 0);
 142
 143         do {
 144                 progress = false;
 145
 146                 OPT_V(s, nir_lower_vars_to_ssa);
 147                 progress |= OPT(s, nir_opt_copy_prop_vars);
 148                 progress |= OPT(s, nir_opt_dead_write_vars);
 149                 progress |= OPT(s, nir_lower_alu_to_scalar, NULL, NULL);
 150                 progress |= OPT(s, nir_lower_phis_to_scalar);
 151
 152                 progress |= OPT(s, nir_copy_prop);
 153                 progress |= OPT(s, nir_opt_dce);
 154                 progress |= OPT(s, nir_opt_cse);
 155                 static int gcm = -1;
 156                 if (gcm == -1)
 157                         gcm = env_var_as_unsigned("GCM", 0);
 158                 if (gcm == 1)
 159                         progress |= OPT(s, nir_opt_gcm, true);
 160                 else if (gcm == 2)
 161                         progress |= OPT(s, nir_opt_gcm, false);
 162                 progress |= OPT(s, nir_opt_peephole_select, 16, true, true);
 163                 progress |= OPT(s, nir_opt_intrinsics);
 164                 progress |= OPT(s, nir_opt_algebraic);
 165                 progress |= OPT(s, nir_lower_alu);
 166                 progress |= OPT(s, nir_lower_pack);
 167                 progress |= OPT(s, nir_opt_constant_folding);
 168
 169                 if (lower_flrp != 0) {
 170                         if (OPT(s, nir_lower_flrp,
 171                                         lower_flrp,
 172                                         false /* always_precise */,
 173                                         s->options->lower_ffma)) {
 174                                 OPT(s, nir_opt_constant_folding);
 175                                 progress = true;
 176                         }
 177
 178                         /* Nothing should rematerialize any flrps, so we only
 179                          * need to do this lowering once.
 180                          */
 181                         lower_flrp = 0;
 182                 }
 183
 184                 progress |= OPT(s, nir_opt_dead_cf);
 185                 if (OPT(s, nir_opt_trivial_continues)) {
 186                         progress |= true;
 187                         /* If nir_opt_trivial_continues makes progress, then we need to clean
 188                          * things up if we want any hope of nir_opt_if or nir_opt_loop_unroll
 189                          * to make progress.
 190                          */
 191                         OPT(s, nir_copy_prop);
 192                         OPT(s, nir_opt_dce);
 193                 }
 194                 progress |= OPT(s, nir_opt_if, false);
 195                 progress |= OPT(s, nir_opt_remove_phis);
 196                 progress |= OPT(s, nir_opt_undef);
 197         } while (progress);
 198 }
 199
 200 static bool
 201 should_split_wrmask(const nir_instr *instr, const void *data)
 202 {
 203         nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
 204
 205         switch (intr->intrinsic) {
 206         case nir_intrinsic_store_ssbo:
 207         case nir_intrinsic_store_shared:
 208         case nir_intrinsic_store_global:
 209                 return true;
 210         default:
 211                 return false;
 212         }
 213 }
 214
 215 void
 216 ir3_optimize_nir(struct ir3_shader *shader, nir_shader *s)
 217 {
 218         struct nir_lower_tex_options tex_options = {
 219                         .lower_rect = 0,
 220                         .lower_tg4_offsets = true,
 221         };
 222
 223         if (shader->compiler->gpu_id >= 400) {
 224                 /* a4xx seems to have *no* sam.p */
 225                 tex_options.lower_txp = ~0;  /* lower all txp */
 226         } else {
 227                 /* a3xx just needs to avoid sam.p for 3d tex */
 228                 tex_options.lower_txp = (1 << GLSL_SAMPLER_DIM_3D);
 229         }
 230
 231         if (ir3_shader_debug & IR3_DBG_DISASM) {
 232                 debug_printf("----------------------\n");
 233                 nir_print_shader(s, stdout);
 234                 debug_printf("----------------------\n");
 235         }
 236
 237         OPT_V(s, nir_lower_regs_to_ssa);
 238         OPT_V(s, nir_lower_wrmasks, should_split_wrmask, s);
 239
 240         OPT_V(s, ir3_nir_apply_trig_workarounds);
 241
 242         if (shader->type == MESA_SHADER_FRAGMENT)
 243                 OPT_V(s, nir_lower_fb_read);
 244
 245         OPT_V(s, nir_lower_tex, &tex_options);
 246         OPT_V(s, nir_lower_load_const_to_scalar);
 247         if (shader->compiler->gpu_id < 500)
 248                 OPT_V(s, ir3_nir_lower_tg4_to_tex);
 249
 250         ir3_optimize_loop(s);
 251
 252         /* do idiv lowering after first opt loop to get a chance to propagate
 253          * constants for divide by immed power-of-two:
 254          */
 255         const bool idiv_progress = OPT(s, nir_lower_idiv, nir_lower_idiv_fast);
 256
 257         if (idiv_progress)
 258                 ir3_optimize_loop(s);
 259
 260         OPT_V(s, nir_remove_dead_variables, nir_var_function_temp, NULL);
 261
 262         if (ir3_shader_debug & IR3_DBG_DISASM) {
 263                 debug_printf("----------------------\n");
 264                 nir_print_shader(s, stdout);
 265                 debug_printf("----------------------\n");
 266         }
 267
 268         nir_sweep(s);
 269 }
 270
 271 void
 272 ir3_nir_lower_variant(struct ir3_shader_variant *so, nir_shader *s)
 273 {
 274         if (ir3_shader_debug & IR3_DBG_DISASM) {
 275                 debug_printf("----------------------\n");
 276                 nir_print_shader(s, stdout);
 277                 debug_printf("----------------------\n");
 278         }
 279
 280         bool progress = false;
 281
 282         if (so->key.has_gs || so->key.tessellation) {
 283                 switch (so->shader->type) {
 284                 case MESA_SHADER_VERTEX:
 285                         NIR_PASS_V(s, ir3_nir_lower_to_explicit_output, so, so->key.tessellation);
 286                         progress = true;
 287                         break;
 288                 case MESA_SHADER_TESS_CTRL:
 289                         NIR_PASS_V(s, ir3_nir_lower_tess_ctrl, so, so->key.tessellation);
 290                         NIR_PASS_V(s, ir3_nir_lower_to_explicit_input);
 291                         progress = true;
 292                         break;
 293                 case MESA_SHADER_TESS_EVAL:
 294                         NIR_PASS_V(s, ir3_nir_lower_tess_eval, so->key.tessellation);
 295                         if (so->key.has_gs)
 296                                 NIR_PASS_V(s, ir3_nir_lower_to_explicit_output, so, so->key.tessellation);
 297                         progress = true;
 298                         break;
 299                 case MESA_SHADER_GEOMETRY:
 300                         NIR_PASS_V(s, ir3_nir_lower_to_explicit_input);
 301                         progress = true;
 302                         break;
 303                 default:
 304                         break;
 305                 }
 306         }
 307
 308         if (s->info.stage == MESA_SHADER_VERTEX) {
 309                 if (so->key.ucp_enables)
 310                         progress |= OPT(s, nir_lower_clip_vs, so->key.ucp_enables, false, false, NULL);
 311                 if (so->key.vclamp_color)
 312                         progress |= OPT(s, nir_lower_clamp_color_outputs);
 313         } else if (s->info.stage == MESA_SHADER_FRAGMENT) {
 314                 if (so->key.ucp_enables)
 315                         progress |= OPT(s, nir_lower_clip_fs, so->key.ucp_enables, false);
 316                 if (so->key.fclamp_color)
 317                         progress |= OPT(s, nir_lower_clamp_color_outputs);
 318         }
 319         if (so->key.color_two_side) {
 320                 OPT_V(s, nir_lower_two_sided_color);
 321                 progress = true;
 322         }
 323
 324         struct nir_lower_tex_options tex_options = { };
 325
 326         switch (so->shader->type) {
 327         case MESA_SHADER_FRAGMENT:
 328                 tex_options.saturate_s = so->key.fsaturate_s;
 329                 tex_options.saturate_t = so->key.fsaturate_t;
 330                 tex_options.saturate_r = so->key.fsaturate_r;
 331                 break;
 332         case MESA_SHADER_VERTEX:
 333                 tex_options.saturate_s = so->key.vsaturate_s;
 334                 tex_options.saturate_t = so->key.vsaturate_t;
 335                 tex_options.saturate_r = so->key.vsaturate_r;
 336                 break;
 337         default:
 338                 /* TODO */
 339                 break;
 340         }
 341
 342         if (tex_options.saturate_s || tex_options.saturate_t ||
 343                 tex_options.saturate_r) {
 344                 progress |= OPT(s, nir_lower_tex, &tex_options);
 345         }
 346
 347         if (!so->binning_pass)
 348                 OPT_V(s, ir3_nir_analyze_ubo_ranges, so);
 349
 350         progress |= OPT(s, ir3_nir_lower_ubo_loads, so);
 351
 352         /* UBO offset lowering has to come after we've decided what will
 353          * be left as load_ubo
 354          */
 355         OPT_V(s, ir3_nir_lower_io_offsets, so->shader->compiler->gpu_id);
 356
 357         if (progress)
 358                 ir3_optimize_loop(s);
 359
 360         /* Do late algebraic optimization to turn add(a, neg(b)) back into
 361         * subs, then the mandatory cleanup after algebraic.  Note that it may
 362         * produce fnegs, and if so then we need to keep running to squash
 363         * fneg(fneg(a)).
 364         */
 365         bool more_late_algebraic = true;
 366         while (more_late_algebraic) {
 367                 more_late_algebraic = OPT(s, nir_opt_algebraic_late);
 368                 OPT_V(s, nir_opt_constant_folding);
 369                 OPT_V(s, nir_copy_prop);
 370                 OPT_V(s, nir_opt_dce);
 371                 OPT_V(s, nir_opt_cse);
 372         }
 373
 374         OPT_V(s, nir_opt_sink, nir_move_const_undef);
 375
 376         if (ir3_shader_debug & IR3_DBG_DISASM) {
 377                 debug_printf("----------------------\n");
 378                 nir_print_shader(s, stdout);
 379                 debug_printf("----------------------\n");
 380         }
 381
 382         nir_sweep(s);
 383
 384         /* Binning pass variants re-use  the const_state of the corresponding
 385          * draw pass shader, so that same const emit can be re-used for both
 386          * passes:
 387          */
 388         if (!so->binning_pass)
 389                 ir3_setup_const_state(s, so, ir3_const_state(so));
 390 }
 391
 392 static void
 393 ir3_nir_scan_driver_consts(nir_shader *shader,
 394                 struct ir3_const_state *layout)
 395 {
 396         nir_foreach_function (function, shader) {
 397                 if (!function->impl)
 398                         continue;
 399
 400                 nir_foreach_block (block, function->impl) {
 401                         nir_foreach_instr (instr, block) {
 402                                 if (instr->type != nir_instr_type_intrinsic)
 403                                         continue;
 404
 405                                 nir_intrinsic_instr *intr =
 406                                         nir_instr_as_intrinsic(instr);
 407                                 unsigned idx;
 408
 409                                 switch (intr->intrinsic) {
 410                                 case nir_intrinsic_get_buffer_size:
 411                                         idx = nir_src_as_uint(intr->src[0]);
 412                                         if (layout->ssbo_size.mask & (1 << idx))
 413                                                 break;
 414                                         layout->ssbo_size.mask |= (1 << idx);
 415                                         layout->ssbo_size.off[idx] =
 416                                                 layout->ssbo_size.count;
 417                                         layout->ssbo_size.count += 1; /* one const per */
 418                                         break;
 419                                 case nir_intrinsic_image_atomic_add:
 420                                 case nir_intrinsic_image_atomic_imin:
 421                                 case nir_intrinsic_image_atomic_umin:
 422                                 case nir_intrinsic_image_atomic_imax:
 423                                 case nir_intrinsic_image_atomic_umax:
 424                                 case nir_intrinsic_image_atomic_and:
 425                                 case nir_intrinsic_image_atomic_or:
 426                                 case nir_intrinsic_image_atomic_xor:
 427                                 case nir_intrinsic_image_atomic_exchange:
 428                                 case nir_intrinsic_image_atomic_comp_swap:
 429                                 case nir_intrinsic_image_store:
 430                                 case nir_intrinsic_image_size:
 431                                         idx = nir_src_as_uint(intr->src[0]);
 432                                         if (layout->image_dims.mask & (1 << idx))
 433                                                 break;
 434                                         layout->image_dims.mask |= (1 << idx);
 435                                         layout->image_dims.off[idx] =
 436                                                 layout->image_dims.count;
 437                                         layout->image_dims.count += 3; /* three const per */
 438                                         break;
 439                                 case nir_intrinsic_load_base_vertex:
 440                                 case nir_intrinsic_load_first_vertex:
 441                                         layout->num_driver_params =
 442                                                 MAX2(layout->num_driver_params, IR3_DP_VTXID_BASE + 1);
 443                                         break;
 444                                 case nir_intrinsic_load_base_instance:
 445                                         layout->num_driver_params =
 446                                                 MAX2(layout->num_driver_params, IR3_DP_INSTID_BASE + 1);
 447                                         break;
 448                                 case nir_intrinsic_load_user_clip_plane:
 449                                         layout->num_driver_params =
 450                                                 MAX2(layout->num_driver_params, IR3_DP_UCP7_W + 1);
 451                                         break;
 452                                 case nir_intrinsic_load_num_work_groups:
 453                                         layout->num_driver_params =
 454                                                 MAX2(layout->num_driver_params, IR3_DP_NUM_WORK_GROUPS_Z + 1);
 455                                         break;
 456                                 case nir_intrinsic_load_local_group_size:
 457                                         layout->num_driver_params =
 458                                                 MAX2(layout->num_driver_params, IR3_DP_LOCAL_GROUP_SIZE_Z + 1);
 459                                         break;
 460                                 default:
 461                                         break;
 462                                 }
 463                         }
 464                 }
 465         }
 466 }
 467
 468 /* Sets up the variant-dependent constant state for the ir3_shader.  Note
 469  * that it is also used from ir3_nir_analyze_ubo_ranges() to figure out the
 470  * maximum number of driver params that would eventually be used, to leave
 471  * space for this function to allocate the driver params.
 472  */
 473 void
 474 ir3_setup_const_state(nir_shader *nir, struct ir3_shader_variant *v,
 475                 struct ir3_const_state *const_state)
 476 {
 477         struct ir3_compiler *compiler = v->shader->compiler;
 478
 479         memset(&const_state->offsets, ~0, sizeof(const_state->offsets));
 480
 481         ir3_nir_scan_driver_consts(nir, const_state);
 482
 483         if ((compiler->gpu_id < 500) &&
 484                         (v->shader->stream_output.num_outputs > 0)) {
 485                 const_state->num_driver_params =
 486                         MAX2(const_state->num_driver_params, IR3_DP_VTXCNT_MAX + 1);
 487         }
 488
 489         const_state->num_ubos = nir->info.num_ubos;
 490
 491         /* num_driver_params is scalar, align to vec4: */
 492         const_state->num_driver_params = align(const_state->num_driver_params, 4);
 493
 494         debug_assert((const_state->ubo_state.size % 16) == 0);
 495         unsigned constoff = const_state->ubo_state.size / 16;
 496         unsigned ptrsz = ir3_pointer_size(compiler);
 497
 498         if (const_state->num_ubos > 0) {
 499                 const_state->offsets.ubo = constoff;
 500                 constoff += align(const_state->num_ubos * ptrsz, 4) / 4;
 501         }
 502
 503         if (const_state->ssbo_size.count > 0) {
 504                 unsigned cnt = const_state->ssbo_size.count;
 505                 const_state->offsets.ssbo_sizes = constoff;
 506                 constoff += align(cnt, 4) / 4;
 507         }
 508
 509         if (const_state->image_dims.count > 0) {
 510                 unsigned cnt = const_state->image_dims.count;
 511                 const_state->offsets.image_dims = constoff;
 512                 constoff += align(cnt, 4) / 4;
 513         }
 514
 515         if (const_state->num_driver_params > 0)
 516                 const_state->offsets.driver_param = constoff;
 517         constoff += const_state->num_driver_params / 4;
 518
 519         if ((v->type == MESA_SHADER_VERTEX) &&
 520                         (compiler->gpu_id < 500) &&
 521                         v->shader->stream_output.num_outputs > 0) {
 522                 const_state->offsets.tfbo = constoff;
 523                 constoff += align(IR3_MAX_SO_BUFFERS * ptrsz, 4) / 4;
 524         }
 525
 526         switch (v->type) {
 527         case MESA_SHADER_VERTEX:
 528                 const_state->offsets.primitive_param = constoff;
 529                 constoff += 1;
 530                 break;
 531         case MESA_SHADER_TESS_CTRL:
 532         case MESA_SHADER_TESS_EVAL:
 533                 constoff = align(constoff - 1, 4) + 3;
 534                 const_state->offsets.primitive_param = constoff;
 535                 const_state->offsets.primitive_map = constoff + 5;
 536                 constoff += 5 + DIV_ROUND_UP(nir->num_inputs, 4);
 537                 break;
 538         case MESA_SHADER_GEOMETRY:
 539                 const_state->offsets.primitive_param = constoff;
 540                 const_state->offsets.primitive_map = constoff + 1;
 541                 constoff += 1 + DIV_ROUND_UP(nir->num_inputs, 4);
 542                 break;
 543         default:
 544                 break;
 545         }
 546
 547         const_state->offsets.immediate = constoff;
 548
 549         assert(constoff <= compiler->max_const);
 550 }