2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
28 #include "util/debug.h"
29 #include "util/u_math.h"
32 #include "ir3_compiler.h"
33 #include "ir3_shader.h"
35 static void ir3_setup_const_state(struct ir3_shader
*shader
, nir_shader
*nir
);
37 static const nir_shader_compiler_options options
= {
48 .lower_uadd_carry
= true,
49 .lower_usub_borrow
= true,
50 .lower_mul_high
= true,
51 .lower_mul_2x32_64
= true,
53 .vertex_id_zero_based
= true,
54 .lower_extract_byte
= true,
55 .lower_extract_word
= true,
56 .lower_all_io_to_elements
= true,
57 .lower_helper_invocation
= true,
58 .lower_bitfield_insert_to_shifts
= true,
59 .lower_bitfield_extract_to_shifts
= true,
60 .lower_pack_half_2x16
= true,
61 .lower_pack_snorm_4x8
= true,
62 .lower_pack_snorm_2x16
= true,
63 .lower_pack_unorm_4x8
= true,
64 .lower_pack_unorm_2x16
= true,
65 .lower_unpack_half_2x16
= true,
66 .lower_unpack_snorm_4x8
= true,
67 .lower_unpack_snorm_2x16
= true,
68 .lower_unpack_unorm_4x8
= true,
69 .lower_unpack_unorm_2x16
= true,
70 .lower_pack_split
= true,
71 .use_interpolated_input_intrinsics
= true,
73 .lower_to_scalar
= true,
77 /* we don't want to lower vertex_id to _zero_based on newer gpus: */
78 static const nir_shader_compiler_options options_a6xx
= {
89 .lower_uadd_carry
= true,
90 .lower_usub_borrow
= true,
91 .lower_mul_high
= true,
92 .lower_mul_2x32_64
= true,
94 .vertex_id_zero_based
= false,
95 .lower_extract_byte
= true,
96 .lower_extract_word
= true,
97 .lower_all_io_to_elements
= true,
98 .lower_helper_invocation
= true,
99 .lower_bitfield_insert_to_shifts
= true,
100 .lower_bitfield_extract_to_shifts
= true,
101 .lower_pack_half_2x16
= true,
102 .lower_pack_snorm_4x8
= true,
103 .lower_pack_snorm_2x16
= true,
104 .lower_pack_unorm_4x8
= true,
105 .lower_pack_unorm_2x16
= true,
106 .lower_unpack_half_2x16
= true,
107 .lower_unpack_snorm_4x8
= true,
108 .lower_unpack_snorm_2x16
= true,
109 .lower_unpack_unorm_4x8
= true,
110 .lower_unpack_unorm_2x16
= true,
111 .lower_pack_split
= true,
112 .use_interpolated_input_intrinsics
= true,
113 .lower_rotate
= true,
114 .vectorize_io
= true,
115 .lower_to_scalar
= true,
117 .max_unroll_iterations
= 32,
120 const nir_shader_compiler_options
*
121 ir3_get_compiler_options(struct ir3_compiler
*compiler
)
123 if (compiler
->gpu_id
>= 600)
124 return &options_a6xx
;
128 /* for given shader key, are any steps handled in nir? */
130 ir3_key_lowers_nir(const struct ir3_shader_key
*key
)
132 return key
->fsaturate_s
| key
->fsaturate_t
| key
->fsaturate_r
|
133 key
->vsaturate_s
| key
->vsaturate_t
| key
->vsaturate_r
|
134 key
->ucp_enables
| key
->color_two_side
|
135 key
->fclamp_color
| key
->vclamp_color
|
136 key
->tessellation
| key
->has_gs
;
139 #define OPT(nir, pass, ...) ({ \
140 bool this_progress = false; \
141 NIR_PASS(this_progress, nir, pass, ##__VA_ARGS__); \
145 #define OPT_V(nir, pass, ...) NIR_PASS_V(nir, pass, ##__VA_ARGS__)
148 ir3_optimize_loop(nir_shader
*s
)
151 unsigned lower_flrp
=
152 (s
->options
->lower_flrp16
? 16 : 0) |
153 (s
->options
->lower_flrp32
? 32 : 0) |
154 (s
->options
->lower_flrp64
? 64 : 0);
159 OPT_V(s
, nir_lower_vars_to_ssa
);
160 progress
|= OPT(s
, nir_opt_copy_prop_vars
);
161 progress
|= OPT(s
, nir_opt_dead_write_vars
);
162 progress
|= OPT(s
, nir_lower_alu_to_scalar
, NULL
, NULL
);
163 progress
|= OPT(s
, nir_lower_phis_to_scalar
);
165 progress
|= OPT(s
, nir_copy_prop
);
166 progress
|= OPT(s
, nir_opt_dce
);
167 progress
|= OPT(s
, nir_opt_cse
);
170 gcm
= env_var_as_unsigned("GCM", 0);
172 progress
|= OPT(s
, nir_opt_gcm
, true);
174 progress
|= OPT(s
, nir_opt_gcm
, false);
175 progress
|= OPT(s
, nir_opt_peephole_select
, 16, true, true);
176 progress
|= OPT(s
, nir_opt_intrinsics
);
177 progress
|= OPT(s
, nir_opt_algebraic
);
178 progress
|= OPT(s
, nir_lower_alu
);
179 progress
|= OPT(s
, nir_lower_pack
);
180 progress
|= OPT(s
, nir_opt_constant_folding
);
182 if (lower_flrp
!= 0) {
183 if (OPT(s
, nir_lower_flrp
,
185 false /* always_precise */,
186 s
->options
->lower_ffma
)) {
187 OPT(s
, nir_opt_constant_folding
);
191 /* Nothing should rematerialize any flrps, so we only
192 * need to do this lowering once.
197 progress
|= OPT(s
, nir_opt_dead_cf
);
198 if (OPT(s
, nir_opt_trivial_continues
)) {
200 /* If nir_opt_trivial_continues makes progress, then we need to clean
201 * things up if we want any hope of nir_opt_if or nir_opt_loop_unroll
204 OPT(s
, nir_copy_prop
);
207 progress
|= OPT(s
, nir_opt_if
, false);
208 progress
|= OPT(s
, nir_opt_remove_phis
);
209 progress
|= OPT(s
, nir_opt_undef
);
214 ir3_optimize_nir(struct ir3_shader
*shader
, nir_shader
*s
,
215 const struct ir3_shader_key
*key
)
217 struct nir_lower_tex_options tex_options
= {
219 .lower_tg4_offsets
= true,
222 if (key
&& (key
->has_gs
|| key
->tessellation
)) {
223 switch (shader
->type
) {
224 case MESA_SHADER_VERTEX
:
225 NIR_PASS_V(s
, ir3_nir_lower_to_explicit_output
, shader
, key
->tessellation
);
227 case MESA_SHADER_TESS_CTRL
:
228 NIR_PASS_V(s
, ir3_nir_lower_tess_ctrl
, shader
, key
->tessellation
);
230 case MESA_SHADER_TESS_EVAL
:
231 NIR_PASS_V(s
, ir3_nir_lower_tess_eval
, key
->tessellation
);
233 NIR_PASS_V(s
, ir3_nir_lower_to_explicit_output
, shader
, key
->tessellation
);
235 case MESA_SHADER_GEOMETRY
:
236 NIR_PASS_V(s
, ir3_nir_lower_gs
, shader
);
244 switch (shader
->type
) {
245 case MESA_SHADER_FRAGMENT
:
246 tex_options
.saturate_s
= key
->fsaturate_s
;
247 tex_options
.saturate_t
= key
->fsaturate_t
;
248 tex_options
.saturate_r
= key
->fsaturate_r
;
250 case MESA_SHADER_VERTEX
:
251 tex_options
.saturate_s
= key
->vsaturate_s
;
252 tex_options
.saturate_t
= key
->vsaturate_t
;
253 tex_options
.saturate_r
= key
->vsaturate_r
;
261 if (shader
->compiler
->gpu_id
>= 400) {
262 /* a4xx seems to have *no* sam.p */
263 tex_options
.lower_txp
= ~0; /* lower all txp */
265 /* a3xx just needs to avoid sam.p for 3d tex */
266 tex_options
.lower_txp
= (1 << GLSL_SAMPLER_DIM_3D
);
269 if (ir3_shader_debug
& IR3_DBG_DISASM
) {
270 debug_printf("----------------------\n");
271 nir_print_shader(s
, stdout
);
272 debug_printf("----------------------\n");
275 OPT_V(s
, nir_lower_regs_to_ssa
);
276 OPT_V(s
, ir3_nir_lower_io_offsets
);
279 if (s
->info
.stage
== MESA_SHADER_VERTEX
) {
280 OPT_V(s
, nir_lower_clip_vs
, key
->ucp_enables
, false, false, NULL
);
281 if (key
->vclamp_color
)
282 OPT_V(s
, nir_lower_clamp_color_outputs
);
283 } else if (s
->info
.stage
== MESA_SHADER_FRAGMENT
) {
284 OPT_V(s
, nir_lower_clip_fs
, key
->ucp_enables
, false);
285 if (key
->fclamp_color
)
286 OPT_V(s
, nir_lower_clamp_color_outputs
);
288 if (key
->color_two_side
) {
289 OPT_V(s
, nir_lower_two_sided_color
);
292 /* only want to do this the first time (when key is null)
293 * and not again on any potential 2nd variant lowering pass:
295 OPT_V(s
, ir3_nir_apply_trig_workarounds
);
297 /* This wouldn't hurt to run multiple times, but there is
300 if (shader
->type
== MESA_SHADER_FRAGMENT
)
301 OPT_V(s
, nir_lower_fb_read
);
304 OPT_V(s
, nir_lower_tex
, &tex_options
);
305 OPT_V(s
, nir_lower_load_const_to_scalar
);
306 if (shader
->compiler
->gpu_id
< 500)
307 OPT_V(s
, ir3_nir_lower_tg4_to_tex
);
309 ir3_optimize_loop(s
);
311 /* do ubo load and idiv lowering after first opt loop to get a chance to
312 * propagate constants for divide by immed power-of-two and constant ubo
315 * NOTE that UBO analysis pass should only be done once, before variants
317 const bool ubo_progress
= !key
&& OPT(s
, ir3_nir_analyze_ubo_ranges
, shader
);
318 const bool idiv_progress
= OPT(s
, nir_lower_idiv
, nir_lower_idiv_fast
);
319 if (ubo_progress
|| idiv_progress
)
320 ir3_optimize_loop(s
);
322 /* Do late algebraic optimization to turn add(a, neg(b)) back into
323 * subs, then the mandatory cleanup after algebraic. Note that it may
324 * produce fnegs, and if so then we need to keep running to squash
327 bool more_late_algebraic
= true;
328 while (more_late_algebraic
) {
329 more_late_algebraic
= OPT(s
, nir_opt_algebraic_late
);
330 OPT_V(s
, nir_opt_constant_folding
);
331 OPT_V(s
, nir_copy_prop
);
332 OPT_V(s
, nir_opt_dce
);
333 OPT_V(s
, nir_opt_cse
);
336 OPT_V(s
, nir_remove_dead_variables
, nir_var_function_temp
);
338 OPT_V(s
, nir_opt_sink
, nir_move_const_undef
);
340 if (ir3_shader_debug
& IR3_DBG_DISASM
) {
341 debug_printf("----------------------\n");
342 nir_print_shader(s
, stdout
);
343 debug_printf("----------------------\n");
348 /* The first time thru, when not creating variant, do the one-time
349 * const_state layout setup. This should be done after ubo range
353 ir3_setup_const_state(shader
, s
);
358 ir3_nir_scan_driver_consts(nir_shader
*shader
,
359 struct ir3_const_state
*layout
)
361 nir_foreach_function (function
, shader
) {
365 nir_foreach_block (block
, function
->impl
) {
366 nir_foreach_instr (instr
, block
) {
367 if (instr
->type
!= nir_instr_type_intrinsic
)
370 nir_intrinsic_instr
*intr
=
371 nir_instr_as_intrinsic(instr
);
374 switch (intr
->intrinsic
) {
375 case nir_intrinsic_get_buffer_size
:
376 idx
= nir_src_as_uint(intr
->src
[0]);
377 if (layout
->ssbo_size
.mask
& (1 << idx
))
379 layout
->ssbo_size
.mask
|= (1 << idx
);
380 layout
->ssbo_size
.off
[idx
] =
381 layout
->ssbo_size
.count
;
382 layout
->ssbo_size
.count
+= 1; /* one const per */
384 case nir_intrinsic_image_atomic_add
:
385 case nir_intrinsic_image_atomic_imin
:
386 case nir_intrinsic_image_atomic_umin
:
387 case nir_intrinsic_image_atomic_imax
:
388 case nir_intrinsic_image_atomic_umax
:
389 case nir_intrinsic_image_atomic_and
:
390 case nir_intrinsic_image_atomic_or
:
391 case nir_intrinsic_image_atomic_xor
:
392 case nir_intrinsic_image_atomic_exchange
:
393 case nir_intrinsic_image_atomic_comp_swap
:
394 case nir_intrinsic_image_store
:
395 case nir_intrinsic_image_size
:
396 idx
= nir_src_as_uint(intr
->src
[0]);
397 if (layout
->image_dims
.mask
& (1 << idx
))
399 layout
->image_dims
.mask
|= (1 << idx
);
400 layout
->image_dims
.off
[idx
] =
401 layout
->image_dims
.count
;
402 layout
->image_dims
.count
+= 3; /* three const per */
404 case nir_intrinsic_load_ubo
:
405 if (nir_src_is_const(intr
->src
[0])) {
406 layout
->num_ubos
= MAX2(layout
->num_ubos
,
407 nir_src_as_uint(intr
->src
[0]) + 1);
409 layout
->num_ubos
= shader
->info
.num_ubos
;
412 case nir_intrinsic_load_base_vertex
:
413 case nir_intrinsic_load_first_vertex
:
414 layout
->num_driver_params
=
415 MAX2(layout
->num_driver_params
, IR3_DP_VTXID_BASE
+ 1);
417 case nir_intrinsic_load_base_instance
:
418 layout
->num_driver_params
=
419 MAX2(layout
->num_driver_params
, IR3_DP_INSTID_BASE
+ 1);
421 case nir_intrinsic_load_user_clip_plane
:
422 layout
->num_driver_params
=
423 MAX2(layout
->num_driver_params
, IR3_DP_UCP7_W
+ 1);
425 case nir_intrinsic_load_num_work_groups
:
426 layout
->num_driver_params
=
427 MAX2(layout
->num_driver_params
, IR3_DP_NUM_WORK_GROUPS_Z
+ 1);
429 case nir_intrinsic_load_local_group_size
:
430 layout
->num_driver_params
=
431 MAX2(layout
->num_driver_params
, IR3_DP_LOCAL_GROUP_SIZE_Z
+ 1);
442 ir3_setup_const_state(struct ir3_shader
*shader
, nir_shader
*nir
)
444 struct ir3_compiler
*compiler
= shader
->compiler
;
445 struct ir3_const_state
*const_state
= &shader
->const_state
;
447 memset(&const_state
->offsets
, ~0, sizeof(const_state
->offsets
));
449 ir3_nir_scan_driver_consts(nir
, const_state
);
451 if ((compiler
->gpu_id
< 500) &&
452 (shader
->stream_output
.num_outputs
> 0)) {
453 const_state
->num_driver_params
=
454 MAX2(const_state
->num_driver_params
, IR3_DP_VTXCNT_MAX
+ 1);
457 /* num_driver_params is scalar, align to vec4: */
458 const_state
->num_driver_params
= align(const_state
->num_driver_params
, 4);
460 debug_assert((shader
->ubo_state
.size
% 16) == 0);
461 unsigned constoff
= align(shader
->ubo_state
.size
/ 16, 8);
462 unsigned ptrsz
= ir3_pointer_size(compiler
);
464 if (const_state
->num_ubos
> 0) {
465 const_state
->offsets
.ubo
= constoff
;
466 constoff
+= align(nir
->info
.num_ubos
* ptrsz
, 4) / 4;
469 if (const_state
->ssbo_size
.count
> 0) {
470 unsigned cnt
= const_state
->ssbo_size
.count
;
471 const_state
->offsets
.ssbo_sizes
= constoff
;
472 constoff
+= align(cnt
, 4) / 4;
475 if (const_state
->image_dims
.count
> 0) {
476 unsigned cnt
= const_state
->image_dims
.count
;
477 const_state
->offsets
.image_dims
= constoff
;
478 constoff
+= align(cnt
, 4) / 4;
481 if (const_state
->num_driver_params
> 0)
482 const_state
->offsets
.driver_param
= constoff
;
483 constoff
+= const_state
->num_driver_params
/ 4;
485 if ((shader
->type
== MESA_SHADER_VERTEX
) &&
486 (compiler
->gpu_id
< 500) &&
487 shader
->stream_output
.num_outputs
> 0) {
488 const_state
->offsets
.tfbo
= constoff
;
489 constoff
+= align(IR3_MAX_SO_BUFFERS
* ptrsz
, 4) / 4;
492 switch (shader
->type
) {
493 case MESA_SHADER_VERTEX
:
494 const_state
->offsets
.primitive_param
= constoff
;
497 case MESA_SHADER_TESS_CTRL
:
498 case MESA_SHADER_TESS_EVAL
:
499 constoff
= align(constoff
- 1, 4) + 3;
500 const_state
->offsets
.primitive_param
= constoff
;
501 const_state
->offsets
.primitive_map
= constoff
+ 5;
502 constoff
+= 5 + DIV_ROUND_UP(nir
->num_inputs
, 4);
504 case MESA_SHADER_GEOMETRY
:
505 const_state
->offsets
.primitive_param
= constoff
;
506 const_state
->offsets
.primitive_map
= constoff
+ 1;
507 constoff
+= 1 + DIV_ROUND_UP(nir
->num_inputs
, 4);
513 const_state
->offsets
.immediate
= constoff
;