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freedreno: Move register constant files to src/freedreno.
[mesa.git] / src / freedreno / registers / adreno_pm4.xml.h
1 #ifndef ADRENO_PM4_XML
2 #define ADRENO_PM4_XML
3
4 /* Autogenerated file, DO NOT EDIT manually!
5
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
12 - /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
13 - /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 42463 bytes, from 2018-11-19 13:44:03)
14 - /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14239 bytes, from 2018-12-05 15:25:53)
15 - /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43052 bytes, from 2018-12-21 18:21:34)
16 - /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
17 - /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
18 - /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-12-21 18:21:34)
19 - /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 141895 bytes, from 2018-12-21 18:21:34)
20 - /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
21 - /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
22
23 Copyright (C) 2013-2018 by the following authors:
24 - Rob Clark <robdclark@gmail.com> (robclark)
25 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
26
27 Permission is hereby granted, free of charge, to any person obtaining
28 a copy of this software and associated documentation files (the
29 "Software"), to deal in the Software without restriction, including
30 without limitation the rights to use, copy, modify, merge, publish,
31 distribute, sublicense, and/or sell copies of the Software, and to
32 permit persons to whom the Software is furnished to do so, subject to
33 the following conditions:
34
35 The above copyright notice and this permission notice (including the
36 next paragraph) shall be included in all copies or substantial
37 portions of the Software.
38
39 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
40 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
41 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
42 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
43 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
44 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
45 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48
49 enum vgt_event_type {
50 VS_DEALLOC = 0,
51 PS_DEALLOC = 1,
52 VS_DONE_TS = 2,
53 PS_DONE_TS = 3,
54 CACHE_FLUSH_TS = 4,
55 CONTEXT_DONE = 5,
56 CACHE_FLUSH = 6,
57 HLSQ_FLUSH = 7,
58 VIZQUERY_START = 7,
59 VIZQUERY_END = 8,
60 SC_WAIT_WC = 9,
61 RST_PIX_CNT = 13,
62 RST_VTX_CNT = 14,
63 TILE_FLUSH = 15,
64 STAT_EVENT = 16,
65 CACHE_FLUSH_AND_INV_TS_EVENT = 20,
66 ZPASS_DONE = 21,
67 CACHE_FLUSH_AND_INV_EVENT = 22,
68 PERFCOUNTER_START = 23,
69 PERFCOUNTER_STOP = 24,
70 VS_FETCH_DONE = 27,
71 FACENESS_FLUSH = 28,
72 FLUSH_SO_0 = 17,
73 FLUSH_SO_1 = 18,
74 FLUSH_SO_2 = 19,
75 FLUSH_SO_3 = 20,
76 PC_CCU_INVALIDATE_DEPTH = 24,
77 PC_CCU_INVALIDATE_COLOR = 25,
78 UNK_1C = 28,
79 UNK_1D = 29,
80 BLIT = 30,
81 UNK_25 = 37,
82 LRZ_FLUSH = 38,
83 UNK_2C = 44,
84 UNK_2D = 45,
85 };
86
87 enum pc_di_primtype {
88 DI_PT_NONE = 0,
89 DI_PT_POINTLIST_PSIZE = 1,
90 DI_PT_LINELIST = 2,
91 DI_PT_LINESTRIP = 3,
92 DI_PT_TRILIST = 4,
93 DI_PT_TRIFAN = 5,
94 DI_PT_TRISTRIP = 6,
95 DI_PT_LINELOOP = 7,
96 DI_PT_RECTLIST = 8,
97 DI_PT_POINTLIST = 9,
98 DI_PT_LINE_ADJ = 10,
99 DI_PT_LINESTRIP_ADJ = 11,
100 DI_PT_TRI_ADJ = 12,
101 DI_PT_TRISTRIP_ADJ = 13,
102 };
103
104 enum pc_di_src_sel {
105 DI_SRC_SEL_DMA = 0,
106 DI_SRC_SEL_IMMEDIATE = 1,
107 DI_SRC_SEL_AUTO_INDEX = 2,
108 DI_SRC_SEL_RESERVED = 3,
109 };
110
111 enum pc_di_face_cull_sel {
112 DI_FACE_CULL_NONE = 0,
113 DI_FACE_CULL_FETCH = 1,
114 DI_FACE_BACKFACE_CULL = 2,
115 DI_FACE_FRONTFACE_CULL = 3,
116 };
117
118 enum pc_di_index_size {
119 INDEX_SIZE_IGN = 0,
120 INDEX_SIZE_16_BIT = 0,
121 INDEX_SIZE_32_BIT = 1,
122 INDEX_SIZE_8_BIT = 2,
123 INDEX_SIZE_INVALID = 0,
124 };
125
126 enum pc_di_vis_cull_mode {
127 IGNORE_VISIBILITY = 0,
128 USE_VISIBILITY = 1,
129 };
130
131 enum adreno_pm4_packet_type {
132 CP_TYPE0_PKT = 0,
133 CP_TYPE1_PKT = 0x40000000,
134 CP_TYPE2_PKT = 0x80000000,
135 CP_TYPE3_PKT = 0xc0000000,
136 CP_TYPE4_PKT = 0x40000000,
137 CP_TYPE7_PKT = 0x70000000,
138 };
139
140 enum adreno_pm4_type3_packets {
141 CP_ME_INIT = 72,
142 CP_NOP = 16,
143 CP_PREEMPT_ENABLE = 28,
144 CP_PREEMPT_TOKEN = 30,
145 CP_INDIRECT_BUFFER = 63,
146 CP_INDIRECT_BUFFER_PFD = 55,
147 CP_WAIT_FOR_IDLE = 38,
148 CP_WAIT_REG_MEM = 60,
149 CP_WAIT_REG_EQ = 82,
150 CP_WAIT_REG_GTE = 83,
151 CP_WAIT_UNTIL_READ = 92,
152 CP_WAIT_IB_PFD_COMPLETE = 93,
153 CP_REG_RMW = 33,
154 CP_SET_BIN_DATA = 47,
155 CP_SET_BIN_DATA5 = 47,
156 CP_REG_TO_MEM = 62,
157 CP_MEM_WRITE = 61,
158 CP_MEM_WRITE_CNTR = 79,
159 CP_COND_EXEC = 68,
160 CP_COND_WRITE = 69,
161 CP_COND_WRITE5 = 69,
162 CP_EVENT_WRITE = 70,
163 CP_EVENT_WRITE_SHD = 88,
164 CP_EVENT_WRITE_CFL = 89,
165 CP_EVENT_WRITE_ZPD = 91,
166 CP_RUN_OPENCL = 49,
167 CP_DRAW_INDX = 34,
168 CP_DRAW_INDX_2 = 54,
169 CP_DRAW_INDX_BIN = 52,
170 CP_DRAW_INDX_2_BIN = 53,
171 CP_VIZ_QUERY = 35,
172 CP_SET_STATE = 37,
173 CP_SET_CONSTANT = 45,
174 CP_IM_LOAD = 39,
175 CP_IM_LOAD_IMMEDIATE = 43,
176 CP_LOAD_CONSTANT_CONTEXT = 46,
177 CP_INVALIDATE_STATE = 59,
178 CP_SET_SHADER_BASES = 74,
179 CP_SET_BIN_MASK = 80,
180 CP_SET_BIN_SELECT = 81,
181 CP_CONTEXT_UPDATE = 94,
182 CP_INTERRUPT = 64,
183 CP_IM_STORE = 44,
184 CP_SET_DRAW_INIT_FLAGS = 75,
185 CP_SET_PROTECTED_MODE = 95,
186 CP_BOOTSTRAP_UCODE = 111,
187 CP_LOAD_STATE = 48,
188 CP_LOAD_STATE4 = 48,
189 CP_COND_INDIRECT_BUFFER_PFE = 58,
190 CP_COND_INDIRECT_BUFFER_PFD = 50,
191 CP_INDIRECT_BUFFER_PFE = 63,
192 CP_SET_BIN = 76,
193 CP_TEST_TWO_MEMS = 113,
194 CP_REG_WR_NO_CTXT = 120,
195 CP_RECORD_PFP_TIMESTAMP = 17,
196 CP_SET_SECURE_MODE = 102,
197 CP_WAIT_FOR_ME = 19,
198 CP_SET_DRAW_STATE = 67,
199 CP_DRAW_INDX_OFFSET = 56,
200 CP_DRAW_INDIRECT = 40,
201 CP_DRAW_INDX_INDIRECT = 41,
202 CP_DRAW_AUTO = 36,
203 CP_UNKNOWN_19 = 25,
204 CP_UNKNOWN_1A = 26,
205 CP_UNKNOWN_4E = 78,
206 CP_WIDE_REG_WRITE = 116,
207 CP_SCRATCH_TO_REG = 77,
208 CP_REG_TO_SCRATCH = 74,
209 CP_WAIT_MEM_WRITES = 18,
210 CP_COND_REG_EXEC = 71,
211 CP_MEM_TO_REG = 66,
212 CP_EXEC_CS_INDIRECT = 65,
213 CP_EXEC_CS = 51,
214 CP_PERFCOUNTER_ACTION = 80,
215 CP_SMMU_TABLE_UPDATE = 83,
216 CP_SET_MARKER = 101,
217 CP_SET_PSEUDO_REG = 86,
218 CP_CONTEXT_REG_BUNCH = 92,
219 CP_YIELD_ENABLE = 28,
220 CP_SKIP_IB2_ENABLE_GLOBAL = 29,
221 CP_SKIP_IB2_ENABLE_LOCAL = 35,
222 CP_SET_SUBDRAW_SIZE = 53,
223 CP_SET_VISIBILITY_OVERRIDE = 100,
224 CP_PREEMPT_ENABLE_GLOBAL = 105,
225 CP_PREEMPT_ENABLE_LOCAL = 106,
226 CP_CONTEXT_SWITCH_YIELD = 107,
227 CP_SET_RENDER_MODE = 108,
228 CP_COMPUTE_CHECKPOINT = 110,
229 CP_MEM_TO_MEM = 115,
230 CP_BLIT = 44,
231 CP_REG_TEST = 57,
232 CP_SET_MODE = 99,
233 CP_LOAD_STATE6_GEOM = 50,
234 CP_LOAD_STATE6_FRAG = 52,
235 IN_IB_PREFETCH_END = 23,
236 IN_SUBBLK_PREFETCH = 31,
237 IN_INSTR_PREFETCH = 32,
238 IN_INSTR_MATCH = 71,
239 IN_CONST_PREFETCH = 73,
240 IN_INCR_UPDT_STATE = 85,
241 IN_INCR_UPDT_CONST = 86,
242 IN_INCR_UPDT_INSTR = 87,
243 PKT4 = 4,
244 CP_UNK_A6XX_14 = 20,
245 CP_UNK_A6XX_36 = 54,
246 CP_UNK_A6XX_55 = 85,
247 CP_REG_WRITE = 109,
248 };
249
250 enum adreno_state_block {
251 SB_VERT_TEX = 0,
252 SB_VERT_MIPADDR = 1,
253 SB_FRAG_TEX = 2,
254 SB_FRAG_MIPADDR = 3,
255 SB_VERT_SHADER = 4,
256 SB_GEOM_SHADER = 5,
257 SB_FRAG_SHADER = 6,
258 SB_COMPUTE_SHADER = 7,
259 };
260
261 enum adreno_state_type {
262 ST_SHADER = 0,
263 ST_CONSTANTS = 1,
264 };
265
266 enum adreno_state_src {
267 SS_DIRECT = 0,
268 SS_INVALID_ALL_IC = 2,
269 SS_INVALID_PART_IC = 3,
270 SS_INDIRECT = 4,
271 SS_INDIRECT_TCM = 5,
272 SS_INDIRECT_STM = 6,
273 };
274
275 enum a4xx_state_block {
276 SB4_VS_TEX = 0,
277 SB4_HS_TEX = 1,
278 SB4_DS_TEX = 2,
279 SB4_GS_TEX = 3,
280 SB4_FS_TEX = 4,
281 SB4_CS_TEX = 5,
282 SB4_VS_SHADER = 8,
283 SB4_HS_SHADER = 9,
284 SB4_DS_SHADER = 10,
285 SB4_GS_SHADER = 11,
286 SB4_FS_SHADER = 12,
287 SB4_CS_SHADER = 13,
288 SB4_SSBO = 14,
289 SB4_CS_SSBO = 15,
290 };
291
292 enum a4xx_state_type {
293 ST4_SHADER = 0,
294 ST4_CONSTANTS = 1,
295 };
296
297 enum a4xx_state_src {
298 SS4_DIRECT = 0,
299 SS4_INDIRECT = 2,
300 };
301
302 enum a6xx_state_block {
303 SB6_VS_TEX = 0,
304 SB6_HS_TEX = 1,
305 SB6_DS_TEX = 2,
306 SB6_GS_TEX = 3,
307 SB6_FS_TEX = 4,
308 SB6_CS_TEX = 5,
309 SB6_VS_SHADER = 8,
310 SB6_HS_SHADER = 9,
311 SB6_DS_SHADER = 10,
312 SB6_GS_SHADER = 11,
313 SB6_FS_SHADER = 12,
314 SB6_CS_SHADER = 13,
315 SB6_SSBO = 14,
316 SB6_CS_SSBO = 15,
317 };
318
319 enum a6xx_state_type {
320 ST6_SHADER = 0,
321 ST6_CONSTANTS = 1,
322 };
323
324 enum a6xx_state_src {
325 SS6_DIRECT = 0,
326 SS6_INDIRECT = 2,
327 };
328
329 enum a4xx_index_size {
330 INDEX4_SIZE_8_BIT = 0,
331 INDEX4_SIZE_16_BIT = 1,
332 INDEX4_SIZE_32_BIT = 2,
333 };
334
335 enum cp_cond_function {
336 WRITE_ALWAYS = 0,
337 WRITE_LT = 1,
338 WRITE_LE = 2,
339 WRITE_EQ = 3,
340 WRITE_NE = 4,
341 WRITE_GE = 5,
342 WRITE_GT = 6,
343 };
344
345 enum render_mode_cmd {
346 BYPASS = 1,
347 BINNING = 2,
348 GMEM = 3,
349 BLIT2D = 5,
350 BLIT2DSCALE = 7,
351 END2D = 8,
352 };
353
354 enum cp_blit_cmd {
355 BLIT_OP_FILL = 0,
356 BLIT_OP_COPY = 1,
357 BLIT_OP_SCALE = 3,
358 };
359
360 enum a6xx_render_mode {
361 RM6_BYPASS = 1,
362 RM6_BINNING = 2,
363 RM6_GMEM = 4,
364 RM6_BLIT2D = 5,
365 RM6_RESOLVE = 6,
366 RM6_BLIT2DSCALE = 12,
367 };
368
369 enum pseudo_reg {
370 SMMU_INFO = 0,
371 NON_SECURE_SAVE_ADDR = 1,
372 SECURE_SAVE_ADDR = 2,
373 NON_PRIV_SAVE_ADDR = 3,
374 COUNTER = 4,
375 };
376
377 #define REG_CP_LOAD_STATE_0 0x00000000
378 #define CP_LOAD_STATE_0_DST_OFF__MASK 0x0000ffff
379 #define CP_LOAD_STATE_0_DST_OFF__SHIFT 0
380 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val)
381 {
382 return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK;
383 }
384 #define CP_LOAD_STATE_0_STATE_SRC__MASK 0x00070000
385 #define CP_LOAD_STATE_0_STATE_SRC__SHIFT 16
386 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val)
387 {
388 return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK;
389 }
390 #define CP_LOAD_STATE_0_STATE_BLOCK__MASK 0x00380000
391 #define CP_LOAD_STATE_0_STATE_BLOCK__SHIFT 19
392 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val)
393 {
394 return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK;
395 }
396 #define CP_LOAD_STATE_0_NUM_UNIT__MASK 0xffc00000
397 #define CP_LOAD_STATE_0_NUM_UNIT__SHIFT 22
398 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val)
399 {
400 return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK;
401 }
402
403 #define REG_CP_LOAD_STATE_1 0x00000001
404 #define CP_LOAD_STATE_1_STATE_TYPE__MASK 0x00000003
405 #define CP_LOAD_STATE_1_STATE_TYPE__SHIFT 0
406 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val)
407 {
408 return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK;
409 }
410 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK 0xfffffffc
411 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT 2
412 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)
413 {
414 assert(!(val & 0x3));
415 return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK;
416 }
417
418 #define REG_CP_LOAD_STATE4_0 0x00000000
419 #define CP_LOAD_STATE4_0_DST_OFF__MASK 0x00003fff
420 #define CP_LOAD_STATE4_0_DST_OFF__SHIFT 0
421 static inline uint32_t CP_LOAD_STATE4_0_DST_OFF(uint32_t val)
422 {
423 return ((val) << CP_LOAD_STATE4_0_DST_OFF__SHIFT) & CP_LOAD_STATE4_0_DST_OFF__MASK;
424 }
425 #define CP_LOAD_STATE4_0_STATE_SRC__MASK 0x00030000
426 #define CP_LOAD_STATE4_0_STATE_SRC__SHIFT 16
427 static inline uint32_t CP_LOAD_STATE4_0_STATE_SRC(enum a4xx_state_src val)
428 {
429 return ((val) << CP_LOAD_STATE4_0_STATE_SRC__SHIFT) & CP_LOAD_STATE4_0_STATE_SRC__MASK;
430 }
431 #define CP_LOAD_STATE4_0_STATE_BLOCK__MASK 0x003c0000
432 #define CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT 18
433 static inline uint32_t CP_LOAD_STATE4_0_STATE_BLOCK(enum a4xx_state_block val)
434 {
435 return ((val) << CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE4_0_STATE_BLOCK__MASK;
436 }
437 #define CP_LOAD_STATE4_0_NUM_UNIT__MASK 0xffc00000
438 #define CP_LOAD_STATE4_0_NUM_UNIT__SHIFT 22
439 static inline uint32_t CP_LOAD_STATE4_0_NUM_UNIT(uint32_t val)
440 {
441 return ((val) << CP_LOAD_STATE4_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE4_0_NUM_UNIT__MASK;
442 }
443
444 #define REG_CP_LOAD_STATE4_1 0x00000001
445 #define CP_LOAD_STATE4_1_STATE_TYPE__MASK 0x00000003
446 #define CP_LOAD_STATE4_1_STATE_TYPE__SHIFT 0
447 static inline uint32_t CP_LOAD_STATE4_1_STATE_TYPE(enum a4xx_state_type val)
448 {
449 return ((val) << CP_LOAD_STATE4_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE4_1_STATE_TYPE__MASK;
450 }
451 #define CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK 0xfffffffc
452 #define CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT 2
453 static inline uint32_t CP_LOAD_STATE4_1_EXT_SRC_ADDR(uint32_t val)
454 {
455 assert(!(val & 0x3));
456 return ((val >> 2) << CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK;
457 }
458
459 #define REG_CP_LOAD_STATE4_2 0x00000002
460 #define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK 0xffffffff
461 #define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT 0
462 static inline uint32_t CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(uint32_t val)
463 {
464 return ((val) << CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK;
465 }
466
467 #define REG_CP_LOAD_STATE6_0 0x00000000
468 #define CP_LOAD_STATE6_0_DST_OFF__MASK 0x00003fff
469 #define CP_LOAD_STATE6_0_DST_OFF__SHIFT 0
470 static inline uint32_t CP_LOAD_STATE6_0_DST_OFF(uint32_t val)
471 {
472 return ((val) << CP_LOAD_STATE6_0_DST_OFF__SHIFT) & CP_LOAD_STATE6_0_DST_OFF__MASK;
473 }
474 #define CP_LOAD_STATE6_0_STATE_TYPE__MASK 0x00004000
475 #define CP_LOAD_STATE6_0_STATE_TYPE__SHIFT 14
476 static inline uint32_t CP_LOAD_STATE6_0_STATE_TYPE(enum a6xx_state_type val)
477 {
478 return ((val) << CP_LOAD_STATE6_0_STATE_TYPE__SHIFT) & CP_LOAD_STATE6_0_STATE_TYPE__MASK;
479 }
480 #define CP_LOAD_STATE6_0_STATE_SRC__MASK 0x00030000
481 #define CP_LOAD_STATE6_0_STATE_SRC__SHIFT 16
482 static inline uint32_t CP_LOAD_STATE6_0_STATE_SRC(enum a6xx_state_src val)
483 {
484 return ((val) << CP_LOAD_STATE6_0_STATE_SRC__SHIFT) & CP_LOAD_STATE6_0_STATE_SRC__MASK;
485 }
486 #define CP_LOAD_STATE6_0_STATE_BLOCK__MASK 0x003c0000
487 #define CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT 18
488 static inline uint32_t CP_LOAD_STATE6_0_STATE_BLOCK(enum a6xx_state_block val)
489 {
490 return ((val) << CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE6_0_STATE_BLOCK__MASK;
491 }
492 #define CP_LOAD_STATE6_0_NUM_UNIT__MASK 0xffc00000
493 #define CP_LOAD_STATE6_0_NUM_UNIT__SHIFT 22
494 static inline uint32_t CP_LOAD_STATE6_0_NUM_UNIT(uint32_t val)
495 {
496 return ((val) << CP_LOAD_STATE6_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE6_0_NUM_UNIT__MASK;
497 }
498
499 #define REG_CP_LOAD_STATE6_1 0x00000001
500 #define CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK 0xfffffffc
501 #define CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT 2
502 static inline uint32_t CP_LOAD_STATE6_1_EXT_SRC_ADDR(uint32_t val)
503 {
504 assert(!(val & 0x3));
505 return ((val >> 2) << CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK;
506 }
507
508 #define REG_CP_LOAD_STATE6_2 0x00000002
509 #define CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK 0xffffffff
510 #define CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT 0
511 static inline uint32_t CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(uint32_t val)
512 {
513 return ((val) << CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK;
514 }
515
516 #define REG_CP_DRAW_INDX_0 0x00000000
517 #define CP_DRAW_INDX_0_VIZ_QUERY__MASK 0xffffffff
518 #define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT 0
519 static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val)
520 {
521 return ((val) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK;
522 }
523
524 #define REG_CP_DRAW_INDX_1 0x00000001
525 #define CP_DRAW_INDX_1_PRIM_TYPE__MASK 0x0000003f
526 #define CP_DRAW_INDX_1_PRIM_TYPE__SHIFT 0
527 static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val)
528 {
529 return ((val) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK;
530 }
531 #define CP_DRAW_INDX_1_SOURCE_SELECT__MASK 0x000000c0
532 #define CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT 6
533 static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val)
534 {
535 return ((val) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK;
536 }
537 #define CP_DRAW_INDX_1_VIS_CULL__MASK 0x00000600
538 #define CP_DRAW_INDX_1_VIS_CULL__SHIFT 9
539 static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val)
540 {
541 return ((val) << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK;
542 }
543 #define CP_DRAW_INDX_1_INDEX_SIZE__MASK 0x00000800
544 #define CP_DRAW_INDX_1_INDEX_SIZE__SHIFT 11
545 static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val)
546 {
547 return ((val) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK;
548 }
549 #define CP_DRAW_INDX_1_NOT_EOP 0x00001000
550 #define CP_DRAW_INDX_1_SMALL_INDEX 0x00002000
551 #define CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000
552 #define CP_DRAW_INDX_1_NUM_INSTANCES__MASK 0xff000000
553 #define CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT 24
554 static inline uint32_t CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val)
555 {
556 return ((val) << CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_1_NUM_INSTANCES__MASK;
557 }
558
559 #define REG_CP_DRAW_INDX_2 0x00000002
560 #define CP_DRAW_INDX_2_NUM_INDICES__MASK 0xffffffff
561 #define CP_DRAW_INDX_2_NUM_INDICES__SHIFT 0
562 static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val)
563 {
564 return ((val) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK;
565 }
566
567 #define REG_CP_DRAW_INDX_3 0x00000003
568 #define CP_DRAW_INDX_3_INDX_BASE__MASK 0xffffffff
569 #define CP_DRAW_INDX_3_INDX_BASE__SHIFT 0
570 static inline uint32_t CP_DRAW_INDX_3_INDX_BASE(uint32_t val)
571 {
572 return ((val) << CP_DRAW_INDX_3_INDX_BASE__SHIFT) & CP_DRAW_INDX_3_INDX_BASE__MASK;
573 }
574
575 #define REG_CP_DRAW_INDX_4 0x00000004
576 #define CP_DRAW_INDX_4_INDX_SIZE__MASK 0xffffffff
577 #define CP_DRAW_INDX_4_INDX_SIZE__SHIFT 0
578 static inline uint32_t CP_DRAW_INDX_4_INDX_SIZE(uint32_t val)
579 {
580 return ((val) << CP_DRAW_INDX_4_INDX_SIZE__SHIFT) & CP_DRAW_INDX_4_INDX_SIZE__MASK;
581 }
582
583 #define REG_CP_DRAW_INDX_2_0 0x00000000
584 #define CP_DRAW_INDX_2_0_VIZ_QUERY__MASK 0xffffffff
585 #define CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT 0
586 static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val)
587 {
588 return ((val) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK;
589 }
590
591 #define REG_CP_DRAW_INDX_2_1 0x00000001
592 #define CP_DRAW_INDX_2_1_PRIM_TYPE__MASK 0x0000003f
593 #define CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT 0
594 static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val)
595 {
596 return ((val) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK;
597 }
598 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK 0x000000c0
599 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT 6
600 static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val)
601 {
602 return ((val) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK;
603 }
604 #define CP_DRAW_INDX_2_1_VIS_CULL__MASK 0x00000600
605 #define CP_DRAW_INDX_2_1_VIS_CULL__SHIFT 9
606 static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val)
607 {
608 return ((val) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK;
609 }
610 #define CP_DRAW_INDX_2_1_INDEX_SIZE__MASK 0x00000800
611 #define CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT 11
612 static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val)
613 {
614 return ((val) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK;
615 }
616 #define CP_DRAW_INDX_2_1_NOT_EOP 0x00001000
617 #define CP_DRAW_INDX_2_1_SMALL_INDEX 0x00002000
618 #define CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000
619 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK 0xff000000
620 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT 24
621 static inline uint32_t CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val)
622 {
623 return ((val) << CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK;
624 }
625
626 #define REG_CP_DRAW_INDX_2_2 0x00000002
627 #define CP_DRAW_INDX_2_2_NUM_INDICES__MASK 0xffffffff
628 #define CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT 0
629 static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val)
630 {
631 return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK;
632 }
633
634 #define REG_CP_DRAW_INDX_OFFSET_0 0x00000000
635 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK 0x0000003f
636 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT 0
637 static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val)
638 {
639 return ((val) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK;
640 }
641 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK 0x000000c0
642 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT 6
643 static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val)
644 {
645 return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK;
646 }
647 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK 0x00000300
648 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT 8
649 static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val)
650 {
651 return ((val) << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK;
652 }
653 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK 0x00000c00
654 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT 10
655 static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val)
656 {
657 return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK;
658 }
659 #define CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK 0x01f00000
660 #define CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT 20
661 static inline uint32_t CP_DRAW_INDX_OFFSET_0_TESS_MODE(uint32_t val)
662 {
663 return ((val) << CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT) & CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK;
664 }
665
666 #define REG_CP_DRAW_INDX_OFFSET_1 0x00000001
667 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK 0xffffffff
668 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT 0
669 static inline uint32_t CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val)
670 {
671 return ((val) << CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK;
672 }
673
674 #define REG_CP_DRAW_INDX_OFFSET_2 0x00000002
675 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK 0xffffffff
676 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT 0
677 static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val)
678 {
679 return ((val) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK;
680 }
681
682 #define REG_CP_DRAW_INDX_OFFSET_3 0x00000003
683
684 #define REG_CP_DRAW_INDX_OFFSET_4 0x00000004
685 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK 0xffffffff
686 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT 0
687 static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val)
688 {
689 return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK;
690 }
691
692 #define REG_CP_DRAW_INDX_OFFSET_5 0x00000005
693 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK 0xffffffff
694 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT 0
695 static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val)
696 {
697 return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK;
698 }
699
700 #define REG_A4XX_CP_DRAW_INDIRECT_0 0x00000000
701 #define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK 0x0000003f
702 #define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT 0
703 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)
704 {
705 return ((val) << A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK;
706 }
707 #define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK 0x000000c0
708 #define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT 6
709 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)
710 {
711 return ((val) << A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK;
712 }
713 #define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK 0x00000300
714 #define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT 8
715 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)
716 {
717 return ((val) << A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK;
718 }
719 #define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK 0x00000c00
720 #define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT 10
721 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)
722 {
723 return ((val) << A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK;
724 }
725 #define A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__MASK 0x01f00000
726 #define A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__SHIFT 20
727 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_TESS_MODE(uint32_t val)
728 {
729 return ((val) << A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__MASK;
730 }
731
732 #define REG_A4XX_CP_DRAW_INDIRECT_1 0x00000001
733 #define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK 0xffffffff
734 #define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT 0
735 static inline uint32_t A4XX_CP_DRAW_INDIRECT_1_INDIRECT(uint32_t val)
736 {
737 return ((val) << A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK;
738 }
739
740
741 #define REG_A5XX_CP_DRAW_INDIRECT_2 0x00000002
742 #define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK 0xffffffff
743 #define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT 0
744 static inline uint32_t A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI(uint32_t val)
745 {
746 return ((val) << A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK;
747 }
748
749 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_0 0x00000000
750 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK 0x0000003f
751 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT 0
752 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)
753 {
754 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK;
755 }
756 #define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK 0x000000c0
757 #define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT 6
758 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)
759 {
760 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK;
761 }
762 #define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK 0x00000300
763 #define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT 8
764 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)
765 {
766 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK;
767 }
768 #define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK 0x00000c00
769 #define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT 10
770 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)
771 {
772 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK;
773 }
774 #define A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__MASK 0x01f00000
775 #define A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__SHIFT 20
776 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE(uint32_t val)
777 {
778 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__MASK;
779 }
780
781
782 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_1 0x00000001
783 #define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK 0xffffffff
784 #define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT 0
785 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE(uint32_t val)
786 {
787 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK;
788 }
789
790 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_2 0x00000002
791 #define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK 0xffffffff
792 #define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT 0
793 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE(uint32_t val)
794 {
795 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK;
796 }
797
798 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_3 0x00000003
799 #define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK 0xffffffff
800 #define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT 0
801 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT(uint32_t val)
802 {
803 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK;
804 }
805
806
807 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_1 0x00000001
808 #define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK 0xffffffff
809 #define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT 0
810 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO(uint32_t val)
811 {
812 return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK;
813 }
814
815 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_2 0x00000002
816 #define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK 0xffffffff
817 #define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT 0
818 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI(uint32_t val)
819 {
820 return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK;
821 }
822
823 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_3 0x00000003
824 #define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK 0xffffffff
825 #define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT 0
826 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(uint32_t val)
827 {
828 return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK;
829 }
830
831 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_4 0x00000004
832 #define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK 0xffffffff
833 #define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT 0
834 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO(uint32_t val)
835 {
836 return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK;
837 }
838
839 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_5 0x00000005
840 #define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK 0xffffffff
841 #define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT 0
842 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI(uint32_t val)
843 {
844 return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK;
845 }
846
847 static inline uint32_t REG_CP_SET_DRAW_STATE_(uint32_t i0) { return 0x00000000 + 0x3*i0; }
848
849 static inline uint32_t REG_CP_SET_DRAW_STATE__0(uint32_t i0) { return 0x00000000 + 0x3*i0; }
850 #define CP_SET_DRAW_STATE__0_COUNT__MASK 0x0000ffff
851 #define CP_SET_DRAW_STATE__0_COUNT__SHIFT 0
852 static inline uint32_t CP_SET_DRAW_STATE__0_COUNT(uint32_t val)
853 {
854 return ((val) << CP_SET_DRAW_STATE__0_COUNT__SHIFT) & CP_SET_DRAW_STATE__0_COUNT__MASK;
855 }
856 #define CP_SET_DRAW_STATE__0_DIRTY 0x00010000
857 #define CP_SET_DRAW_STATE__0_DISABLE 0x00020000
858 #define CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS 0x00040000
859 #define CP_SET_DRAW_STATE__0_LOAD_IMMED 0x00080000
860 #define CP_SET_DRAW_STATE__0_ENABLE_MASK__MASK 0x00f00000
861 #define CP_SET_DRAW_STATE__0_ENABLE_MASK__SHIFT 20
862 static inline uint32_t CP_SET_DRAW_STATE__0_ENABLE_MASK(uint32_t val)
863 {
864 return ((val) << CP_SET_DRAW_STATE__0_ENABLE_MASK__SHIFT) & CP_SET_DRAW_STATE__0_ENABLE_MASK__MASK;
865 }
866 #define CP_SET_DRAW_STATE__0_GROUP_ID__MASK 0x1f000000
867 #define CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT 24
868 static inline uint32_t CP_SET_DRAW_STATE__0_GROUP_ID(uint32_t val)
869 {
870 return ((val) << CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE__0_GROUP_ID__MASK;
871 }
872
873 static inline uint32_t REG_CP_SET_DRAW_STATE__1(uint32_t i0) { return 0x00000001 + 0x3*i0; }
874 #define CP_SET_DRAW_STATE__1_ADDR_LO__MASK 0xffffffff
875 #define CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT 0
876 static inline uint32_t CP_SET_DRAW_STATE__1_ADDR_LO(uint32_t val)
877 {
878 return ((val) << CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT) & CP_SET_DRAW_STATE__1_ADDR_LO__MASK;
879 }
880
881 static inline uint32_t REG_CP_SET_DRAW_STATE__2(uint32_t i0) { return 0x00000002 + 0x3*i0; }
882 #define CP_SET_DRAW_STATE__2_ADDR_HI__MASK 0xffffffff
883 #define CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT 0
884 static inline uint32_t CP_SET_DRAW_STATE__2_ADDR_HI(uint32_t val)
885 {
886 return ((val) << CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT) & CP_SET_DRAW_STATE__2_ADDR_HI__MASK;
887 }
888
889 #define REG_CP_SET_BIN_0 0x00000000
890
891 #define REG_CP_SET_BIN_1 0x00000001
892 #define CP_SET_BIN_1_X1__MASK 0x0000ffff
893 #define CP_SET_BIN_1_X1__SHIFT 0
894 static inline uint32_t CP_SET_BIN_1_X1(uint32_t val)
895 {
896 return ((val) << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK;
897 }
898 #define CP_SET_BIN_1_Y1__MASK 0xffff0000
899 #define CP_SET_BIN_1_Y1__SHIFT 16
900 static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val)
901 {
902 return ((val) << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK;
903 }
904
905 #define REG_CP_SET_BIN_2 0x00000002
906 #define CP_SET_BIN_2_X2__MASK 0x0000ffff
907 #define CP_SET_BIN_2_X2__SHIFT 0
908 static inline uint32_t CP_SET_BIN_2_X2(uint32_t val)
909 {
910 return ((val) << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK;
911 }
912 #define CP_SET_BIN_2_Y2__MASK 0xffff0000
913 #define CP_SET_BIN_2_Y2__SHIFT 16
914 static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val)
915 {
916 return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK;
917 }
918
919 #define REG_CP_SET_BIN_DATA_0 0x00000000
920 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK 0xffffffff
921 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT 0
922 static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val)
923 {
924 return ((val) << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK;
925 }
926
927 #define REG_CP_SET_BIN_DATA_1 0x00000001
928 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK 0xffffffff
929 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT 0
930 static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)
931 {
932 return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK;
933 }
934
935 #define REG_CP_SET_BIN_DATA5_0 0x00000000
936 #define CP_SET_BIN_DATA5_0_VSC_SIZE__MASK 0x003f0000
937 #define CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT 16
938 static inline uint32_t CP_SET_BIN_DATA5_0_VSC_SIZE(uint32_t val)
939 {
940 return ((val) << CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_0_VSC_SIZE__MASK;
941 }
942 #define CP_SET_BIN_DATA5_0_VSC_N__MASK 0x07c00000
943 #define CP_SET_BIN_DATA5_0_VSC_N__SHIFT 22
944 static inline uint32_t CP_SET_BIN_DATA5_0_VSC_N(uint32_t val)
945 {
946 return ((val) << CP_SET_BIN_DATA5_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_0_VSC_N__MASK;
947 }
948
949 #define REG_CP_SET_BIN_DATA5_1 0x00000001
950 #define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK 0xffffffff
951 #define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT 0
952 static inline uint32_t CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO(uint32_t val)
953 {
954 return ((val) << CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT) & CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK;
955 }
956
957 #define REG_CP_SET_BIN_DATA5_2 0x00000002
958 #define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK 0xffffffff
959 #define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT 0
960 static inline uint32_t CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI(uint32_t val)
961 {
962 return ((val) << CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT) & CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK;
963 }
964
965 #define REG_CP_SET_BIN_DATA5_3 0x00000003
966 #define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK 0xffffffff
967 #define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT 0
968 static inline uint32_t CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO(uint32_t val)
969 {
970 return ((val) << CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT) & CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK;
971 }
972
973 #define REG_CP_SET_BIN_DATA5_4 0x00000004
974 #define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK 0xffffffff
975 #define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT 0
976 static inline uint32_t CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(uint32_t val)
977 {
978 return ((val) << CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT) & CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK;
979 }
980
981 #define REG_CP_SET_BIN_DATA5_5 0x00000005
982 #define CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO__MASK 0xffffffff
983 #define CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO__SHIFT 0
984 static inline uint32_t CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO(uint32_t val)
985 {
986 return ((val) << CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO__SHIFT) & CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO__MASK;
987 }
988
989 #define REG_CP_SET_BIN_DATA5_6 0x00000006
990 #define CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO__MASK 0xffffffff
991 #define CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO__SHIFT 0
992 static inline uint32_t CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO(uint32_t val)
993 {
994 return ((val) << CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO__SHIFT) & CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO__MASK;
995 }
996
997 #define REG_CP_REG_TO_MEM_0 0x00000000
998 #define CP_REG_TO_MEM_0_REG__MASK 0x0000ffff
999 #define CP_REG_TO_MEM_0_REG__SHIFT 0
1000 static inline uint32_t CP_REG_TO_MEM_0_REG(uint32_t val)
1001 {
1002 return ((val) << CP_REG_TO_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_0_REG__MASK;
1003 }
1004 #define CP_REG_TO_MEM_0_CNT__MASK 0x3ff80000
1005 #define CP_REG_TO_MEM_0_CNT__SHIFT 19
1006 static inline uint32_t CP_REG_TO_MEM_0_CNT(uint32_t val)
1007 {
1008 return ((val) << CP_REG_TO_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_0_CNT__MASK;
1009 }
1010 #define CP_REG_TO_MEM_0_64B 0x40000000
1011 #define CP_REG_TO_MEM_0_ACCUMULATE 0x80000000
1012
1013 #define REG_CP_REG_TO_MEM_1 0x00000001
1014 #define CP_REG_TO_MEM_1_DEST__MASK 0xffffffff
1015 #define CP_REG_TO_MEM_1_DEST__SHIFT 0
1016 static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val)
1017 {
1018 return ((val) << CP_REG_TO_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_1_DEST__MASK;
1019 }
1020
1021 #define REG_CP_REG_TO_MEM_2 0x00000002
1022 #define CP_REG_TO_MEM_2_DEST_HI__MASK 0xffffffff
1023 #define CP_REG_TO_MEM_2_DEST_HI__SHIFT 0
1024 static inline uint32_t CP_REG_TO_MEM_2_DEST_HI(uint32_t val)
1025 {
1026 return ((val) << CP_REG_TO_MEM_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_2_DEST_HI__MASK;
1027 }
1028
1029 #define REG_CP_MEM_TO_REG_0 0x00000000
1030 #define CP_MEM_TO_REG_0_REG__MASK 0x0000ffff
1031 #define CP_MEM_TO_REG_0_REG__SHIFT 0
1032 static inline uint32_t CP_MEM_TO_REG_0_REG(uint32_t val)
1033 {
1034 return ((val) << CP_MEM_TO_REG_0_REG__SHIFT) & CP_MEM_TO_REG_0_REG__MASK;
1035 }
1036 #define CP_MEM_TO_REG_0_CNT__MASK 0x3ff80000
1037 #define CP_MEM_TO_REG_0_CNT__SHIFT 19
1038 static inline uint32_t CP_MEM_TO_REG_0_CNT(uint32_t val)
1039 {
1040 return ((val) << CP_MEM_TO_REG_0_CNT__SHIFT) & CP_MEM_TO_REG_0_CNT__MASK;
1041 }
1042 #define CP_MEM_TO_REG_0_64B 0x40000000
1043 #define CP_MEM_TO_REG_0_ACCUMULATE 0x80000000
1044
1045 #define REG_CP_MEM_TO_REG_1 0x00000001
1046 #define CP_MEM_TO_REG_1_SRC__MASK 0xffffffff
1047 #define CP_MEM_TO_REG_1_SRC__SHIFT 0
1048 static inline uint32_t CP_MEM_TO_REG_1_SRC(uint32_t val)
1049 {
1050 return ((val) << CP_MEM_TO_REG_1_SRC__SHIFT) & CP_MEM_TO_REG_1_SRC__MASK;
1051 }
1052
1053 #define REG_CP_MEM_TO_REG_2 0x00000002
1054 #define CP_MEM_TO_REG_2_SRC_HI__MASK 0xffffffff
1055 #define CP_MEM_TO_REG_2_SRC_HI__SHIFT 0
1056 static inline uint32_t CP_MEM_TO_REG_2_SRC_HI(uint32_t val)
1057 {
1058 return ((val) << CP_MEM_TO_REG_2_SRC_HI__SHIFT) & CP_MEM_TO_REG_2_SRC_HI__MASK;
1059 }
1060
1061 #define REG_CP_MEM_TO_MEM_0 0x00000000
1062 #define CP_MEM_TO_MEM_0_NEG_A 0x00000001
1063 #define CP_MEM_TO_MEM_0_NEG_B 0x00000002
1064 #define CP_MEM_TO_MEM_0_NEG_C 0x00000004
1065 #define CP_MEM_TO_MEM_0_DOUBLE 0x20000000
1066
1067 #define REG_CP_COND_WRITE_0 0x00000000
1068 #define CP_COND_WRITE_0_FUNCTION__MASK 0x00000007
1069 #define CP_COND_WRITE_0_FUNCTION__SHIFT 0
1070 static inline uint32_t CP_COND_WRITE_0_FUNCTION(enum cp_cond_function val)
1071 {
1072 return ((val) << CP_COND_WRITE_0_FUNCTION__SHIFT) & CP_COND_WRITE_0_FUNCTION__MASK;
1073 }
1074 #define CP_COND_WRITE_0_POLL_MEMORY 0x00000010
1075 #define CP_COND_WRITE_0_WRITE_MEMORY 0x00000100
1076
1077 #define REG_CP_COND_WRITE_1 0x00000001
1078 #define CP_COND_WRITE_1_POLL_ADDR__MASK 0xffffffff
1079 #define CP_COND_WRITE_1_POLL_ADDR__SHIFT 0
1080 static inline uint32_t CP_COND_WRITE_1_POLL_ADDR(uint32_t val)
1081 {
1082 return ((val) << CP_COND_WRITE_1_POLL_ADDR__SHIFT) & CP_COND_WRITE_1_POLL_ADDR__MASK;
1083 }
1084
1085 #define REG_CP_COND_WRITE_2 0x00000002
1086 #define CP_COND_WRITE_2_REF__MASK 0xffffffff
1087 #define CP_COND_WRITE_2_REF__SHIFT 0
1088 static inline uint32_t CP_COND_WRITE_2_REF(uint32_t val)
1089 {
1090 return ((val) << CP_COND_WRITE_2_REF__SHIFT) & CP_COND_WRITE_2_REF__MASK;
1091 }
1092
1093 #define REG_CP_COND_WRITE_3 0x00000003
1094 #define CP_COND_WRITE_3_MASK__MASK 0xffffffff
1095 #define CP_COND_WRITE_3_MASK__SHIFT 0
1096 static inline uint32_t CP_COND_WRITE_3_MASK(uint32_t val)
1097 {
1098 return ((val) << CP_COND_WRITE_3_MASK__SHIFT) & CP_COND_WRITE_3_MASK__MASK;
1099 }
1100
1101 #define REG_CP_COND_WRITE_4 0x00000004
1102 #define CP_COND_WRITE_4_WRITE_ADDR__MASK 0xffffffff
1103 #define CP_COND_WRITE_4_WRITE_ADDR__SHIFT 0
1104 static inline uint32_t CP_COND_WRITE_4_WRITE_ADDR(uint32_t val)
1105 {
1106 return ((val) << CP_COND_WRITE_4_WRITE_ADDR__SHIFT) & CP_COND_WRITE_4_WRITE_ADDR__MASK;
1107 }
1108
1109 #define REG_CP_COND_WRITE_5 0x00000005
1110 #define CP_COND_WRITE_5_WRITE_DATA__MASK 0xffffffff
1111 #define CP_COND_WRITE_5_WRITE_DATA__SHIFT 0
1112 static inline uint32_t CP_COND_WRITE_5_WRITE_DATA(uint32_t val)
1113 {
1114 return ((val) << CP_COND_WRITE_5_WRITE_DATA__SHIFT) & CP_COND_WRITE_5_WRITE_DATA__MASK;
1115 }
1116
1117 #define REG_CP_COND_WRITE5_0 0x00000000
1118 #define CP_COND_WRITE5_0_FUNCTION__MASK 0x00000007
1119 #define CP_COND_WRITE5_0_FUNCTION__SHIFT 0
1120 static inline uint32_t CP_COND_WRITE5_0_FUNCTION(enum cp_cond_function val)
1121 {
1122 return ((val) << CP_COND_WRITE5_0_FUNCTION__SHIFT) & CP_COND_WRITE5_0_FUNCTION__MASK;
1123 }
1124 #define CP_COND_WRITE5_0_POLL_MEMORY 0x00000010
1125 #define CP_COND_WRITE5_0_WRITE_MEMORY 0x00000100
1126
1127 #define REG_CP_COND_WRITE5_1 0x00000001
1128 #define CP_COND_WRITE5_1_POLL_ADDR_LO__MASK 0xffffffff
1129 #define CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT 0
1130 static inline uint32_t CP_COND_WRITE5_1_POLL_ADDR_LO(uint32_t val)
1131 {
1132 return ((val) << CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT) & CP_COND_WRITE5_1_POLL_ADDR_LO__MASK;
1133 }
1134
1135 #define REG_CP_COND_WRITE5_2 0x00000002
1136 #define CP_COND_WRITE5_2_POLL_ADDR_HI__MASK 0xffffffff
1137 #define CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT 0
1138 static inline uint32_t CP_COND_WRITE5_2_POLL_ADDR_HI(uint32_t val)
1139 {
1140 return ((val) << CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT) & CP_COND_WRITE5_2_POLL_ADDR_HI__MASK;
1141 }
1142
1143 #define REG_CP_COND_WRITE5_3 0x00000003
1144 #define CP_COND_WRITE5_3_REF__MASK 0xffffffff
1145 #define CP_COND_WRITE5_3_REF__SHIFT 0
1146 static inline uint32_t CP_COND_WRITE5_3_REF(uint32_t val)
1147 {
1148 return ((val) << CP_COND_WRITE5_3_REF__SHIFT) & CP_COND_WRITE5_3_REF__MASK;
1149 }
1150
1151 #define REG_CP_COND_WRITE5_4 0x00000004
1152 #define CP_COND_WRITE5_4_MASK__MASK 0xffffffff
1153 #define CP_COND_WRITE5_4_MASK__SHIFT 0
1154 static inline uint32_t CP_COND_WRITE5_4_MASK(uint32_t val)
1155 {
1156 return ((val) << CP_COND_WRITE5_4_MASK__SHIFT) & CP_COND_WRITE5_4_MASK__MASK;
1157 }
1158
1159 #define REG_CP_COND_WRITE5_5 0x00000005
1160 #define CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK 0xffffffff
1161 #define CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT 0
1162 static inline uint32_t CP_COND_WRITE5_5_WRITE_ADDR_LO(uint32_t val)
1163 {
1164 return ((val) << CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT) & CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK;
1165 }
1166
1167 #define REG_CP_COND_WRITE5_6 0x00000006
1168 #define CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK 0xffffffff
1169 #define CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT 0
1170 static inline uint32_t CP_COND_WRITE5_6_WRITE_ADDR_HI(uint32_t val)
1171 {
1172 return ((val) << CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT) & CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK;
1173 }
1174
1175 #define REG_CP_COND_WRITE5_7 0x00000007
1176 #define CP_COND_WRITE5_7_WRITE_DATA__MASK 0xffffffff
1177 #define CP_COND_WRITE5_7_WRITE_DATA__SHIFT 0
1178 static inline uint32_t CP_COND_WRITE5_7_WRITE_DATA(uint32_t val)
1179 {
1180 return ((val) << CP_COND_WRITE5_7_WRITE_DATA__SHIFT) & CP_COND_WRITE5_7_WRITE_DATA__MASK;
1181 }
1182
1183 #define REG_CP_DISPATCH_COMPUTE_0 0x00000000
1184
1185 #define REG_CP_DISPATCH_COMPUTE_1 0x00000001
1186 #define CP_DISPATCH_COMPUTE_1_X__MASK 0xffffffff
1187 #define CP_DISPATCH_COMPUTE_1_X__SHIFT 0
1188 static inline uint32_t CP_DISPATCH_COMPUTE_1_X(uint32_t val)
1189 {
1190 return ((val) << CP_DISPATCH_COMPUTE_1_X__SHIFT) & CP_DISPATCH_COMPUTE_1_X__MASK;
1191 }
1192
1193 #define REG_CP_DISPATCH_COMPUTE_2 0x00000002
1194 #define CP_DISPATCH_COMPUTE_2_Y__MASK 0xffffffff
1195 #define CP_DISPATCH_COMPUTE_2_Y__SHIFT 0
1196 static inline uint32_t CP_DISPATCH_COMPUTE_2_Y(uint32_t val)
1197 {
1198 return ((val) << CP_DISPATCH_COMPUTE_2_Y__SHIFT) & CP_DISPATCH_COMPUTE_2_Y__MASK;
1199 }
1200
1201 #define REG_CP_DISPATCH_COMPUTE_3 0x00000003
1202 #define CP_DISPATCH_COMPUTE_3_Z__MASK 0xffffffff
1203 #define CP_DISPATCH_COMPUTE_3_Z__SHIFT 0
1204 static inline uint32_t CP_DISPATCH_COMPUTE_3_Z(uint32_t val)
1205 {
1206 return ((val) << CP_DISPATCH_COMPUTE_3_Z__SHIFT) & CP_DISPATCH_COMPUTE_3_Z__MASK;
1207 }
1208
1209 #define REG_CP_SET_RENDER_MODE_0 0x00000000
1210 #define CP_SET_RENDER_MODE_0_MODE__MASK 0x000001ff
1211 #define CP_SET_RENDER_MODE_0_MODE__SHIFT 0
1212 static inline uint32_t CP_SET_RENDER_MODE_0_MODE(enum render_mode_cmd val)
1213 {
1214 return ((val) << CP_SET_RENDER_MODE_0_MODE__SHIFT) & CP_SET_RENDER_MODE_0_MODE__MASK;
1215 }
1216
1217 #define REG_CP_SET_RENDER_MODE_1 0x00000001
1218 #define CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK 0xffffffff
1219 #define CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT 0
1220 static inline uint32_t CP_SET_RENDER_MODE_1_ADDR_0_LO(uint32_t val)
1221 {
1222 return ((val) << CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT) & CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK;
1223 }
1224
1225 #define REG_CP_SET_RENDER_MODE_2 0x00000002
1226 #define CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK 0xffffffff
1227 #define CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT 0
1228 static inline uint32_t CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val)
1229 {
1230 return ((val) << CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT) & CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK;
1231 }
1232
1233 #define REG_CP_SET_RENDER_MODE_3 0x00000003
1234 #define CP_SET_RENDER_MODE_3_VSC_ENABLE 0x00000008
1235 #define CP_SET_RENDER_MODE_3_GMEM_ENABLE 0x00000010
1236
1237 #define REG_CP_SET_RENDER_MODE_4 0x00000004
1238
1239 #define REG_CP_SET_RENDER_MODE_5 0x00000005
1240 #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK 0xffffffff
1241 #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT 0
1242 static inline uint32_t CP_SET_RENDER_MODE_5_ADDR_1_LEN(uint32_t val)
1243 {
1244 return ((val) << CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT) & CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK;
1245 }
1246
1247 #define REG_CP_SET_RENDER_MODE_6 0x00000006
1248 #define CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK 0xffffffff
1249 #define CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT 0
1250 static inline uint32_t CP_SET_RENDER_MODE_6_ADDR_1_LO(uint32_t val)
1251 {
1252 return ((val) << CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT) & CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK;
1253 }
1254
1255 #define REG_CP_SET_RENDER_MODE_7 0x00000007
1256 #define CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK 0xffffffff
1257 #define CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT 0
1258 static inline uint32_t CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val)
1259 {
1260 return ((val) << CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT) & CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK;
1261 }
1262
1263 #define REG_CP_COMPUTE_CHECKPOINT_0 0x00000000
1264 #define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK 0xffffffff
1265 #define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT 0
1266 static inline uint32_t CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO(uint32_t val)
1267 {
1268 return ((val) << CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK;
1269 }
1270
1271 #define REG_CP_COMPUTE_CHECKPOINT_1 0x00000001
1272 #define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK 0xffffffff
1273 #define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT 0
1274 static inline uint32_t CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI(uint32_t val)
1275 {
1276 return ((val) << CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK;
1277 }
1278
1279 #define REG_CP_COMPUTE_CHECKPOINT_2 0x00000002
1280
1281 #define REG_CP_COMPUTE_CHECKPOINT_3 0x00000003
1282 #define CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__MASK 0xffffffff
1283 #define CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__SHIFT 0
1284 static inline uint32_t CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN(uint32_t val)
1285 {
1286 return ((val) << CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__SHIFT) & CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__MASK;
1287 }
1288
1289 #define REG_CP_COMPUTE_CHECKPOINT_4 0x00000004
1290
1291 #define REG_CP_COMPUTE_CHECKPOINT_5 0x00000005
1292 #define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK 0xffffffff
1293 #define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT 0
1294 static inline uint32_t CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO(uint32_t val)
1295 {
1296 return ((val) << CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK;
1297 }
1298
1299 #define REG_CP_COMPUTE_CHECKPOINT_6 0x00000006
1300 #define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK 0xffffffff
1301 #define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT 0
1302 static inline uint32_t CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI(uint32_t val)
1303 {
1304 return ((val) << CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK;
1305 }
1306
1307 #define REG_CP_COMPUTE_CHECKPOINT_7 0x00000007
1308
1309 #define REG_CP_PERFCOUNTER_ACTION_0 0x00000000
1310
1311 #define REG_CP_PERFCOUNTER_ACTION_1 0x00000001
1312 #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK 0xffffffff
1313 #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT 0
1314 static inline uint32_t CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(uint32_t val)
1315 {
1316 return ((val) << CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT) & CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK;
1317 }
1318
1319 #define REG_CP_PERFCOUNTER_ACTION_2 0x00000002
1320 #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK 0xffffffff
1321 #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT 0
1322 static inline uint32_t CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(uint32_t val)
1323 {
1324 return ((val) << CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT) & CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK;
1325 }
1326
1327 #define REG_CP_EVENT_WRITE_0 0x00000000
1328 #define CP_EVENT_WRITE_0_EVENT__MASK 0x000000ff
1329 #define CP_EVENT_WRITE_0_EVENT__SHIFT 0
1330 static inline uint32_t CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val)
1331 {
1332 return ((val) << CP_EVENT_WRITE_0_EVENT__SHIFT) & CP_EVENT_WRITE_0_EVENT__MASK;
1333 }
1334 #define CP_EVENT_WRITE_0_TIMESTAMP 0x40000000
1335
1336 #define REG_CP_EVENT_WRITE_1 0x00000001
1337 #define CP_EVENT_WRITE_1_ADDR_0_LO__MASK 0xffffffff
1338 #define CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT 0
1339 static inline uint32_t CP_EVENT_WRITE_1_ADDR_0_LO(uint32_t val)
1340 {
1341 return ((val) << CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT) & CP_EVENT_WRITE_1_ADDR_0_LO__MASK;
1342 }
1343
1344 #define REG_CP_EVENT_WRITE_2 0x00000002
1345 #define CP_EVENT_WRITE_2_ADDR_0_HI__MASK 0xffffffff
1346 #define CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT 0
1347 static inline uint32_t CP_EVENT_WRITE_2_ADDR_0_HI(uint32_t val)
1348 {
1349 return ((val) << CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT) & CP_EVENT_WRITE_2_ADDR_0_HI__MASK;
1350 }
1351
1352 #define REG_CP_EVENT_WRITE_3 0x00000003
1353
1354 #define REG_CP_BLIT_0 0x00000000
1355 #define CP_BLIT_0_OP__MASK 0x0000000f
1356 #define CP_BLIT_0_OP__SHIFT 0
1357 static inline uint32_t CP_BLIT_0_OP(enum cp_blit_cmd val)
1358 {
1359 return ((val) << CP_BLIT_0_OP__SHIFT) & CP_BLIT_0_OP__MASK;
1360 }
1361
1362 #define REG_CP_BLIT_1 0x00000001
1363 #define CP_BLIT_1_SRC_X1__MASK 0x00003fff
1364 #define CP_BLIT_1_SRC_X1__SHIFT 0
1365 static inline uint32_t CP_BLIT_1_SRC_X1(uint32_t val)
1366 {
1367 return ((val) << CP_BLIT_1_SRC_X1__SHIFT) & CP_BLIT_1_SRC_X1__MASK;
1368 }
1369 #define CP_BLIT_1_SRC_Y1__MASK 0x3fff0000
1370 #define CP_BLIT_1_SRC_Y1__SHIFT 16
1371 static inline uint32_t CP_BLIT_1_SRC_Y1(uint32_t val)
1372 {
1373 return ((val) << CP_BLIT_1_SRC_Y1__SHIFT) & CP_BLIT_1_SRC_Y1__MASK;
1374 }
1375
1376 #define REG_CP_BLIT_2 0x00000002
1377 #define CP_BLIT_2_SRC_X2__MASK 0x00003fff
1378 #define CP_BLIT_2_SRC_X2__SHIFT 0
1379 static inline uint32_t CP_BLIT_2_SRC_X2(uint32_t val)
1380 {
1381 return ((val) << CP_BLIT_2_SRC_X2__SHIFT) & CP_BLIT_2_SRC_X2__MASK;
1382 }
1383 #define CP_BLIT_2_SRC_Y2__MASK 0x3fff0000
1384 #define CP_BLIT_2_SRC_Y2__SHIFT 16
1385 static inline uint32_t CP_BLIT_2_SRC_Y2(uint32_t val)
1386 {
1387 return ((val) << CP_BLIT_2_SRC_Y2__SHIFT) & CP_BLIT_2_SRC_Y2__MASK;
1388 }
1389
1390 #define REG_CP_BLIT_3 0x00000003
1391 #define CP_BLIT_3_DST_X1__MASK 0x00003fff
1392 #define CP_BLIT_3_DST_X1__SHIFT 0
1393 static inline uint32_t CP_BLIT_3_DST_X1(uint32_t val)
1394 {
1395 return ((val) << CP_BLIT_3_DST_X1__SHIFT) & CP_BLIT_3_DST_X1__MASK;
1396 }
1397 #define CP_BLIT_3_DST_Y1__MASK 0x3fff0000
1398 #define CP_BLIT_3_DST_Y1__SHIFT 16
1399 static inline uint32_t CP_BLIT_3_DST_Y1(uint32_t val)
1400 {
1401 return ((val) << CP_BLIT_3_DST_Y1__SHIFT) & CP_BLIT_3_DST_Y1__MASK;
1402 }
1403
1404 #define REG_CP_BLIT_4 0x00000004
1405 #define CP_BLIT_4_DST_X2__MASK 0x00003fff
1406 #define CP_BLIT_4_DST_X2__SHIFT 0
1407 static inline uint32_t CP_BLIT_4_DST_X2(uint32_t val)
1408 {
1409 return ((val) << CP_BLIT_4_DST_X2__SHIFT) & CP_BLIT_4_DST_X2__MASK;
1410 }
1411 #define CP_BLIT_4_DST_Y2__MASK 0x3fff0000
1412 #define CP_BLIT_4_DST_Y2__SHIFT 16
1413 static inline uint32_t CP_BLIT_4_DST_Y2(uint32_t val)
1414 {
1415 return ((val) << CP_BLIT_4_DST_Y2__SHIFT) & CP_BLIT_4_DST_Y2__MASK;
1416 }
1417
1418 #define REG_CP_EXEC_CS_0 0x00000000
1419
1420 #define REG_CP_EXEC_CS_1 0x00000001
1421 #define CP_EXEC_CS_1_NGROUPS_X__MASK 0xffffffff
1422 #define CP_EXEC_CS_1_NGROUPS_X__SHIFT 0
1423 static inline uint32_t CP_EXEC_CS_1_NGROUPS_X(uint32_t val)
1424 {
1425 return ((val) << CP_EXEC_CS_1_NGROUPS_X__SHIFT) & CP_EXEC_CS_1_NGROUPS_X__MASK;
1426 }
1427
1428 #define REG_CP_EXEC_CS_2 0x00000002
1429 #define CP_EXEC_CS_2_NGROUPS_Y__MASK 0xffffffff
1430 #define CP_EXEC_CS_2_NGROUPS_Y__SHIFT 0
1431 static inline uint32_t CP_EXEC_CS_2_NGROUPS_Y(uint32_t val)
1432 {
1433 return ((val) << CP_EXEC_CS_2_NGROUPS_Y__SHIFT) & CP_EXEC_CS_2_NGROUPS_Y__MASK;
1434 }
1435
1436 #define REG_CP_EXEC_CS_3 0x00000003
1437 #define CP_EXEC_CS_3_NGROUPS_Z__MASK 0xffffffff
1438 #define CP_EXEC_CS_3_NGROUPS_Z__SHIFT 0
1439 static inline uint32_t CP_EXEC_CS_3_NGROUPS_Z(uint32_t val)
1440 {
1441 return ((val) << CP_EXEC_CS_3_NGROUPS_Z__SHIFT) & CP_EXEC_CS_3_NGROUPS_Z__MASK;
1442 }
1443
1444 #define REG_A4XX_CP_EXEC_CS_INDIRECT_0 0x00000000
1445
1446
1447 #define REG_A4XX_CP_EXEC_CS_INDIRECT_1 0x00000001
1448 #define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK 0xffffffff
1449 #define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT 0
1450 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_1_ADDR(uint32_t val)
1451 {
1452 return ((val) << A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK;
1453 }
1454
1455 #define REG_A4XX_CP_EXEC_CS_INDIRECT_2 0x00000002
1456 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK 0x00000ffc
1457 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT 2
1458 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX(uint32_t val)
1459 {
1460 return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK;
1461 }
1462 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK 0x003ff000
1463 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT 12
1464 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY(uint32_t val)
1465 {
1466 return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK;
1467 }
1468 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK 0xffc00000
1469 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT 22
1470 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ(uint32_t val)
1471 {
1472 return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK;
1473 }
1474
1475
1476 #define REG_A5XX_CP_EXEC_CS_INDIRECT_1 0x00000001
1477 #define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK 0xffffffff
1478 #define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT 0
1479 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO(uint32_t val)
1480 {
1481 return ((val) << A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK;
1482 }
1483
1484 #define REG_A5XX_CP_EXEC_CS_INDIRECT_2 0x00000002
1485 #define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK 0xffffffff
1486 #define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT 0
1487 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI(uint32_t val)
1488 {
1489 return ((val) << A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK;
1490 }
1491
1492 #define REG_A5XX_CP_EXEC_CS_INDIRECT_3 0x00000003
1493 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK 0x00000ffc
1494 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT 2
1495 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(uint32_t val)
1496 {
1497 return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK;
1498 }
1499 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK 0x003ff000
1500 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT 12
1501 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(uint32_t val)
1502 {
1503 return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK;
1504 }
1505 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK 0xffc00000
1506 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT 22
1507 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(uint32_t val)
1508 {
1509 return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK;
1510 }
1511
1512 #define REG_A2XX_CP_SET_MARKER_0 0x00000000
1513 #define A2XX_CP_SET_MARKER_0_MARKER__MASK 0x0000000f
1514 #define A2XX_CP_SET_MARKER_0_MARKER__SHIFT 0
1515 static inline uint32_t A2XX_CP_SET_MARKER_0_MARKER(uint32_t val)
1516 {
1517 return ((val) << A2XX_CP_SET_MARKER_0_MARKER__SHIFT) & A2XX_CP_SET_MARKER_0_MARKER__MASK;
1518 }
1519 #define A2XX_CP_SET_MARKER_0_MODE__MASK 0x0000000f
1520 #define A2XX_CP_SET_MARKER_0_MODE__SHIFT 0
1521 static inline uint32_t A2XX_CP_SET_MARKER_0_MODE(enum a6xx_render_mode val)
1522 {
1523 return ((val) << A2XX_CP_SET_MARKER_0_MODE__SHIFT) & A2XX_CP_SET_MARKER_0_MODE__MASK;
1524 }
1525 #define A2XX_CP_SET_MARKER_0_IFPC 0x00000100
1526
1527 static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG_(uint32_t i0) { return 0x00000000 + 0x3*i0; }
1528
1529 static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG__0(uint32_t i0) { return 0x00000000 + 0x3*i0; }
1530 #define A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK 0x00000007
1531 #define A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT 0
1532 static inline uint32_t A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(enum pseudo_reg val)
1533 {
1534 return ((val) << A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT) & A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK;
1535 }
1536
1537 static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG__1(uint32_t i0) { return 0x00000001 + 0x3*i0; }
1538 #define A2XX_CP_SET_PSEUDO_REG__1_LO__MASK 0xffffffff
1539 #define A2XX_CP_SET_PSEUDO_REG__1_LO__SHIFT 0
1540 static inline uint32_t A2XX_CP_SET_PSEUDO_REG__1_LO(uint32_t val)
1541 {
1542 return ((val) << A2XX_CP_SET_PSEUDO_REG__1_LO__SHIFT) & A2XX_CP_SET_PSEUDO_REG__1_LO__MASK;
1543 }
1544
1545 static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG__2(uint32_t i0) { return 0x00000002 + 0x3*i0; }
1546 #define A2XX_CP_SET_PSEUDO_REG__2_HI__MASK 0xffffffff
1547 #define A2XX_CP_SET_PSEUDO_REG__2_HI__SHIFT 0
1548 static inline uint32_t A2XX_CP_SET_PSEUDO_REG__2_HI(uint32_t val)
1549 {
1550 return ((val) << A2XX_CP_SET_PSEUDO_REG__2_HI__SHIFT) & A2XX_CP_SET_PSEUDO_REG__2_HI__MASK;
1551 }
1552
1553 #define REG_A2XX_CP_REG_TEST_0 0x00000000
1554 #define A2XX_CP_REG_TEST_0_REG__MASK 0x00000fff
1555 #define A2XX_CP_REG_TEST_0_REG__SHIFT 0
1556 static inline uint32_t A2XX_CP_REG_TEST_0_REG(uint32_t val)
1557 {
1558 return ((val) << A2XX_CP_REG_TEST_0_REG__SHIFT) & A2XX_CP_REG_TEST_0_REG__MASK;
1559 }
1560 #define A2XX_CP_REG_TEST_0_BIT__MASK 0x01f00000
1561 #define A2XX_CP_REG_TEST_0_BIT__SHIFT 20
1562 static inline uint32_t A2XX_CP_REG_TEST_0_BIT(uint32_t val)
1563 {
1564 return ((val) << A2XX_CP_REG_TEST_0_BIT__SHIFT) & A2XX_CP_REG_TEST_0_BIT__MASK;
1565 }
1566 #define A2XX_CP_REG_TEST_0_UNK25 0x02000000
1567
1568
1569 #endif /* ADRENO_PM4_XML */