2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 #include "tu_private.h"
30 #include "ir3/ir3_nir.h"
31 #include "main/menums.h"
33 #include "nir/nir_builder.h"
34 #include "spirv/nir_spirv.h"
35 #include "util/debug.h"
36 #include "util/mesa-sha1.h"
37 #include "util/u_atomic.h"
38 #include "vk_format.h"
43 /* Emit IB that preloads the descriptors that the shader uses */
45 static inline uint32_t
46 tu6_vkstage2opcode(VkShaderStageFlags stage
)
49 case VK_SHADER_STAGE_VERTEX_BIT
:
50 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
51 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
52 case VK_SHADER_STAGE_GEOMETRY_BIT
:
53 return CP_LOAD_STATE6_GEOM
;
54 case VK_SHADER_STAGE_FRAGMENT_BIT
:
55 case VK_SHADER_STAGE_COMPUTE_BIT
:
56 return CP_LOAD_STATE6_FRAG
;
58 unreachable("bad shader type");
62 static enum a6xx_state_block
63 tu6_tex_stage2sb(VkShaderStageFlags stage
)
66 case VK_SHADER_STAGE_VERTEX_BIT
:
68 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
70 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
72 case VK_SHADER_STAGE_GEOMETRY_BIT
:
74 case VK_SHADER_STAGE_FRAGMENT_BIT
:
76 case VK_SHADER_STAGE_COMPUTE_BIT
:
79 unreachable("bad shader stage");
83 static enum a6xx_state_block
84 tu6_ubo_stage2sb(VkShaderStageFlags stage
)
87 case VK_SHADER_STAGE_VERTEX_BIT
:
89 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
91 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
93 case VK_SHADER_STAGE_GEOMETRY_BIT
:
95 case VK_SHADER_STAGE_FRAGMENT_BIT
:
97 case VK_SHADER_STAGE_COMPUTE_BIT
:
100 unreachable("bad shader stage");
105 emit_load_state(struct tu_cs
*cs
, unsigned opcode
, enum a6xx_state_type st
,
106 enum a6xx_state_block sb
, unsigned base
, unsigned offset
,
109 /* Note: just emit one packet, even if count overflows NUM_UNIT. It's not
110 * clear if emitting more packets will even help anything. Presumably the
111 * descriptor cache is relatively small, and these packets stop doing
112 * anything when there are too many descriptors.
114 tu_cs_emit_pkt7(cs
, opcode
, 3);
116 CP_LOAD_STATE6_0_STATE_TYPE(st
) |
117 CP_LOAD_STATE6_0_STATE_SRC(SS6_BINDLESS
) |
118 CP_LOAD_STATE6_0_STATE_BLOCK(sb
) |
119 CP_LOAD_STATE6_0_NUM_UNIT(MIN2(count
, 1024-1)));
120 tu_cs_emit_qw(cs
, offset
| (base
<< 28));
124 tu6_load_state_size(struct tu_pipeline_layout
*layout
, bool compute
)
126 const unsigned load_state_size
= 4;
128 for (unsigned i
= 0; i
< layout
->num_sets
; i
++) {
129 struct tu_descriptor_set_layout
*set_layout
= layout
->set
[i
].layout
;
130 for (unsigned j
= 0; j
< set_layout
->binding_count
; j
++) {
131 struct tu_descriptor_set_binding_layout
*binding
= &set_layout
->binding
[j
];
133 /* Note: some users, like amber for example, pass in
134 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
135 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
137 VkShaderStageFlags stages
= compute
?
138 binding
->shader_stages
& VK_SHADER_STAGE_COMPUTE_BIT
:
139 binding
->shader_stages
& VK_SHADER_STAGE_ALL_GRAPHICS
;
140 unsigned stage_count
= util_bitcount(stages
);
141 switch (binding
->type
) {
142 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
143 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
:
144 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
:
145 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
146 /* IBO-backed resources only need one packet for all graphics stages */
147 if (stages
& ~VK_SHADER_STAGE_COMPUTE_BIT
)
149 if (stages
& VK_SHADER_STAGE_COMPUTE_BIT
)
152 case VK_DESCRIPTOR_TYPE_SAMPLER
:
153 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
:
154 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
155 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
156 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
157 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
158 /* Textures and UBO's needs a packet for each stage */
161 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
162 /* Because of how we pack combined images and samplers, we
163 * currently can't use one packet for the whole array.
165 count
= stage_count
* binding
->array_size
* 2;
168 unreachable("bad descriptor type");
170 size
+= count
* load_state_size
;
177 tu6_emit_load_state(struct tu_pipeline
*pipeline
, bool compute
)
179 unsigned size
= tu6_load_state_size(pipeline
->layout
, compute
);
184 tu_cs_begin_sub_stream(&pipeline
->cs
, size
, &cs
);
186 struct tu_pipeline_layout
*layout
= pipeline
->layout
;
187 for (unsigned i
= 0; i
< layout
->num_sets
; i
++) {
188 struct tu_descriptor_set_layout
*set_layout
= layout
->set
[i
].layout
;
189 for (unsigned j
= 0; j
< set_layout
->binding_count
; j
++) {
190 struct tu_descriptor_set_binding_layout
*binding
= &set_layout
->binding
[j
];
192 unsigned offset
= binding
->offset
/ 4;
193 /* Note: some users, like amber for example, pass in
194 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
195 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
197 VkShaderStageFlags stages
= compute
?
198 binding
->shader_stages
& VK_SHADER_STAGE_COMPUTE_BIT
:
199 binding
->shader_stages
& VK_SHADER_STAGE_ALL_GRAPHICS
;
200 unsigned count
= binding
->array_size
;
201 if (count
== 0 || stages
== 0)
203 switch (binding
->type
) {
204 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
:
206 offset
= (layout
->input_attachment_count
+
207 layout
->set
[i
].dynamic_offset_start
+
208 binding
->dynamic_offset_offset
) * A6XX_TEX_CONST_DWORDS
;
210 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
211 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
:
212 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
213 /* IBO-backed resources only need one packet for all graphics stages */
214 if (stages
& ~VK_SHADER_STAGE_COMPUTE_BIT
) {
215 emit_load_state(&cs
, CP_LOAD_STATE6
, ST6_SHADER
, SB6_IBO
,
216 base
, offset
, count
);
218 if (stages
& VK_SHADER_STAGE_COMPUTE_BIT
) {
219 emit_load_state(&cs
, CP_LOAD_STATE6_FRAG
, ST6_IBO
, SB6_CS_SHADER
,
220 base
, offset
, count
);
223 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
225 offset
= (layout
->set
[i
].input_attachment_start
+
226 binding
->input_attachment_offset
) * A6XX_TEX_CONST_DWORDS
;
227 case VK_DESCRIPTOR_TYPE_SAMPLER
:
228 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
:
229 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
: {
231 for_each_bit(stage_log2
, stages
) {
232 VkShaderStageFlags stage
= 1 << stage_log2
;
233 emit_load_state(&cs
, tu6_vkstage2opcode(stage
),
234 binding
->type
== VK_DESCRIPTOR_TYPE_SAMPLER
?
235 ST6_SHADER
: ST6_CONSTANTS
,
236 tu6_tex_stage2sb(stage
), base
, offset
, count
);
240 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
242 offset
= (layout
->input_attachment_count
+
243 layout
->set
[i
].dynamic_offset_start
+
244 binding
->dynamic_offset_offset
) * A6XX_TEX_CONST_DWORDS
;
246 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
: {
248 for_each_bit(stage_log2
, stages
) {
249 VkShaderStageFlags stage
= 1 << stage_log2
;
250 emit_load_state(&cs
, tu6_vkstage2opcode(stage
), ST6_UBO
,
251 tu6_ubo_stage2sb(stage
), base
, offset
, count
);
255 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
: {
257 for_each_bit(stage_log2
, stages
) {
258 VkShaderStageFlags stage
= 1 << stage_log2
;
259 /* TODO: We could emit less CP_LOAD_STATE6 if we used
260 * struct-of-arrays instead of array-of-structs.
262 for (unsigned i
= 0; i
< count
; i
++) {
263 unsigned tex_offset
= offset
+ 2 * i
* A6XX_TEX_CONST_DWORDS
;
264 unsigned sam_offset
= offset
+ (2 * i
+ 1) * A6XX_TEX_CONST_DWORDS
;
265 emit_load_state(&cs
, tu6_vkstage2opcode(stage
),
266 ST6_CONSTANTS
, tu6_tex_stage2sb(stage
),
267 base
, tex_offset
, 1);
268 emit_load_state(&cs
, tu6_vkstage2opcode(stage
),
269 ST6_SHADER
, tu6_tex_stage2sb(stage
),
270 base
, sam_offset
, 1);
276 unreachable("bad descriptor type");
281 pipeline
->load_state
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &cs
);
284 struct tu_pipeline_builder
286 struct tu_device
*device
;
287 struct tu_pipeline_cache
*cache
;
288 struct tu_pipeline_layout
*layout
;
289 const VkAllocationCallbacks
*alloc
;
290 const VkGraphicsPipelineCreateInfo
*create_info
;
292 struct tu_shader
*shaders
[MESA_SHADER_STAGES
];
293 uint32_t shader_offsets
[MESA_SHADER_STAGES
];
294 uint32_t binning_vs_offset
;
295 uint32_t shader_total_size
;
297 bool rasterizer_discard
;
298 /* these states are affectd by rasterizer_discard */
299 VkSampleCountFlagBits samples
;
300 bool use_color_attachments
;
301 bool use_dual_src_blend
;
302 uint32_t color_attachment_count
;
303 VkFormat color_attachment_formats
[MAX_RTS
];
304 VkFormat depth_attachment_format
;
305 uint32_t render_components
;
308 static enum tu_dynamic_state_bits
309 tu_dynamic_state_bit(VkDynamicState state
)
312 case VK_DYNAMIC_STATE_VIEWPORT
:
313 return TU_DYNAMIC_VIEWPORT
;
314 case VK_DYNAMIC_STATE_SCISSOR
:
315 return TU_DYNAMIC_SCISSOR
;
316 case VK_DYNAMIC_STATE_LINE_WIDTH
:
317 return TU_DYNAMIC_LINE_WIDTH
;
318 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
319 return TU_DYNAMIC_DEPTH_BIAS
;
320 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
321 return TU_DYNAMIC_BLEND_CONSTANTS
;
322 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
323 return TU_DYNAMIC_DEPTH_BOUNDS
;
324 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
325 return TU_DYNAMIC_STENCIL_COMPARE_MASK
;
326 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
327 return TU_DYNAMIC_STENCIL_WRITE_MASK
;
328 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
329 return TU_DYNAMIC_STENCIL_REFERENCE
;
330 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT
:
331 return TU_DYNAMIC_SAMPLE_LOCATIONS
;
333 unreachable("invalid dynamic state");
338 static gl_shader_stage
339 tu_shader_stage(VkShaderStageFlagBits stage
)
342 case VK_SHADER_STAGE_VERTEX_BIT
:
343 return MESA_SHADER_VERTEX
;
344 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
345 return MESA_SHADER_TESS_CTRL
;
346 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
347 return MESA_SHADER_TESS_EVAL
;
348 case VK_SHADER_STAGE_GEOMETRY_BIT
:
349 return MESA_SHADER_GEOMETRY
;
350 case VK_SHADER_STAGE_FRAGMENT_BIT
:
351 return MESA_SHADER_FRAGMENT
;
352 case VK_SHADER_STAGE_COMPUTE_BIT
:
353 return MESA_SHADER_COMPUTE
;
355 unreachable("invalid VkShaderStageFlagBits");
356 return MESA_SHADER_NONE
;
361 tu_logic_op_reads_dst(VkLogicOp op
)
364 case VK_LOGIC_OP_CLEAR
:
365 case VK_LOGIC_OP_COPY
:
366 case VK_LOGIC_OP_COPY_INVERTED
:
367 case VK_LOGIC_OP_SET
:
375 tu_blend_factor_no_dst_alpha(VkBlendFactor factor
)
377 /* treat dst alpha as 1.0 and avoid reading it */
379 case VK_BLEND_FACTOR_DST_ALPHA
:
380 return VK_BLEND_FACTOR_ONE
;
381 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
382 return VK_BLEND_FACTOR_ZERO
;
388 static bool tu_blend_factor_is_dual_src(VkBlendFactor factor
)
391 case VK_BLEND_FACTOR_SRC1_COLOR
:
392 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
393 case VK_BLEND_FACTOR_SRC1_ALPHA
:
394 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
402 tu_blend_state_is_dual_src(const VkPipelineColorBlendStateCreateInfo
*info
)
407 for (unsigned i
= 0; i
< info
->attachmentCount
; i
++) {
408 const VkPipelineColorBlendAttachmentState
*blend
= &info
->pAttachments
[i
];
409 if (tu_blend_factor_is_dual_src(blend
->srcColorBlendFactor
) ||
410 tu_blend_factor_is_dual_src(blend
->dstColorBlendFactor
) ||
411 tu_blend_factor_is_dual_src(blend
->srcAlphaBlendFactor
) ||
412 tu_blend_factor_is_dual_src(blend
->dstAlphaBlendFactor
))
419 static enum pc_di_primtype
420 tu6_primtype(VkPrimitiveTopology topology
)
423 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
424 return DI_PT_POINTLIST
;
425 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
426 return DI_PT_LINELIST
;
427 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
428 return DI_PT_LINESTRIP
;
429 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
430 return DI_PT_TRILIST
;
431 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
432 return DI_PT_TRISTRIP
;
433 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
435 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
436 return DI_PT_LINE_ADJ
;
437 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
438 return DI_PT_LINESTRIP_ADJ
;
439 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
440 return DI_PT_TRI_ADJ
;
441 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
442 return DI_PT_TRISTRIP_ADJ
;
443 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
445 unreachable("invalid primitive topology");
450 static enum adreno_compare_func
451 tu6_compare_func(VkCompareOp op
)
454 case VK_COMPARE_OP_NEVER
:
456 case VK_COMPARE_OP_LESS
:
458 case VK_COMPARE_OP_EQUAL
:
460 case VK_COMPARE_OP_LESS_OR_EQUAL
:
462 case VK_COMPARE_OP_GREATER
:
464 case VK_COMPARE_OP_NOT_EQUAL
:
465 return FUNC_NOTEQUAL
;
466 case VK_COMPARE_OP_GREATER_OR_EQUAL
:
468 case VK_COMPARE_OP_ALWAYS
:
471 unreachable("invalid VkCompareOp");
476 static enum adreno_stencil_op
477 tu6_stencil_op(VkStencilOp op
)
480 case VK_STENCIL_OP_KEEP
:
482 case VK_STENCIL_OP_ZERO
:
484 case VK_STENCIL_OP_REPLACE
:
485 return STENCIL_REPLACE
;
486 case VK_STENCIL_OP_INCREMENT_AND_CLAMP
:
487 return STENCIL_INCR_CLAMP
;
488 case VK_STENCIL_OP_DECREMENT_AND_CLAMP
:
489 return STENCIL_DECR_CLAMP
;
490 case VK_STENCIL_OP_INVERT
:
491 return STENCIL_INVERT
;
492 case VK_STENCIL_OP_INCREMENT_AND_WRAP
:
493 return STENCIL_INCR_WRAP
;
494 case VK_STENCIL_OP_DECREMENT_AND_WRAP
:
495 return STENCIL_DECR_WRAP
;
497 unreachable("invalid VkStencilOp");
502 static enum a3xx_rop_code
503 tu6_rop(VkLogicOp op
)
506 case VK_LOGIC_OP_CLEAR
:
508 case VK_LOGIC_OP_AND
:
510 case VK_LOGIC_OP_AND_REVERSE
:
511 return ROP_AND_REVERSE
;
512 case VK_LOGIC_OP_COPY
:
514 case VK_LOGIC_OP_AND_INVERTED
:
515 return ROP_AND_INVERTED
;
516 case VK_LOGIC_OP_NO_OP
:
518 case VK_LOGIC_OP_XOR
:
522 case VK_LOGIC_OP_NOR
:
524 case VK_LOGIC_OP_EQUIVALENT
:
526 case VK_LOGIC_OP_INVERT
:
528 case VK_LOGIC_OP_OR_REVERSE
:
529 return ROP_OR_REVERSE
;
530 case VK_LOGIC_OP_COPY_INVERTED
:
531 return ROP_COPY_INVERTED
;
532 case VK_LOGIC_OP_OR_INVERTED
:
533 return ROP_OR_INVERTED
;
534 case VK_LOGIC_OP_NAND
:
536 case VK_LOGIC_OP_SET
:
539 unreachable("invalid VkLogicOp");
544 static enum adreno_rb_blend_factor
545 tu6_blend_factor(VkBlendFactor factor
)
548 case VK_BLEND_FACTOR_ZERO
:
550 case VK_BLEND_FACTOR_ONE
:
552 case VK_BLEND_FACTOR_SRC_COLOR
:
553 return FACTOR_SRC_COLOR
;
554 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
555 return FACTOR_ONE_MINUS_SRC_COLOR
;
556 case VK_BLEND_FACTOR_DST_COLOR
:
557 return FACTOR_DST_COLOR
;
558 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
:
559 return FACTOR_ONE_MINUS_DST_COLOR
;
560 case VK_BLEND_FACTOR_SRC_ALPHA
:
561 return FACTOR_SRC_ALPHA
;
562 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
563 return FACTOR_ONE_MINUS_SRC_ALPHA
;
564 case VK_BLEND_FACTOR_DST_ALPHA
:
565 return FACTOR_DST_ALPHA
;
566 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
567 return FACTOR_ONE_MINUS_DST_ALPHA
;
568 case VK_BLEND_FACTOR_CONSTANT_COLOR
:
569 return FACTOR_CONSTANT_COLOR
;
570 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
:
571 return FACTOR_ONE_MINUS_CONSTANT_COLOR
;
572 case VK_BLEND_FACTOR_CONSTANT_ALPHA
:
573 return FACTOR_CONSTANT_ALPHA
;
574 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
:
575 return FACTOR_ONE_MINUS_CONSTANT_ALPHA
;
576 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
577 return FACTOR_SRC_ALPHA_SATURATE
;
578 case VK_BLEND_FACTOR_SRC1_COLOR
:
579 return FACTOR_SRC1_COLOR
;
580 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
581 return FACTOR_ONE_MINUS_SRC1_COLOR
;
582 case VK_BLEND_FACTOR_SRC1_ALPHA
:
583 return FACTOR_SRC1_ALPHA
;
584 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
585 return FACTOR_ONE_MINUS_SRC1_ALPHA
;
587 unreachable("invalid VkBlendFactor");
592 static enum a3xx_rb_blend_opcode
593 tu6_blend_op(VkBlendOp op
)
596 case VK_BLEND_OP_ADD
:
597 return BLEND_DST_PLUS_SRC
;
598 case VK_BLEND_OP_SUBTRACT
:
599 return BLEND_SRC_MINUS_DST
;
600 case VK_BLEND_OP_REVERSE_SUBTRACT
:
601 return BLEND_DST_MINUS_SRC
;
602 case VK_BLEND_OP_MIN
:
603 return BLEND_MIN_DST_SRC
;
604 case VK_BLEND_OP_MAX
:
605 return BLEND_MAX_DST_SRC
;
607 unreachable("invalid VkBlendOp");
608 return BLEND_DST_PLUS_SRC
;
613 emit_xs_config(const struct ir3_shader_variant
*sh
)
616 return A6XX_SP_VS_CONFIG_ENABLED
|
617 COND(sh
->bindless_tex
, A6XX_SP_VS_CONFIG_BINDLESS_TEX
) |
618 COND(sh
->bindless_samp
, A6XX_SP_VS_CONFIG_BINDLESS_SAMP
) |
619 COND(sh
->bindless_ibo
, A6XX_SP_VS_CONFIG_BINDLESS_IBO
) |
620 COND(sh
->bindless_ubo
, A6XX_SP_VS_CONFIG_BINDLESS_UBO
);
627 tu6_emit_vs_config(struct tu_cs
*cs
, struct tu_shader
*shader
,
628 const struct ir3_shader_variant
*vs
)
630 uint32_t sp_vs_ctrl
=
631 A6XX_SP_VS_CTRL_REG0_THREADSIZE(FOUR_QUADS
) |
632 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs
->info
.max_reg
+ 1) |
633 A6XX_SP_VS_CTRL_REG0_MERGEDREGS
|
634 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs
->branchstack
);
636 sp_vs_ctrl
|= A6XX_SP_VS_CTRL_REG0_PIXLODENABLE
;
637 if (vs
->need_fine_derivatives
)
638 sp_vs_ctrl
|= A6XX_SP_VS_CTRL_REG0_DIFF_FINE
;
640 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_VS_CTRL_REG0
, 1);
641 tu_cs_emit(cs
, sp_vs_ctrl
);
643 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_VS_CONFIG
, 2);
644 tu_cs_emit(cs
, emit_xs_config(vs
));
645 tu_cs_emit(cs
, vs
->instrlen
);
647 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_VS_CNTL
, 1);
648 tu_cs_emit(cs
, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(vs
->constlen
, 4)) |
649 A6XX_HLSQ_VS_CNTL_ENABLED
);
653 tu6_emit_hs_config(struct tu_cs
*cs
, struct tu_shader
*shader
,
654 const struct ir3_shader_variant
*hs
)
656 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_HS_UNKNOWN_A831
, 1);
659 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_HS_CONFIG
, 2);
660 tu_cs_emit(cs
, emit_xs_config(hs
));
661 tu_cs_emit(cs
, hs
->instrlen
);
663 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_HS_CNTL
, 1);
664 tu_cs_emit(cs
, A6XX_HLSQ_HS_CNTL_CONSTLEN(align(hs
->constlen
, 4)));
668 tu6_emit_ds_config(struct tu_cs
*cs
, struct tu_shader
*shader
,
669 const struct ir3_shader_variant
*ds
)
671 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_DS_CONFIG
, 2);
672 tu_cs_emit(cs
, emit_xs_config(ds
));
673 tu_cs_emit(cs
, ds
->instrlen
);
675 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_DS_CNTL
, 1);
676 tu_cs_emit(cs
, A6XX_HLSQ_DS_CNTL_CONSTLEN(align(ds
->constlen
, 4)));
680 tu6_emit_gs_config(struct tu_cs
*cs
, struct tu_shader
*shader
,
681 const struct ir3_shader_variant
*gs
)
683 bool has_gs
= gs
->type
!= MESA_SHADER_NONE
;
684 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_GS_PRIM_SIZE
, 1);
687 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_GS_CONFIG
, 2);
688 tu_cs_emit(cs
, emit_xs_config(gs
));
689 tu_cs_emit(cs
, gs
->instrlen
);
691 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_GS_CNTL
, 1);
692 tu_cs_emit(cs
, COND(has_gs
, A6XX_HLSQ_GS_CNTL_ENABLED
) |
693 A6XX_HLSQ_GS_CNTL_CONSTLEN(align(gs
->constlen
, 4)));
697 tu6_emit_fs_config(struct tu_cs
*cs
, struct tu_shader
*shader
,
698 const struct ir3_shader_variant
*fs
)
700 uint32_t sp_fs_ctrl
=
701 A6XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS
) | 0x1000000 |
702 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs
->info
.max_reg
+ 1) |
703 A6XX_SP_FS_CTRL_REG0_MERGEDREGS
|
704 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(fs
->branchstack
);
705 if (fs
->total_in
> 0)
706 sp_fs_ctrl
|= A6XX_SP_FS_CTRL_REG0_VARYING
;
708 sp_fs_ctrl
|= A6XX_SP_FS_CTRL_REG0_PIXLODENABLE
;
709 if (fs
->need_fine_derivatives
)
710 sp_fs_ctrl
|= A6XX_SP_FS_CTRL_REG0_DIFF_FINE
;
712 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_CTRL_REG0
, 1);
713 tu_cs_emit(cs
, sp_fs_ctrl
);
715 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_CONFIG
, 2);
716 tu_cs_emit(cs
, emit_xs_config(fs
));
717 tu_cs_emit(cs
, fs
->instrlen
);
719 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_FS_CNTL
, 1);
720 tu_cs_emit(cs
, A6XX_HLSQ_FS_CNTL_CONSTLEN(align(fs
->constlen
, 4)) |
721 A6XX_HLSQ_FS_CNTL_ENABLED
);
725 tu6_emit_cs_config(struct tu_cs
*cs
, const struct tu_shader
*shader
,
726 const struct ir3_shader_variant
*v
)
728 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_UPDATE_CNTL
, 1);
729 tu_cs_emit(cs
, 0xff);
731 unsigned constlen
= align(v
->constlen
, 4);
732 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_CS_CNTL
, 1);
733 tu_cs_emit(cs
, A6XX_HLSQ_CS_CNTL_CONSTLEN(constlen
) |
734 A6XX_HLSQ_CS_CNTL_ENABLED
);
736 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_CS_CONFIG
, 2);
737 tu_cs_emit(cs
, emit_xs_config(v
));
738 tu_cs_emit(cs
, v
->instrlen
);
740 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_CS_CTRL_REG0
, 1);
741 tu_cs_emit(cs
, A6XX_SP_CS_CTRL_REG0_THREADSIZE(FOUR_QUADS
) |
742 A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(v
->info
.max_reg
+ 1) |
743 A6XX_SP_CS_CTRL_REG0_MERGEDREGS
|
744 A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(v
->branchstack
) |
745 COND(v
->need_pixlod
, A6XX_SP_CS_CTRL_REG0_PIXLODENABLE
) |
746 COND(v
->need_fine_derivatives
, A6XX_SP_CS_CTRL_REG0_DIFF_FINE
));
748 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_CS_UNKNOWN_A9B1
, 1);
749 tu_cs_emit(cs
, 0x41);
751 uint32_t local_invocation_id
=
752 ir3_find_sysval_regid(v
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
);
753 uint32_t work_group_id
=
754 ir3_find_sysval_regid(v
, SYSTEM_VALUE_WORK_GROUP_ID
);
756 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_CS_CNTL_0
, 2);
758 A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id
) |
759 A6XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
760 A6XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
761 A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id
));
762 tu_cs_emit(cs
, 0x2fc); /* HLSQ_CS_UNKNOWN_B998 */
766 tu6_emit_vs_system_values(struct tu_cs
*cs
,
767 const struct ir3_shader_variant
*vs
,
768 const struct ir3_shader_variant
*gs
,
769 bool primid_passthru
)
771 const uint32_t vertexid_regid
=
772 ir3_find_sysval_regid(vs
, SYSTEM_VALUE_VERTEX_ID
);
773 const uint32_t instanceid_regid
=
774 ir3_find_sysval_regid(vs
, SYSTEM_VALUE_INSTANCE_ID
);
775 const uint32_t primitiveid_regid
= gs
->type
!= MESA_SHADER_NONE
?
776 ir3_find_sysval_regid(gs
, SYSTEM_VALUE_PRIMITIVE_ID
) :
778 const uint32_t gsheader_regid
= gs
->type
!= MESA_SHADER_NONE
?
779 ir3_find_sysval_regid(gs
, SYSTEM_VALUE_GS_HEADER_IR3
) :
782 tu_cs_emit_pkt4(cs
, REG_A6XX_VFD_CONTROL_1
, 6);
783 tu_cs_emit(cs
, A6XX_VFD_CONTROL_1_REGID4VTX(vertexid_regid
) |
784 A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid
) |
785 A6XX_VFD_CONTROL_1_REGID4PRIMID(primitiveid_regid
) |
787 tu_cs_emit(cs
, 0x0000fcfc); /* VFD_CONTROL_2 */
788 tu_cs_emit(cs
, 0xfcfcfcfc); /* VFD_CONTROL_3 */
789 tu_cs_emit(cs
, 0x000000fc); /* VFD_CONTROL_4 */
790 tu_cs_emit(cs
, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gsheader_regid
) |
791 0xfc00); /* VFD_CONTROL_5 */
792 tu_cs_emit(cs
, COND(primid_passthru
, A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU
)); /* VFD_CONTROL_6 */
795 /* Add any missing varyings needed for stream-out. Otherwise varyings not
796 * used by fragment shader will be stripped out.
799 tu6_link_streamout(struct ir3_shader_linkage
*l
,
800 const struct ir3_shader_variant
*v
)
802 const struct ir3_stream_output_info
*info
= &v
->shader
->stream_output
;
805 * First, any stream-out varyings not already in linkage map (ie. also
806 * consumed by frag shader) need to be added:
808 for (unsigned i
= 0; i
< info
->num_outputs
; i
++) {
809 const struct ir3_stream_output
*out
= &info
->output
[i
];
811 (1 << (out
->num_components
+ out
->start_component
)) - 1;
812 unsigned k
= out
->register_index
;
813 unsigned idx
, nextloc
= 0;
815 /* psize/pos need to be the last entries in linkage map, and will
816 * get added link_stream_out, so skip over them:
818 if (v
->outputs
[k
].slot
== VARYING_SLOT_PSIZ
||
819 v
->outputs
[k
].slot
== VARYING_SLOT_POS
)
822 for (idx
= 0; idx
< l
->cnt
; idx
++) {
823 if (l
->var
[idx
].regid
== v
->outputs
[k
].regid
)
825 nextloc
= MAX2(nextloc
, l
->var
[idx
].loc
+ 4);
828 /* add if not already in linkage map: */
830 ir3_link_add(l
, v
->outputs
[k
].regid
, compmask
, nextloc
);
832 /* expand component-mask if needed, ie streaming out all components
833 * but frag shader doesn't consume all components:
835 if (compmask
& ~l
->var
[idx
].compmask
) {
836 l
->var
[idx
].compmask
|= compmask
;
837 l
->max_loc
= MAX2(l
->max_loc
, l
->var
[idx
].loc
+
838 util_last_bit(l
->var
[idx
].compmask
));
844 tu6_setup_streamout(const struct ir3_shader_variant
*v
,
845 struct ir3_shader_linkage
*l
, struct tu_streamout_state
*tf
)
847 const struct ir3_stream_output_info
*info
= &v
->shader
->stream_output
;
849 memset(tf
, 0, sizeof(*tf
));
851 tf
->prog_count
= align(l
->max_loc
, 2) / 2;
853 debug_assert(tf
->prog_count
< ARRAY_SIZE(tf
->prog
));
855 /* set stride info to the streamout state */
856 for (unsigned i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++)
857 tf
->stride
[i
] = info
->stride
[i
];
859 for (unsigned i
= 0; i
< info
->num_outputs
; i
++) {
860 const struct ir3_stream_output
*out
= &info
->output
[i
];
861 unsigned k
= out
->register_index
;
864 /* Skip it, if there's an unused reg in the middle of outputs. */
865 if (v
->outputs
[k
].regid
== INVALID_REG
)
868 tf
->ncomp
[out
->output_buffer
] += out
->num_components
;
870 /* linkage map sorted by order frag shader wants things, so
871 * a bit less ideal here..
873 for (idx
= 0; idx
< l
->cnt
; idx
++)
874 if (l
->var
[idx
].regid
== v
->outputs
[k
].regid
)
877 debug_assert(idx
< l
->cnt
);
879 for (unsigned j
= 0; j
< out
->num_components
; j
++) {
880 unsigned c
= j
+ out
->start_component
;
881 unsigned loc
= l
->var
[idx
].loc
+ c
;
882 unsigned off
= j
+ out
->dst_offset
; /* in dwords */
885 tf
->prog
[loc
/2] |= A6XX_VPC_SO_PROG_B_EN
|
886 A6XX_VPC_SO_PROG_B_BUF(out
->output_buffer
) |
887 A6XX_VPC_SO_PROG_B_OFF(off
* 4);
889 tf
->prog
[loc
/2] |= A6XX_VPC_SO_PROG_A_EN
|
890 A6XX_VPC_SO_PROG_A_BUF(out
->output_buffer
) |
891 A6XX_VPC_SO_PROG_A_OFF(off
* 4);
896 tf
->vpc_so_buf_cntl
= A6XX_VPC_SO_BUF_CNTL_ENABLE
|
897 COND(tf
->ncomp
[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0
) |
898 COND(tf
->ncomp
[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1
) |
899 COND(tf
->ncomp
[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2
) |
900 COND(tf
->ncomp
[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3
);
904 tu6_emit_const(struct tu_cs
*cs
, uint32_t opcode
, uint32_t base
,
905 enum a6xx_state_block block
, uint32_t offset
,
906 uint32_t size
, uint32_t *dwords
) {
907 assert(size
% 4 == 0);
909 tu_cs_emit_pkt7(cs
, opcode
, 3 + size
);
910 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(base
) |
911 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
912 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
913 CP_LOAD_STATE6_0_STATE_BLOCK(block
) |
914 CP_LOAD_STATE6_0_NUM_UNIT(size
/ 4));
916 tu_cs_emit(cs
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
917 tu_cs_emit(cs
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
918 dwords
= (uint32_t *)&((uint8_t *)dwords
)[offset
];
920 tu_cs_emit_array(cs
, dwords
, size
);
924 tu6_emit_link_map(struct tu_cs
*cs
,
925 const struct ir3_shader_variant
*producer
,
926 const struct ir3_shader_variant
*consumer
) {
927 const struct ir3_const_state
*const_state
= &consumer
->shader
->const_state
;
928 uint32_t base
= const_state
->offsets
.primitive_map
;
929 uint32_t patch_locs
[MAX_VARYING
] = { }, num_loc
;
930 num_loc
= ir3_link_geometry_stages(producer
, consumer
, patch_locs
);
931 int size
= DIV_ROUND_UP(num_loc
, 4);
933 size
= (MIN2(size
+ base
, consumer
->constlen
) - base
) * 4;
937 tu6_emit_const(cs
, CP_LOAD_STATE6_GEOM
, base
, SB6_GS_SHADER
, 0, size
,
942 gl_primitive_to_tess(uint16_t primitive
) {
948 case GL_TRIANGLE_STRIP
:
956 tu6_emit_vpc(struct tu_cs
*cs
,
957 const struct ir3_shader_variant
*vs
,
958 const struct ir3_shader_variant
*gs
,
959 const struct ir3_shader_variant
*fs
,
961 struct tu_streamout_state
*tf
)
963 bool has_gs
= gs
->type
!= MESA_SHADER_NONE
;
964 const struct ir3_shader_variant
*last_shader
= has_gs
? gs
: vs
;
965 struct ir3_shader_linkage linkage
= { 0 };
966 ir3_link_shaders(&linkage
, last_shader
, fs
, true);
968 if (last_shader
->shader
->stream_output
.num_outputs
)
969 tu6_link_streamout(&linkage
, last_shader
);
971 /* We do this after linking shaders in order to know whether PrimID
972 * passthrough needs to be enabled.
974 bool primid_passthru
= linkage
.primid_loc
!= 0xff;
975 tu6_emit_vs_system_values(cs
, vs
, gs
, primid_passthru
);
977 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_VAR_DISABLE(0), 4);
978 tu_cs_emit(cs
, ~linkage
.varmask
[0]);
979 tu_cs_emit(cs
, ~linkage
.varmask
[1]);
980 tu_cs_emit(cs
, ~linkage
.varmask
[2]);
981 tu_cs_emit(cs
, ~linkage
.varmask
[3]);
983 /* a6xx finds position/pointsize at the end */
984 const uint32_t position_regid
=
985 ir3_find_output_regid(last_shader
, VARYING_SLOT_POS
);
986 const uint32_t pointsize_regid
=
987 ir3_find_output_regid(last_shader
, VARYING_SLOT_PSIZ
);
988 const uint32_t layer_regid
= has_gs
?
989 ir3_find_output_regid(gs
, VARYING_SLOT_LAYER
) : regid(63, 0);
991 uint32_t pointsize_loc
= 0xff, position_loc
= 0xff, layer_loc
= 0xff;
992 if (layer_regid
!= regid(63, 0)) {
993 layer_loc
= linkage
.max_loc
;
994 ir3_link_add(&linkage
, layer_regid
, 0x1, linkage
.max_loc
);
996 if (position_regid
!= regid(63, 0)) {
997 position_loc
= linkage
.max_loc
;
998 ir3_link_add(&linkage
, position_regid
, 0xf, linkage
.max_loc
);
1000 if (pointsize_regid
!= regid(63, 0)) {
1001 pointsize_loc
= linkage
.max_loc
;
1002 ir3_link_add(&linkage
, pointsize_regid
, 0x1, linkage
.max_loc
);
1005 if (last_shader
->shader
->stream_output
.num_outputs
)
1006 tu6_setup_streamout(last_shader
, &linkage
, tf
);
1008 /* map outputs of the last shader to VPC */
1009 assert(linkage
.cnt
<= 32);
1010 const uint32_t sp_out_count
= DIV_ROUND_UP(linkage
.cnt
, 2);
1011 const uint32_t sp_vpc_dst_count
= DIV_ROUND_UP(linkage
.cnt
, 4);
1012 uint32_t sp_out
[16];
1013 uint32_t sp_vpc_dst
[8];
1014 for (uint32_t i
= 0; i
< linkage
.cnt
; i
++) {
1015 ((uint16_t *) sp_out
)[i
] =
1016 A6XX_SP_VS_OUT_REG_A_REGID(linkage
.var
[i
].regid
) |
1017 A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage
.var
[i
].compmask
);
1018 ((uint8_t *) sp_vpc_dst
)[i
] =
1019 A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage
.var
[i
].loc
);
1023 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_GS_OUT_REG(0), sp_out_count
);
1025 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_VS_OUT_REG(0), sp_out_count
);
1026 tu_cs_emit_array(cs
, sp_out
, sp_out_count
);
1029 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_GS_VPC_DST_REG(0), sp_vpc_dst_count
);
1031 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_VS_VPC_DST_REG(0), sp_vpc_dst_count
);
1032 tu_cs_emit_array(cs
, sp_vpc_dst
, sp_vpc_dst_count
);
1034 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_PRIMID_CNTL
, 1);
1035 tu_cs_emit(cs
, COND(primid_passthru
, A6XX_PC_PRIMID_CNTL_PRIMID_PASSTHRU
));
1037 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_CNTL_0
, 1);
1038 tu_cs_emit(cs
, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs
->total_in
) |
1039 (fs
->total_in
> 0 ? A6XX_VPC_CNTL_0_VARYING
: 0) |
1040 A6XX_VPC_CNTL_0_PRIMIDLOC(linkage
.primid_loc
) |
1041 A6XX_VPC_CNTL_0_UNKLOC(0xff));
1043 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_PACK
, 1);
1044 tu_cs_emit(cs
, A6XX_VPC_PACK_POSITIONLOC(position_loc
) |
1045 A6XX_VPC_PACK_PSIZELOC(pointsize_loc
) |
1046 A6XX_VPC_PACK_STRIDE_IN_VPC(linkage
.max_loc
));
1049 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_GS_CTRL_REG0
, 1);
1050 tu_cs_emit(cs
, A6XX_SP_GS_CTRL_REG0_THREADSIZE(TWO_QUADS
) |
1051 A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(gs
->info
.max_reg
+ 1) |
1052 A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(gs
->branchstack
) |
1053 COND(gs
->need_pixlod
, A6XX_SP_GS_CTRL_REG0_PIXLODENABLE
));
1055 tu6_emit_link_map(cs
, vs
, gs
);
1057 uint32_t primitive_regid
=
1058 ir3_find_sysval_regid(gs
, SYSTEM_VALUE_PRIMITIVE_ID
);
1059 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_PACK_GS
, 1);
1060 tu_cs_emit(cs
, A6XX_VPC_PACK_GS_POSITIONLOC(position_loc
) |
1061 A6XX_VPC_PACK_GS_PSIZELOC(pointsize_loc
) |
1062 A6XX_VPC_PACK_GS_STRIDE_IN_VPC(linkage
.max_loc
));
1064 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_UNKNOWN_9105
, 1);
1065 tu_cs_emit(cs
, A6XX_VPC_UNKNOWN_9105_LAYERLOC(layer_loc
) | 0xff00);
1067 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_UNKNOWN_809C
, 1);
1068 tu_cs_emit(cs
, CONDREG(layer_regid
,
1069 A6XX_GRAS_UNKNOWN_809C_GS_WRITES_LAYER
));
1071 uint32_t flags_regid
= ir3_find_output_regid(gs
,
1072 VARYING_SLOT_GS_VERTEX_FLAGS_IR3
);
1074 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_PRIMITIVE_CNTL_GS
, 1);
1075 tu_cs_emit(cs
, A6XX_SP_PRIMITIVE_CNTL_GS_GSOUT(linkage
.cnt
) |
1076 A6XX_SP_PRIMITIVE_CNTL_GS_FLAGS_REGID(flags_regid
));
1078 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_2
, 1);
1079 tu_cs_emit(cs
, A6XX_PC_PRIMITIVE_CNTL_2_STRIDE_IN_VPC(linkage
.max_loc
) |
1080 CONDREG(pointsize_regid
, A6XX_PC_PRIMITIVE_CNTL_2_PSIZE
) |
1081 CONDREG(layer_regid
, A6XX_PC_PRIMITIVE_CNTL_2_LAYER
) |
1082 CONDREG(primitive_regid
, A6XX_PC_PRIMITIVE_CNTL_2_PRIMITIVE_ID
));
1084 uint32_t vertices_out
= gs
->shader
->nir
->info
.gs
.vertices_out
- 1;
1086 gl_primitive_to_tess(gs
->shader
->nir
->info
.gs
.output_primitive
);
1087 uint32_t invocations
= gs
->shader
->nir
->info
.gs
.invocations
- 1;
1088 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_5
, 1);
1090 A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(vertices_out
) |
1091 A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(output
) |
1092 A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(invocations
));
1094 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_3
, 1);
1097 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_UNKNOWN_8003
, 1);
1100 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_UNKNOWN_9100
, 1);
1101 tu_cs_emit(cs
, 0xff);
1103 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_UNKNOWN_9102
, 1);
1104 tu_cs_emit(cs
, 0xffff00);
1106 /* Size of per-primitive alloction in ldlw memory in vec4s. */
1107 uint32_t vec4_size
=
1108 gs
->shader
->nir
->info
.gs
.vertices_in
*
1109 DIV_ROUND_UP(vs
->shader
->output_size
, 4);
1110 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_6
, 1);
1111 tu_cs_emit(cs
, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size
));
1113 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_UNKNOWN_9B07
, 1);
1116 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_GS_PRIM_SIZE
, 1);
1117 tu_cs_emit(cs
, vs
->shader
->output_size
);
1120 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_PRIMITIVE_CNTL
, 1);
1121 tu_cs_emit(cs
, A6XX_SP_PRIMITIVE_CNTL_VSOUT(linkage
.cnt
));
1123 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_1
, 1);
1124 tu_cs_emit(cs
, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(linkage
.max_loc
) |
1125 (last_shader
->writes_psize
? A6XX_PC_PRIMITIVE_CNTL_1_PSIZE
: 0));
1129 tu6_vpc_varying_mode(const struct ir3_shader_variant
*fs
,
1131 uint8_t *interp_mode
,
1132 uint8_t *ps_repl_mode
)
1146 PS_REPL_ONE_MINUS_T
= 3,
1149 const uint32_t compmask
= fs
->inputs
[index
].compmask
;
1151 /* NOTE: varyings are packed, so if compmask is 0xb then first, second, and
1152 * fourth component occupy three consecutive varying slots
1157 if (fs
->inputs
[index
].slot
== VARYING_SLOT_PNTC
) {
1158 if (compmask
& 0x1) {
1159 *ps_repl_mode
|= PS_REPL_S
<< shift
;
1162 if (compmask
& 0x2) {
1163 *ps_repl_mode
|= PS_REPL_T
<< shift
;
1166 if (compmask
& 0x4) {
1167 *interp_mode
|= INTERP_ZERO
<< shift
;
1170 if (compmask
& 0x8) {
1171 *interp_mode
|= INTERP_ONE
<< 6;
1174 } else if ((fs
->inputs
[index
].interpolate
== INTERP_MODE_FLAT
) ||
1175 fs
->inputs
[index
].rasterflat
) {
1176 for (int i
= 0; i
< 4; i
++) {
1177 if (compmask
& (1 << i
)) {
1178 *interp_mode
|= INTERP_FLAT
<< shift
;
1188 tu6_emit_vpc_varying_modes(struct tu_cs
*cs
,
1189 const struct ir3_shader_variant
*fs
,
1192 uint32_t interp_modes
[8] = { 0 };
1193 uint32_t ps_repl_modes
[8] = { 0 };
1195 if (!binning_pass
) {
1197 (i
= ir3_next_varying(fs
, i
)) < (int) fs
->inputs_count
;) {
1199 /* get the mode for input i */
1200 uint8_t interp_mode
;
1201 uint8_t ps_repl_mode
;
1203 tu6_vpc_varying_mode(fs
, i
, &interp_mode
, &ps_repl_mode
);
1205 /* OR the mode into the array */
1206 const uint32_t inloc
= fs
->inputs
[i
].inloc
* 2;
1207 uint32_t n
= inloc
/ 32;
1208 uint32_t shift
= inloc
% 32;
1209 interp_modes
[n
] |= interp_mode
<< shift
;
1210 ps_repl_modes
[n
] |= ps_repl_mode
<< shift
;
1211 if (shift
+ bits
> 32) {
1215 interp_modes
[n
] |= interp_mode
>> shift
;
1216 ps_repl_modes
[n
] |= ps_repl_mode
>> shift
;
1221 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
1222 tu_cs_emit_array(cs
, interp_modes
, 8);
1224 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
1225 tu_cs_emit_array(cs
, ps_repl_modes
, 8);
1229 tu6_emit_fs_inputs(struct tu_cs
*cs
, const struct ir3_shader_variant
*fs
)
1231 uint32_t face_regid
, coord_regid
, zwcoord_regid
, samp_id_regid
;
1232 uint32_t ij_pix_regid
, ij_samp_regid
, ij_cent_regid
, ij_size_regid
;
1233 uint32_t smask_in_regid
;
1235 bool sample_shading
= fs
->per_samp
; /* TODO | key->sample_shading; */
1236 bool enable_varyings
= fs
->total_in
> 0;
1238 samp_id_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_SAMPLE_ID
);
1239 smask_in_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_SAMPLE_MASK_IN
);
1240 face_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_FRONT_FACE
);
1241 coord_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_FRAG_COORD
);
1242 zwcoord_regid
= VALIDREG(coord_regid
) ? coord_regid
+ 2 : regid(63, 0);
1243 ij_pix_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL
);
1244 ij_samp_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE
);
1245 ij_cent_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID
);
1246 ij_size_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE
);
1248 if (fs
->num_sampler_prefetch
> 0) {
1249 assert(VALIDREG(ij_pix_regid
));
1250 /* also, it seems like ij_pix is *required* to be r0.x */
1251 assert(ij_pix_regid
== regid(0, 0));
1254 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_PREFETCH_CNTL
, 1 + fs
->num_sampler_prefetch
);
1255 tu_cs_emit(cs
, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs
->num_sampler_prefetch
) |
1256 A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
1258 for (int i
= 0; i
< fs
->num_sampler_prefetch
; i
++) {
1259 const struct ir3_sampler_prefetch
*prefetch
= &fs
->sampler_prefetch
[i
];
1260 tu_cs_emit(cs
, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch
->src
) |
1261 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch
->samp_id
) |
1262 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch
->tex_id
) |
1263 A6XX_SP_FS_PREFETCH_CMD_DST(prefetch
->dst
) |
1264 A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch
->wrmask
) |
1265 COND(prefetch
->half_precision
, A6XX_SP_FS_PREFETCH_CMD_HALF
) |
1266 A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch
->cmd
));
1269 if (fs
->num_sampler_prefetch
> 0) {
1270 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(0), fs
->num_sampler_prefetch
);
1271 for (int i
= 0; i
< fs
->num_sampler_prefetch
; i
++) {
1272 const struct ir3_sampler_prefetch
*prefetch
= &fs
->sampler_prefetch
[i
];
1274 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(prefetch
->samp_bindless_id
) |
1275 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(prefetch
->tex_bindless_id
));
1279 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_CONTROL_1_REG
, 5);
1280 tu_cs_emit(cs
, 0x7);
1281 tu_cs_emit(cs
, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid
) |
1282 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid
) |
1283 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid
) |
1284 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid
));
1285 tu_cs_emit(cs
, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid
) |
1286 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid
) |
1288 tu_cs_emit(cs
, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid
) |
1289 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid
) |
1290 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid
) |
1292 tu_cs_emit(cs
, 0xfc);
1294 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_UNKNOWN_B980
, 1);
1295 tu_cs_emit(cs
, enable_varyings
? 3 : 1);
1297 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_CNTL
, 1);
1299 CONDREG(ij_pix_regid
, A6XX_GRAS_CNTL_VARYING
) |
1300 CONDREG(ij_cent_regid
, A6XX_GRAS_CNTL_CENTROID
) |
1301 CONDREG(ij_samp_regid
, A6XX_GRAS_CNTL_PERSAMP_VARYING
) |
1302 COND(VALIDREG(ij_size_regid
) && !sample_shading
, A6XX_GRAS_CNTL_SIZE
) |
1303 COND(VALIDREG(ij_size_regid
) && sample_shading
, A6XX_GRAS_CNTL_SIZE_PERSAMP
) |
1304 COND(fs
->fragcoord_compmask
!= 0, A6XX_GRAS_CNTL_SIZE
|
1305 A6XX_GRAS_CNTL_COORD_MASK(fs
->fragcoord_compmask
)) |
1306 COND(fs
->frag_face
, A6XX_GRAS_CNTL_SIZE
));
1308 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_RENDER_CONTROL0
, 2);
1310 CONDREG(ij_pix_regid
, A6XX_RB_RENDER_CONTROL0_VARYING
) |
1311 CONDREG(ij_cent_regid
, A6XX_RB_RENDER_CONTROL0_CENTROID
) |
1312 CONDREG(ij_samp_regid
, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING
) |
1313 COND(enable_varyings
, A6XX_RB_RENDER_CONTROL0_UNK10
) |
1314 COND(VALIDREG(ij_size_regid
) && !sample_shading
, A6XX_RB_RENDER_CONTROL0_SIZE
) |
1315 COND(VALIDREG(ij_size_regid
) && sample_shading
, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP
) |
1316 COND(fs
->fragcoord_compmask
!= 0, A6XX_RB_RENDER_CONTROL0_SIZE
|
1317 A6XX_RB_RENDER_CONTROL0_COORD_MASK(fs
->fragcoord_compmask
)) |
1318 COND(fs
->frag_face
, A6XX_RB_RENDER_CONTROL0_SIZE
));
1320 CONDREG(smask_in_regid
, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK
) |
1321 CONDREG(samp_id_regid
, A6XX_RB_RENDER_CONTROL1_SAMPLEID
) |
1322 CONDREG(ij_size_regid
, A6XX_RB_RENDER_CONTROL1_SIZE
) |
1323 COND(fs
->frag_face
, A6XX_RB_RENDER_CONTROL1_FACENESS
));
1325 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_SAMPLE_CNTL
, 1);
1326 tu_cs_emit(cs
, COND(sample_shading
, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE
));
1328 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_UNKNOWN_8101
, 1);
1329 tu_cs_emit(cs
, COND(sample_shading
, 0x6)); // XXX
1331 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SAMPLE_CNTL
, 1);
1332 tu_cs_emit(cs
, COND(sample_shading
, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE
));
1336 tu6_emit_fs_outputs(struct tu_cs
*cs
,
1337 const struct ir3_shader_variant
*fs
,
1338 uint32_t mrt_count
, bool dual_src_blend
,
1339 uint32_t render_components
)
1341 uint32_t smask_regid
, posz_regid
;
1343 posz_regid
= ir3_find_output_regid(fs
, FRAG_RESULT_DEPTH
);
1344 smask_regid
= ir3_find_output_regid(fs
, FRAG_RESULT_SAMPLE_MASK
);
1346 uint32_t fragdata_regid
[8];
1347 if (fs
->color0_mrt
) {
1348 fragdata_regid
[0] = ir3_find_output_regid(fs
, FRAG_RESULT_COLOR
);
1349 for (uint32_t i
= 1; i
< ARRAY_SIZE(fragdata_regid
); i
++)
1350 fragdata_regid
[i
] = fragdata_regid
[0];
1352 for (uint32_t i
= 0; i
< ARRAY_SIZE(fragdata_regid
); i
++)
1353 fragdata_regid
[i
] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA0
+ i
);
1356 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_OUTPUT_CNTL0
, 2);
1357 tu_cs_emit(cs
, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid
) |
1358 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid
) |
1359 COND(dual_src_blend
, A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE
) |
1361 tu_cs_emit(cs
, A6XX_SP_FS_OUTPUT_CNTL1_MRT(mrt_count
));
1363 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
1364 for (uint32_t i
= 0; i
< ARRAY_SIZE(fragdata_regid
); i
++) {
1365 // TODO we could have a mix of half and full precision outputs,
1366 // we really need to figure out half-precision from IR3_REG_HALF
1367 tu_cs_emit(cs
, A6XX_SP_FS_OUTPUT_REG_REGID(fragdata_regid
[i
]) |
1368 (false ? A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION
: 0));
1372 A6XX_SP_FS_RENDER_COMPONENTS(.dword
= render_components
));
1374 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_FS_OUTPUT_CNTL0
, 2);
1375 tu_cs_emit(cs
, COND(fs
->writes_pos
, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z
) |
1376 COND(fs
->writes_smask
, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK
) |
1377 COND(dual_src_blend
, A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE
));
1378 tu_cs_emit(cs
, A6XX_RB_FS_OUTPUT_CNTL1_MRT(mrt_count
));
1381 A6XX_RB_RENDER_COMPONENTS(.dword
= render_components
));
1383 enum a6xx_ztest_mode zmode
;
1385 if (fs
->no_earlyz
|| fs
->has_kill
|| fs
->writes_pos
) {
1386 zmode
= A6XX_LATE_Z
;
1388 zmode
= A6XX_EARLY_Z
;
1391 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL
, 1);
1392 tu_cs_emit(cs
, A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(zmode
));
1394 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_PLANE_CNTL
, 1);
1395 tu_cs_emit(cs
, A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(zmode
));
1399 tu6_emit_shader_object(struct tu_cs
*cs
,
1400 gl_shader_stage stage
,
1401 const struct ir3_shader_variant
*variant
,
1402 const struct tu_bo
*binary_bo
,
1403 uint32_t binary_offset
)
1407 enum a6xx_state_block sb
;
1409 case MESA_SHADER_VERTEX
:
1410 reg
= REG_A6XX_SP_VS_OBJ_START_LO
;
1411 opcode
= CP_LOAD_STATE6_GEOM
;
1414 case MESA_SHADER_TESS_CTRL
:
1415 reg
= REG_A6XX_SP_HS_OBJ_START_LO
;
1416 opcode
= CP_LOAD_STATE6_GEOM
;
1419 case MESA_SHADER_TESS_EVAL
:
1420 reg
= REG_A6XX_SP_DS_OBJ_START_LO
;
1421 opcode
= CP_LOAD_STATE6_GEOM
;
1424 case MESA_SHADER_GEOMETRY
:
1425 reg
= REG_A6XX_SP_GS_OBJ_START_LO
;
1426 opcode
= CP_LOAD_STATE6_GEOM
;
1429 case MESA_SHADER_FRAGMENT
:
1430 reg
= REG_A6XX_SP_FS_OBJ_START_LO
;
1431 opcode
= CP_LOAD_STATE6_FRAG
;
1434 case MESA_SHADER_COMPUTE
:
1435 reg
= REG_A6XX_SP_CS_OBJ_START_LO
;
1436 opcode
= CP_LOAD_STATE6_FRAG
;
1440 unreachable("invalid gl_shader_stage");
1441 opcode
= CP_LOAD_STATE6_GEOM
;
1446 if (!variant
->instrlen
) {
1447 tu_cs_emit_pkt4(cs
, reg
, 2);
1448 tu_cs_emit_qw(cs
, 0);
1452 assert(variant
->type
== stage
);
1454 const uint64_t binary_iova
= binary_bo
->iova
+ binary_offset
;
1455 assert((binary_iova
& 0xf) == 0);
1456 /* note: it looks like HW might try to read a few instructions beyond the instrlen size
1457 * of the shader. this could be a potential source of problems at some point
1458 * possibly this doesn't happen if shader iova is aligned enough (to 4k for example)
1461 tu_cs_emit_pkt4(cs
, reg
, 2);
1462 tu_cs_emit_qw(cs
, binary_iova
);
1464 /* always indirect */
1465 const bool indirect
= true;
1467 tu_cs_emit_pkt7(cs
, opcode
, 3);
1468 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(0) |
1469 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER
) |
1470 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
1471 CP_LOAD_STATE6_0_STATE_BLOCK(sb
) |
1472 CP_LOAD_STATE6_0_NUM_UNIT(variant
->instrlen
));
1473 tu_cs_emit_qw(cs
, binary_iova
);
1475 const void *binary
= binary_bo
->map
+ binary_offset
;
1477 tu_cs_emit_pkt7(cs
, opcode
, 3 + variant
->info
.sizedwords
);
1478 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(0) |
1479 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER
) |
1480 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
1481 CP_LOAD_STATE6_0_STATE_BLOCK(sb
) |
1482 CP_LOAD_STATE6_0_NUM_UNIT(variant
->instrlen
));
1483 tu_cs_emit_qw(cs
, 0);
1484 tu_cs_emit_array(cs
, binary
, variant
->info
.sizedwords
);
1489 tu6_emit_immediates(struct tu_cs
*cs
, const struct ir3_shader_variant
*v
,
1490 uint32_t opcode
, enum a6xx_state_block block
)
1496 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
1497 uint32_t base
= const_state
->offsets
.immediate
;
1498 int size
= const_state
->immediates_count
;
1500 /* truncate size to avoid writing constants that shader
1503 size
= MIN2(size
+ base
, v
->constlen
) - base
;
1508 tu_cs_emit_pkt7(cs
, opcode
, 3 + size
* 4);
1509 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(base
) |
1510 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
1511 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
1512 CP_LOAD_STATE6_0_STATE_BLOCK(block
) |
1513 CP_LOAD_STATE6_0_NUM_UNIT(size
));
1514 tu_cs_emit(cs
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
1515 tu_cs_emit(cs
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
1517 for (unsigned i
= 0; i
< size
; i
++) {
1518 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[0]);
1519 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[1]);
1520 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[2]);
1521 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[3]);
1526 tu6_emit_geometry_consts(struct tu_cs
*cs
,
1527 const struct ir3_shader_variant
*vs
,
1528 const struct ir3_shader_variant
*gs
) {
1529 unsigned num_vertices
= gs
->shader
->nir
->info
.gs
.vertices_in
;
1531 uint32_t params
[4] = {
1532 vs
->shader
->output_size
* num_vertices
* 4, /* primitive stride */
1533 vs
->shader
->output_size
* 4, /* vertex stride */
1537 uint32_t vs_base
= vs
->shader
->const_state
.offsets
.primitive_param
;
1538 tu6_emit_const(cs
, CP_LOAD_STATE6_GEOM
, vs_base
, SB6_VS_SHADER
, 0,
1539 ARRAY_SIZE(params
), params
);
1541 uint32_t gs_base
= gs
->shader
->const_state
.offsets
.primitive_param
;
1542 tu6_emit_const(cs
, CP_LOAD_STATE6_GEOM
, gs_base
, SB6_GS_SHADER
, 0,
1543 ARRAY_SIZE(params
), params
);
1547 tu6_emit_program(struct tu_cs
*cs
,
1548 const struct tu_pipeline_builder
*builder
,
1549 const struct tu_bo
*binary_bo
,
1551 struct tu_streamout_state
*tf
)
1553 static const struct ir3_shader_variant dummy_variant
= {
1554 .type
= MESA_SHADER_NONE
1556 assert(builder
->shaders
[MESA_SHADER_VERTEX
]);
1557 const struct ir3_shader_variant
*vs
=
1558 &builder
->shaders
[MESA_SHADER_VERTEX
]->variants
[0];
1559 const struct ir3_shader_variant
*hs
=
1560 builder
->shaders
[MESA_SHADER_TESS_CTRL
]
1561 ? &builder
->shaders
[MESA_SHADER_TESS_CTRL
]->variants
[0]
1563 const struct ir3_shader_variant
*ds
=
1564 builder
->shaders
[MESA_SHADER_TESS_EVAL
]
1565 ? &builder
->shaders
[MESA_SHADER_TESS_EVAL
]->variants
[0]
1567 const struct ir3_shader_variant
*gs
=
1568 builder
->shaders
[MESA_SHADER_GEOMETRY
]
1569 ? &builder
->shaders
[MESA_SHADER_GEOMETRY
]->variants
[0]
1571 const struct ir3_shader_variant
*fs
=
1572 builder
->shaders
[MESA_SHADER_FRAGMENT
]
1573 ? &builder
->shaders
[MESA_SHADER_FRAGMENT
]->variants
[0]
1575 uint32_t vs_offset
= builder
->shader_offsets
[MESA_SHADER_VERTEX
];
1576 bool has_gs
= gs
->type
!= MESA_SHADER_NONE
;
1579 /* if we have streamout, use full VS in binning pass, as the
1580 * binning pass VS will have outputs on other than position/psize
1583 * GS also can have streamout, but we completely disable the
1584 * the binning pass variant when GS is present because we don't
1585 * support compiling correct binning pass variants with GS
1587 if (vs
->shader
->stream_output
.num_outputs
== 0 && !has_gs
) {
1588 vs
= &builder
->shaders
[MESA_SHADER_VERTEX
]->variants
[1];
1589 vs_offset
= builder
->binning_vs_offset
;
1591 fs
= &dummy_variant
;
1594 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_UPDATE_CNTL
, 1);
1595 tu_cs_emit(cs
, 0xff); /* XXX */
1597 tu6_emit_vs_config(cs
, builder
->shaders
[MESA_SHADER_VERTEX
], vs
);
1598 tu6_emit_hs_config(cs
, builder
->shaders
[MESA_SHADER_TESS_CTRL
], hs
);
1599 tu6_emit_ds_config(cs
, builder
->shaders
[MESA_SHADER_TESS_EVAL
], ds
);
1600 tu6_emit_gs_config(cs
, builder
->shaders
[MESA_SHADER_GEOMETRY
], gs
);
1601 tu6_emit_fs_config(cs
, builder
->shaders
[MESA_SHADER_FRAGMENT
], fs
);
1603 tu6_emit_vpc(cs
, vs
, gs
, fs
, binning_pass
, tf
);
1604 tu6_emit_vpc_varying_modes(cs
, fs
, binning_pass
);
1605 tu6_emit_fs_inputs(cs
, fs
);
1606 tu6_emit_fs_outputs(cs
, fs
, builder
->color_attachment_count
,
1607 builder
->use_dual_src_blend
,
1608 builder
->render_components
);
1610 tu6_emit_shader_object(cs
, MESA_SHADER_VERTEX
, vs
, binary_bo
, vs_offset
);
1612 tu6_emit_shader_object(cs
, MESA_SHADER_GEOMETRY
, gs
, binary_bo
,
1613 builder
->shader_offsets
[MESA_SHADER_GEOMETRY
]);
1614 tu6_emit_shader_object(cs
, MESA_SHADER_FRAGMENT
, fs
, binary_bo
,
1615 builder
->shader_offsets
[MESA_SHADER_FRAGMENT
]);
1617 tu6_emit_immediates(cs
, vs
, CP_LOAD_STATE6_GEOM
, SB6_VS_SHADER
);
1619 tu6_emit_immediates(cs
, gs
, CP_LOAD_STATE6_GEOM
, SB6_GS_SHADER
);
1620 tu6_emit_geometry_consts(cs
, vs
, gs
);
1623 tu6_emit_immediates(cs
, fs
, CP_LOAD_STATE6_FRAG
, SB6_FS_SHADER
);
1627 tu6_emit_vertex_input(struct tu_cs
*cs
,
1628 const struct ir3_shader_variant
*vs
,
1629 const VkPipelineVertexInputStateCreateInfo
*info
,
1630 uint32_t *bindings_used
)
1632 uint32_t vfd_decode_idx
= 0;
1633 uint32_t binding_instanced
= 0; /* bitmask of instanced bindings */
1635 for (uint32_t i
= 0; i
< info
->vertexBindingDescriptionCount
; i
++) {
1636 const VkVertexInputBindingDescription
*binding
=
1637 &info
->pVertexBindingDescriptions
[i
];
1640 A6XX_VFD_FETCH_STRIDE(binding
->binding
, binding
->stride
));
1642 if (binding
->inputRate
== VK_VERTEX_INPUT_RATE_INSTANCE
)
1643 binding_instanced
|= 1 << binding
->binding
;
1645 *bindings_used
|= 1 << binding
->binding
;
1648 /* TODO: emit all VFD_DECODE/VFD_DEST_CNTL in same (two) pkt4 */
1650 for (uint32_t i
= 0; i
< info
->vertexAttributeDescriptionCount
; i
++) {
1651 const VkVertexInputAttributeDescription
*attr
=
1652 &info
->pVertexAttributeDescriptions
[i
];
1655 for (input_idx
= 0; input_idx
< vs
->inputs_count
; input_idx
++) {
1656 if ((vs
->inputs
[input_idx
].slot
- VERT_ATTRIB_GENERIC0
) == attr
->location
)
1660 /* attribute not used, skip it */
1661 if (input_idx
== vs
->inputs_count
)
1664 const struct tu_native_format format
= tu6_format_vtx(attr
->format
);
1666 A6XX_VFD_DECODE_INSTR(vfd_decode_idx
,
1667 .idx
= attr
->binding
,
1668 .offset
= attr
->offset
,
1669 .instanced
= binding_instanced
& (1 << attr
->binding
),
1670 .format
= format
.fmt
,
1671 .swap
= format
.swap
,
1673 ._float
= !vk_format_is_int(attr
->format
)),
1674 A6XX_VFD_DECODE_STEP_RATE(vfd_decode_idx
, 1));
1677 A6XX_VFD_DEST_CNTL_INSTR(vfd_decode_idx
,
1678 .writemask
= vs
->inputs
[input_idx
].compmask
,
1679 .regid
= vs
->inputs
[input_idx
].regid
));
1686 .fetch_cnt
= info
->vertexBindingDescriptionCount
,
1687 .decode_cnt
= vfd_decode_idx
));
1691 tu6_guardband_adj(uint32_t v
)
1694 return (uint32_t)(511.0 - 65.0 * (log2(v
) - 8.0));
1700 tu6_emit_viewport(struct tu_cs
*cs
, const VkViewport
*viewport
)
1704 scales
[0] = viewport
->width
/ 2.0f
;
1705 scales
[1] = viewport
->height
/ 2.0f
;
1706 scales
[2] = viewport
->maxDepth
- viewport
->minDepth
;
1707 offsets
[0] = viewport
->x
+ scales
[0];
1708 offsets
[1] = viewport
->y
+ scales
[1];
1709 offsets
[2] = viewport
->minDepth
;
1713 min
.x
= (int32_t) viewport
->x
;
1714 max
.x
= (int32_t) ceilf(viewport
->x
+ viewport
->width
);
1715 if (viewport
->height
>= 0.0f
) {
1716 min
.y
= (int32_t) viewport
->y
;
1717 max
.y
= (int32_t) ceilf(viewport
->y
+ viewport
->height
);
1719 min
.y
= (int32_t)(viewport
->y
+ viewport
->height
);
1720 max
.y
= (int32_t) ceilf(viewport
->y
);
1722 /* the spec allows viewport->height to be 0.0f */
1725 assert(min
.x
>= 0 && min
.x
< max
.x
);
1726 assert(min
.y
>= 0 && min
.y
< max
.y
);
1728 VkExtent2D guardband_adj
;
1729 guardband_adj
.width
= tu6_guardband_adj(max
.x
- min
.x
);
1730 guardband_adj
.height
= tu6_guardband_adj(max
.y
- min
.y
);
1732 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0
, 6);
1733 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_XOFFSET_0(offsets
[0]).value
);
1734 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_XSCALE_0(scales
[0]).value
);
1735 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_YOFFSET_0(offsets
[1]).value
);
1736 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_YSCALE_0(scales
[1]).value
);
1737 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_ZOFFSET_0(offsets
[2]).value
);
1738 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_ZSCALE_0(scales
[2]).value
);
1740 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0
, 2);
1741 tu_cs_emit(cs
, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(min
.x
) |
1742 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(min
.y
));
1743 tu_cs_emit(cs
, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(max
.x
- 1) |
1744 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(max
.y
- 1));
1746 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ
, 1);
1748 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_adj
.width
) |
1749 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_adj
.height
));
1751 float z_clamp_min
= MIN2(viewport
->minDepth
, viewport
->maxDepth
);
1752 float z_clamp_max
= MAX2(viewport
->minDepth
, viewport
->maxDepth
);
1755 A6XX_GRAS_CL_Z_CLAMP_MIN(z_clamp_min
),
1756 A6XX_GRAS_CL_Z_CLAMP_MAX(z_clamp_max
));
1759 A6XX_RB_Z_CLAMP_MIN(z_clamp_min
),
1760 A6XX_RB_Z_CLAMP_MAX(z_clamp_max
));
1764 tu6_emit_scissor(struct tu_cs
*cs
, const VkRect2D
*scissor
)
1766 const VkOffset2D min
= scissor
->offset
;
1767 const VkOffset2D max
= {
1768 scissor
->offset
.x
+ scissor
->extent
.width
,
1769 scissor
->offset
.y
+ scissor
->extent
.height
,
1772 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0
, 2);
1773 tu_cs_emit(cs
, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(min
.x
) |
1774 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(min
.y
));
1775 tu_cs_emit(cs
, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(max
.x
- 1) |
1776 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(max
.y
- 1));
1780 tu6_emit_sample_locations(struct tu_cs
*cs
, const VkSampleLocationsInfoEXT
*samp_loc
)
1783 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SAMPLE_CONFIG
, 1);
1786 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_SAMPLE_CONFIG
, 1);
1789 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_TP_SAMPLE_CONFIG
, 1);
1794 assert(samp_loc
->sampleLocationsPerPixel
== samp_loc
->sampleLocationsCount
);
1795 assert(samp_loc
->sampleLocationGridSize
.width
== 1);
1796 assert(samp_loc
->sampleLocationGridSize
.height
== 1);
1798 uint32_t sample_config
=
1799 A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE
;
1800 uint32_t sample_locations
= 0;
1801 for (uint32_t i
= 0; i
< samp_loc
->sampleLocationsCount
; i
++) {
1803 (A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(samp_loc
->pSampleLocations
[i
].x
) |
1804 A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(samp_loc
->pSampleLocations
[i
].y
)) << i
*8;
1807 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SAMPLE_CONFIG
, 2);
1808 tu_cs_emit(cs
, sample_config
);
1809 tu_cs_emit(cs
, sample_locations
);
1811 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_SAMPLE_CONFIG
, 2);
1812 tu_cs_emit(cs
, sample_config
);
1813 tu_cs_emit(cs
, sample_locations
);
1815 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_TP_SAMPLE_CONFIG
, 2);
1816 tu_cs_emit(cs
, sample_config
);
1817 tu_cs_emit(cs
, sample_locations
);
1821 tu6_emit_gras_unknowns(struct tu_cs
*cs
)
1823 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_UNKNOWN_8001
, 1);
1824 tu_cs_emit(cs
, 0x0);
1828 tu6_emit_point_size(struct tu_cs
*cs
)
1830 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SU_POINT_MINMAX
, 2);
1831 tu_cs_emit(cs
, A6XX_GRAS_SU_POINT_MINMAX_MIN(1.0f
/ 16.0f
) |
1832 A6XX_GRAS_SU_POINT_MINMAX_MAX(4092.0f
));
1833 tu_cs_emit(cs
, A6XX_GRAS_SU_POINT_SIZE(1.0f
).value
);
1837 tu6_gras_su_cntl(const VkPipelineRasterizationStateCreateInfo
*rast_info
,
1838 VkSampleCountFlagBits samples
)
1840 uint32_t gras_su_cntl
= 0;
1842 if (rast_info
->cullMode
& VK_CULL_MODE_FRONT_BIT
)
1843 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_CULL_FRONT
;
1844 if (rast_info
->cullMode
& VK_CULL_MODE_BACK_BIT
)
1845 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_CULL_BACK
;
1847 if (rast_info
->frontFace
== VK_FRONT_FACE_CLOCKWISE
)
1848 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_FRONT_CW
;
1850 /* don't set A6XX_GRAS_SU_CNTL_LINEHALFWIDTH */
1852 if (rast_info
->depthBiasEnable
)
1853 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_POLY_OFFSET
;
1855 if (samples
> VK_SAMPLE_COUNT_1_BIT
)
1856 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_MSAA_ENABLE
;
1858 return gras_su_cntl
;
1862 tu6_emit_gras_su_cntl(struct tu_cs
*cs
,
1863 uint32_t gras_su_cntl
,
1866 assert((gras_su_cntl
& A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK
) == 0);
1867 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(line_width
/ 2.0f
);
1869 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SU_CNTL
, 1);
1870 tu_cs_emit(cs
, gras_su_cntl
);
1874 tu6_emit_depth_bias(struct tu_cs
*cs
,
1875 float constant_factor
,
1879 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE
, 3);
1880 tu_cs_emit(cs
, A6XX_GRAS_SU_POLY_OFFSET_SCALE(slope_factor
).value
);
1881 tu_cs_emit(cs
, A6XX_GRAS_SU_POLY_OFFSET_OFFSET(constant_factor
).value
);
1882 tu_cs_emit(cs
, A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(clamp
).value
);
1886 tu6_emit_alpha_control_disable(struct tu_cs
*cs
)
1888 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_ALPHA_CONTROL
, 1);
1893 tu6_emit_depth_control(struct tu_cs
*cs
,
1894 const VkPipelineDepthStencilStateCreateInfo
*ds_info
,
1895 const VkPipelineRasterizationStateCreateInfo
*rast_info
)
1897 assert(!ds_info
->depthBoundsTestEnable
);
1899 uint32_t rb_depth_cntl
= 0;
1900 if (ds_info
->depthTestEnable
) {
1902 A6XX_RB_DEPTH_CNTL_Z_ENABLE
|
1903 A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info
->depthCompareOp
)) |
1904 A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE
;
1906 if (rast_info
->depthClampEnable
)
1907 rb_depth_cntl
|= A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE
;
1909 if (ds_info
->depthWriteEnable
)
1910 rb_depth_cntl
|= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE
;
1913 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_CNTL
, 1);
1914 tu_cs_emit(cs
, rb_depth_cntl
);
1918 tu6_emit_stencil_control(struct tu_cs
*cs
,
1919 const VkPipelineDepthStencilStateCreateInfo
*ds_info
)
1921 uint32_t rb_stencil_control
= 0;
1922 if (ds_info
->stencilTestEnable
) {
1923 const VkStencilOpState
*front
= &ds_info
->front
;
1924 const VkStencilOpState
*back
= &ds_info
->back
;
1925 rb_stencil_control
|=
1926 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE
|
1927 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF
|
1928 A6XX_RB_STENCIL_CONTROL_STENCIL_READ
|
1929 A6XX_RB_STENCIL_CONTROL_FUNC(tu6_compare_func(front
->compareOp
)) |
1930 A6XX_RB_STENCIL_CONTROL_FAIL(tu6_stencil_op(front
->failOp
)) |
1931 A6XX_RB_STENCIL_CONTROL_ZPASS(tu6_stencil_op(front
->passOp
)) |
1932 A6XX_RB_STENCIL_CONTROL_ZFAIL(tu6_stencil_op(front
->depthFailOp
)) |
1933 A6XX_RB_STENCIL_CONTROL_FUNC_BF(tu6_compare_func(back
->compareOp
)) |
1934 A6XX_RB_STENCIL_CONTROL_FAIL_BF(tu6_stencil_op(back
->failOp
)) |
1935 A6XX_RB_STENCIL_CONTROL_ZPASS_BF(tu6_stencil_op(back
->passOp
)) |
1936 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(tu6_stencil_op(back
->depthFailOp
));
1939 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCIL_CONTROL
, 1);
1940 tu_cs_emit(cs
, rb_stencil_control
);
1944 tu6_emit_stencil_compare_mask(struct tu_cs
*cs
, uint32_t front
, uint32_t back
)
1946 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCILMASK
, 1);
1948 cs
, A6XX_RB_STENCILMASK_MASK(front
) | A6XX_RB_STENCILMASK_BFMASK(back
));
1952 tu6_emit_stencil_write_mask(struct tu_cs
*cs
, uint32_t front
, uint32_t back
)
1954 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCILWRMASK
, 1);
1955 tu_cs_emit(cs
, A6XX_RB_STENCILWRMASK_WRMASK(front
) |
1956 A6XX_RB_STENCILWRMASK_BFWRMASK(back
));
1960 tu6_emit_stencil_reference(struct tu_cs
*cs
, uint32_t front
, uint32_t back
)
1962 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCILREF
, 1);
1964 A6XX_RB_STENCILREF_REF(front
) | A6XX_RB_STENCILREF_BFREF(back
));
1968 tu6_rb_mrt_blend_control(const VkPipelineColorBlendAttachmentState
*att
,
1971 const enum a3xx_rb_blend_opcode color_op
= tu6_blend_op(att
->colorBlendOp
);
1972 const enum adreno_rb_blend_factor src_color_factor
= tu6_blend_factor(
1973 has_alpha
? att
->srcColorBlendFactor
1974 : tu_blend_factor_no_dst_alpha(att
->srcColorBlendFactor
));
1975 const enum adreno_rb_blend_factor dst_color_factor
= tu6_blend_factor(
1976 has_alpha
? att
->dstColorBlendFactor
1977 : tu_blend_factor_no_dst_alpha(att
->dstColorBlendFactor
));
1978 const enum a3xx_rb_blend_opcode alpha_op
= tu6_blend_op(att
->alphaBlendOp
);
1979 const enum adreno_rb_blend_factor src_alpha_factor
=
1980 tu6_blend_factor(att
->srcAlphaBlendFactor
);
1981 const enum adreno_rb_blend_factor dst_alpha_factor
=
1982 tu6_blend_factor(att
->dstAlphaBlendFactor
);
1984 return A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(src_color_factor
) |
1985 A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(color_op
) |
1986 A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(dst_color_factor
) |
1987 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(src_alpha_factor
) |
1988 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(alpha_op
) |
1989 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(dst_alpha_factor
);
1993 tu6_rb_mrt_control(const VkPipelineColorBlendAttachmentState
*att
,
1994 uint32_t rb_mrt_control_rop
,
1998 uint32_t rb_mrt_control
=
1999 A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(att
->colorWriteMask
);
2001 /* ignore blending and logic op for integer attachments */
2003 rb_mrt_control
|= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY
);
2004 return rb_mrt_control
;
2007 rb_mrt_control
|= rb_mrt_control_rop
;
2009 if (att
->blendEnable
) {
2010 rb_mrt_control
|= A6XX_RB_MRT_CONTROL_BLEND
;
2013 rb_mrt_control
|= A6XX_RB_MRT_CONTROL_BLEND2
;
2016 return rb_mrt_control
;
2020 tu6_emit_rb_mrt_controls(struct tu_cs
*cs
,
2021 const VkPipelineColorBlendStateCreateInfo
*blend_info
,
2022 const VkFormat attachment_formats
[MAX_RTS
],
2023 uint32_t *blend_enable_mask
)
2025 *blend_enable_mask
= 0;
2027 bool rop_reads_dst
= false;
2028 uint32_t rb_mrt_control_rop
= 0;
2029 if (blend_info
->logicOpEnable
) {
2030 rop_reads_dst
= tu_logic_op_reads_dst(blend_info
->logicOp
);
2031 rb_mrt_control_rop
=
2032 A6XX_RB_MRT_CONTROL_ROP_ENABLE
|
2033 A6XX_RB_MRT_CONTROL_ROP_CODE(tu6_rop(blend_info
->logicOp
));
2036 for (uint32_t i
= 0; i
< blend_info
->attachmentCount
; i
++) {
2037 const VkPipelineColorBlendAttachmentState
*att
=
2038 &blend_info
->pAttachments
[i
];
2039 const VkFormat format
= attachment_formats
[i
];
2041 uint32_t rb_mrt_control
= 0;
2042 uint32_t rb_mrt_blend_control
= 0;
2043 if (format
!= VK_FORMAT_UNDEFINED
) {
2044 const bool is_int
= vk_format_is_int(format
);
2045 const bool has_alpha
= vk_format_has_alpha(format
);
2048 tu6_rb_mrt_control(att
, rb_mrt_control_rop
, is_int
, has_alpha
);
2049 rb_mrt_blend_control
= tu6_rb_mrt_blend_control(att
, has_alpha
);
2051 if (att
->blendEnable
|| rop_reads_dst
)
2052 *blend_enable_mask
|= 1 << i
;
2055 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_MRT_CONTROL(i
), 2);
2056 tu_cs_emit(cs
, rb_mrt_control
);
2057 tu_cs_emit(cs
, rb_mrt_blend_control
);
2062 tu6_emit_blend_control(struct tu_cs
*cs
,
2063 uint32_t blend_enable_mask
,
2064 bool dual_src_blend
,
2065 const VkPipelineMultisampleStateCreateInfo
*msaa_info
)
2067 const uint32_t sample_mask
=
2068 msaa_info
->pSampleMask
? (*msaa_info
->pSampleMask
& 0xffff)
2069 : ((1 << msaa_info
->rasterizationSamples
) - 1);
2072 A6XX_SP_BLEND_CNTL(.enabled
= blend_enable_mask
,
2073 .dual_color_in_enable
= dual_src_blend
,
2074 .alpha_to_coverage
= msaa_info
->alphaToCoverageEnable
,
2077 /* set A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND only when enabled? */
2079 A6XX_RB_BLEND_CNTL(.enable_blend
= blend_enable_mask
,
2080 .independent_blend
= true,
2081 .sample_mask
= sample_mask
,
2082 .dual_color_in_enable
= dual_src_blend
,
2083 .alpha_to_coverage
= msaa_info
->alphaToCoverageEnable
,
2084 .alpha_to_one
= msaa_info
->alphaToOneEnable
));
2088 tu6_emit_blend_constants(struct tu_cs
*cs
, const float constants
[4])
2090 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_BLEND_RED_F32
, 4);
2091 tu_cs_emit_array(cs
, (const uint32_t *) constants
, 4);
2095 tu_pipeline_create(struct tu_device
*dev
,
2096 struct tu_pipeline_layout
*layout
,
2098 const VkAllocationCallbacks
*pAllocator
,
2099 struct tu_pipeline
**out_pipeline
)
2101 struct tu_pipeline
*pipeline
=
2102 vk_zalloc2(&dev
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
2103 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2105 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2107 tu_cs_init(&pipeline
->cs
, dev
, TU_CS_MODE_SUB_STREAM
, 2048);
2109 /* Reserve the space now such that tu_cs_begin_sub_stream never fails. Note
2110 * that LOAD_STATE can potentially take up a large amount of space so we
2111 * calculate its size explicitly.
2113 unsigned load_state_size
= tu6_load_state_size(layout
, compute
);
2114 VkResult result
= tu_cs_reserve_space(&pipeline
->cs
, 2048 + load_state_size
);
2115 if (result
!= VK_SUCCESS
) {
2116 vk_free2(&dev
->alloc
, pAllocator
, pipeline
);
2120 *out_pipeline
= pipeline
;
2126 tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder
*builder
)
2128 const VkPipelineShaderStageCreateInfo
*stage_infos
[MESA_SHADER_STAGES
] = {
2131 for (uint32_t i
= 0; i
< builder
->create_info
->stageCount
; i
++) {
2132 gl_shader_stage stage
=
2133 tu_shader_stage(builder
->create_info
->pStages
[i
].stage
);
2134 stage_infos
[stage
] = &builder
->create_info
->pStages
[i
];
2137 struct tu_shader_compile_options options
;
2138 tu_shader_compile_options_init(&options
, builder
->create_info
);
2140 /* compile shaders in reverse order */
2141 struct tu_shader
*next_stage_shader
= NULL
;
2142 for (gl_shader_stage stage
= MESA_SHADER_STAGES
- 1;
2143 stage
> MESA_SHADER_NONE
; stage
--) {
2144 const VkPipelineShaderStageCreateInfo
*stage_info
= stage_infos
[stage
];
2145 if (!stage_info
&& stage
!= MESA_SHADER_FRAGMENT
)
2148 struct tu_shader
*shader
=
2149 tu_shader_create(builder
->device
, stage
, stage_info
, builder
->layout
,
2152 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2155 tu_shader_compile(builder
->device
, shader
, next_stage_shader
,
2156 &options
, builder
->alloc
);
2157 if (result
!= VK_SUCCESS
)
2160 builder
->shaders
[stage
] = shader
;
2161 builder
->shader_offsets
[stage
] = builder
->shader_total_size
;
2162 builder
->shader_total_size
+=
2163 sizeof(uint32_t) * shader
->variants
[0].info
.sizedwords
;
2165 next_stage_shader
= shader
;
2168 if (builder
->shaders
[MESA_SHADER_VERTEX
]->has_binning_pass
) {
2169 const struct tu_shader
*vs
= builder
->shaders
[MESA_SHADER_VERTEX
];
2170 const struct ir3_shader_variant
*variant
;
2172 if (vs
->ir3_shader
.stream_output
.num_outputs
)
2173 variant
= &vs
->variants
[0];
2175 variant
= &vs
->variants
[1];
2177 builder
->binning_vs_offset
= builder
->shader_total_size
;
2178 builder
->shader_total_size
+=
2179 sizeof(uint32_t) * variant
->info
.sizedwords
;
2186 tu_pipeline_builder_upload_shaders(struct tu_pipeline_builder
*builder
,
2187 struct tu_pipeline
*pipeline
)
2189 struct tu_bo
*bo
= &pipeline
->program
.binary_bo
;
2192 tu_bo_init_new(builder
->device
, bo
, builder
->shader_total_size
);
2193 if (result
!= VK_SUCCESS
)
2196 result
= tu_bo_map(builder
->device
, bo
);
2197 if (result
!= VK_SUCCESS
)
2200 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2201 const struct tu_shader
*shader
= builder
->shaders
[i
];
2205 memcpy(bo
->map
+ builder
->shader_offsets
[i
], shader
->binary
,
2206 sizeof(uint32_t) * shader
->variants
[0].info
.sizedwords
);
2209 if (builder
->shaders
[MESA_SHADER_VERTEX
]->has_binning_pass
) {
2210 const struct tu_shader
*vs
= builder
->shaders
[MESA_SHADER_VERTEX
];
2211 const struct ir3_shader_variant
*variant
;
2214 if (vs
->ir3_shader
.stream_output
.num_outputs
) {
2215 variant
= &vs
->variants
[0];
2218 variant
= &vs
->variants
[1];
2219 bin
= vs
->binning_binary
;
2222 memcpy(bo
->map
+ builder
->binning_vs_offset
, bin
,
2223 sizeof(uint32_t) * variant
->info
.sizedwords
);
2230 tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder
*builder
,
2231 struct tu_pipeline
*pipeline
)
2233 const VkPipelineDynamicStateCreateInfo
*dynamic_info
=
2234 builder
->create_info
->pDynamicState
;
2239 for (uint32_t i
= 0; i
< dynamic_info
->dynamicStateCount
; i
++) {
2240 pipeline
->dynamic_state
.mask
|=
2241 tu_dynamic_state_bit(dynamic_info
->pDynamicStates
[i
]);
2246 tu_pipeline_set_linkage(struct tu_program_descriptor_linkage
*link
,
2247 struct tu_shader
*shader
,
2248 struct ir3_shader_variant
*v
)
2250 link
->ubo_state
= v
->shader
->ubo_state
;
2251 link
->const_state
= v
->shader
->const_state
;
2252 link
->constlen
= v
->constlen
;
2253 link
->push_consts
= shader
->push_consts
;
2257 tu_pipeline_builder_parse_shader_stages(struct tu_pipeline_builder
*builder
,
2258 struct tu_pipeline
*pipeline
)
2260 struct tu_cs prog_cs
;
2261 tu_cs_begin_sub_stream(&pipeline
->cs
, 512, &prog_cs
);
2262 tu6_emit_program(&prog_cs
, builder
, &pipeline
->program
.binary_bo
, false, &pipeline
->streamout
);
2263 pipeline
->program
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &prog_cs
);
2265 tu_cs_begin_sub_stream(&pipeline
->cs
, 512, &prog_cs
);
2266 tu6_emit_program(&prog_cs
, builder
, &pipeline
->program
.binary_bo
, true, &pipeline
->streamout
);
2267 pipeline
->program
.binning_state_ib
=
2268 tu_cs_end_sub_stream(&pipeline
->cs
, &prog_cs
);
2270 VkShaderStageFlags stages
= 0;
2271 for (unsigned i
= 0; i
< builder
->create_info
->stageCount
; i
++) {
2272 stages
|= builder
->create_info
->pStages
[i
].stage
;
2274 pipeline
->active_stages
= stages
;
2276 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2277 if (!builder
->shaders
[i
])
2280 tu_pipeline_set_linkage(&pipeline
->program
.link
[i
],
2281 builder
->shaders
[i
],
2282 &builder
->shaders
[i
]->variants
[0]);
2285 if (builder
->shaders
[MESA_SHADER_FRAGMENT
]) {
2286 memcpy(pipeline
->program
.input_attachment_idx
,
2287 builder
->shaders
[MESA_SHADER_FRAGMENT
]->attachment_idx
,
2288 sizeof(pipeline
->program
.input_attachment_idx
));
2293 tu_pipeline_builder_parse_vertex_input(struct tu_pipeline_builder
*builder
,
2294 struct tu_pipeline
*pipeline
)
2296 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
2297 builder
->create_info
->pVertexInputState
;
2298 const struct tu_shader
*vs
= builder
->shaders
[MESA_SHADER_VERTEX
];
2301 tu_cs_begin_sub_stream(&pipeline
->cs
,
2302 MAX_VERTEX_ATTRIBS
* 7 + 2, &vi_cs
);
2303 tu6_emit_vertex_input(&vi_cs
, &vs
->variants
[0], vi_info
,
2304 &pipeline
->vi
.bindings_used
);
2305 pipeline
->vi
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &vi_cs
);
2307 if (vs
->has_binning_pass
) {
2308 tu_cs_begin_sub_stream(&pipeline
->cs
,
2309 MAX_VERTEX_ATTRIBS
* 7 + 2, &vi_cs
);
2310 tu6_emit_vertex_input(
2311 &vi_cs
, &vs
->variants
[1], vi_info
, &pipeline
->vi
.bindings_used
);
2312 pipeline
->vi
.binning_state_ib
=
2313 tu_cs_end_sub_stream(&pipeline
->cs
, &vi_cs
);
2318 tu_pipeline_builder_parse_input_assembly(struct tu_pipeline_builder
*builder
,
2319 struct tu_pipeline
*pipeline
)
2321 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
2322 builder
->create_info
->pInputAssemblyState
;
2324 pipeline
->ia
.primtype
= tu6_primtype(ia_info
->topology
);
2325 pipeline
->ia
.primitive_restart
= ia_info
->primitiveRestartEnable
;
2329 tu_pipeline_builder_parse_viewport(struct tu_pipeline_builder
*builder
,
2330 struct tu_pipeline
*pipeline
)
2334 * pViewportState is a pointer to an instance of the
2335 * VkPipelineViewportStateCreateInfo structure, and is ignored if the
2336 * pipeline has rasterization disabled."
2338 * We leave the relevant registers stale in that case.
2340 if (builder
->rasterizer_discard
)
2343 const VkPipelineViewportStateCreateInfo
*vp_info
=
2344 builder
->create_info
->pViewportState
;
2347 tu_cs_begin_sub_stream(&pipeline
->cs
, 21, &vp_cs
);
2349 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_VIEWPORT
)) {
2350 assert(vp_info
->viewportCount
== 1);
2351 tu6_emit_viewport(&vp_cs
, vp_info
->pViewports
);
2354 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_SCISSOR
)) {
2355 assert(vp_info
->scissorCount
== 1);
2356 tu6_emit_scissor(&vp_cs
, vp_info
->pScissors
);
2359 pipeline
->vp
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &vp_cs
);
2363 tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder
*builder
,
2364 struct tu_pipeline
*pipeline
)
2366 const VkPipelineRasterizationStateCreateInfo
*rast_info
=
2367 builder
->create_info
->pRasterizationState
;
2369 assert(rast_info
->polygonMode
== VK_POLYGON_MODE_FILL
);
2371 struct tu_cs rast_cs
;
2372 tu_cs_begin_sub_stream(&pipeline
->cs
, 20, &rast_cs
);
2375 tu_cs_emit_regs(&rast_cs
,
2377 .znear_clip_disable
= rast_info
->depthClampEnable
,
2378 .zfar_clip_disable
= rast_info
->depthClampEnable
,
2379 .unk5
= rast_info
->depthClampEnable
,
2380 .zero_gb_scale_z
= 1,
2381 .vp_clip_code_ignore
= 1));
2382 /* move to hw ctx init? */
2383 tu6_emit_gras_unknowns(&rast_cs
);
2384 tu6_emit_point_size(&rast_cs
);
2386 const uint32_t gras_su_cntl
=
2387 tu6_gras_su_cntl(rast_info
, builder
->samples
);
2389 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_LINE_WIDTH
))
2390 tu6_emit_gras_su_cntl(&rast_cs
, gras_su_cntl
, rast_info
->lineWidth
);
2392 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_DEPTH_BIAS
)) {
2393 tu6_emit_depth_bias(&rast_cs
, rast_info
->depthBiasConstantFactor
,
2394 rast_info
->depthBiasClamp
,
2395 rast_info
->depthBiasSlopeFactor
);
2398 pipeline
->rast
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &rast_cs
);
2400 pipeline
->rast
.gras_su_cntl
= gras_su_cntl
;
2404 tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder
*builder
,
2405 struct tu_pipeline
*pipeline
)
2409 * pDepthStencilState is a pointer to an instance of the
2410 * VkPipelineDepthStencilStateCreateInfo structure, and is ignored if
2411 * the pipeline has rasterization disabled or if the subpass of the
2412 * render pass the pipeline is created against does not use a
2413 * depth/stencil attachment.
2415 * Disable both depth and stencil tests if there is no ds attachment,
2416 * Disable depth test if ds attachment is S8_UINT, since S8_UINT defines
2417 * only the separate stencil attachment
2419 static const VkPipelineDepthStencilStateCreateInfo dummy_ds_info
;
2420 const VkPipelineDepthStencilStateCreateInfo
*ds_info
=
2421 builder
->depth_attachment_format
!= VK_FORMAT_UNDEFINED
2422 ? builder
->create_info
->pDepthStencilState
2424 const VkPipelineDepthStencilStateCreateInfo
*ds_info_depth
=
2425 builder
->depth_attachment_format
!= VK_FORMAT_S8_UINT
2426 ? ds_info
: &dummy_ds_info
;
2429 tu_cs_begin_sub_stream(&pipeline
->cs
, 12, &ds_cs
);
2431 /* move to hw ctx init? */
2432 tu6_emit_alpha_control_disable(&ds_cs
);
2434 tu6_emit_depth_control(&ds_cs
, ds_info_depth
,
2435 builder
->create_info
->pRasterizationState
);
2436 tu6_emit_stencil_control(&ds_cs
, ds_info
);
2438 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_COMPARE_MASK
)) {
2439 tu6_emit_stencil_compare_mask(&ds_cs
, ds_info
->front
.compareMask
,
2440 ds_info
->back
.compareMask
);
2442 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_WRITE_MASK
)) {
2443 tu6_emit_stencil_write_mask(&ds_cs
, ds_info
->front
.writeMask
,
2444 ds_info
->back
.writeMask
);
2446 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_REFERENCE
)) {
2447 tu6_emit_stencil_reference(&ds_cs
, ds_info
->front
.reference
,
2448 ds_info
->back
.reference
);
2451 pipeline
->ds
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &ds_cs
);
2455 tu_pipeline_builder_parse_multisample_and_color_blend(
2456 struct tu_pipeline_builder
*builder
, struct tu_pipeline
*pipeline
)
2460 * pMultisampleState is a pointer to an instance of the
2461 * VkPipelineMultisampleStateCreateInfo, and is ignored if the pipeline
2462 * has rasterization disabled.
2466 * pColorBlendState is a pointer to an instance of the
2467 * VkPipelineColorBlendStateCreateInfo structure, and is ignored if the
2468 * pipeline has rasterization disabled or if the subpass of the render
2469 * pass the pipeline is created against does not use any color
2472 * We leave the relevant registers stale when rasterization is disabled.
2474 if (builder
->rasterizer_discard
)
2477 static const VkPipelineColorBlendStateCreateInfo dummy_blend_info
;
2478 const VkPipelineMultisampleStateCreateInfo
*msaa_info
=
2479 builder
->create_info
->pMultisampleState
;
2480 const VkPipelineColorBlendStateCreateInfo
*blend_info
=
2481 builder
->use_color_attachments
? builder
->create_info
->pColorBlendState
2482 : &dummy_blend_info
;
2484 struct tu_cs blend_cs
;
2485 tu_cs_begin_sub_stream(&pipeline
->cs
, MAX_RTS
* 3 + 18, &blend_cs
);
2487 uint32_t blend_enable_mask
;
2488 tu6_emit_rb_mrt_controls(&blend_cs
, blend_info
,
2489 builder
->color_attachment_formats
,
2490 &blend_enable_mask
);
2492 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_BLEND_CONSTANTS
))
2493 tu6_emit_blend_constants(&blend_cs
, blend_info
->blendConstants
);
2495 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_SAMPLE_LOCATIONS
)) {
2496 const struct VkPipelineSampleLocationsStateCreateInfoEXT
*sample_locations
=
2497 vk_find_struct_const(msaa_info
->pNext
, PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
);
2498 const VkSampleLocationsInfoEXT
*samp_loc
= NULL
;
2500 if (sample_locations
&& sample_locations
->sampleLocationsEnable
)
2501 samp_loc
= &sample_locations
->sampleLocationsInfo
;
2503 tu6_emit_sample_locations(&blend_cs
, samp_loc
);
2506 tu6_emit_blend_control(&blend_cs
, blend_enable_mask
,
2507 builder
->use_dual_src_blend
, msaa_info
);
2509 pipeline
->blend
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &blend_cs
);
2513 tu_pipeline_finish(struct tu_pipeline
*pipeline
,
2514 struct tu_device
*dev
,
2515 const VkAllocationCallbacks
*alloc
)
2517 tu_cs_finish(&pipeline
->cs
);
2519 if (pipeline
->program
.binary_bo
.gem_handle
)
2520 tu_bo_finish(dev
, &pipeline
->program
.binary_bo
);
2524 tu_pipeline_builder_build(struct tu_pipeline_builder
*builder
,
2525 struct tu_pipeline
**pipeline
)
2527 VkResult result
= tu_pipeline_create(builder
->device
, builder
->layout
,
2528 false, builder
->alloc
, pipeline
);
2529 if (result
!= VK_SUCCESS
)
2532 (*pipeline
)->layout
= builder
->layout
;
2534 /* compile and upload shaders */
2535 result
= tu_pipeline_builder_compile_shaders(builder
);
2536 if (result
== VK_SUCCESS
)
2537 result
= tu_pipeline_builder_upload_shaders(builder
, *pipeline
);
2538 if (result
!= VK_SUCCESS
) {
2539 tu_pipeline_finish(*pipeline
, builder
->device
, builder
->alloc
);
2540 vk_free2(&builder
->device
->alloc
, builder
->alloc
, *pipeline
);
2541 *pipeline
= VK_NULL_HANDLE
;
2546 tu_pipeline_builder_parse_dynamic(builder
, *pipeline
);
2547 tu_pipeline_builder_parse_shader_stages(builder
, *pipeline
);
2548 tu_pipeline_builder_parse_vertex_input(builder
, *pipeline
);
2549 tu_pipeline_builder_parse_input_assembly(builder
, *pipeline
);
2550 tu_pipeline_builder_parse_viewport(builder
, *pipeline
);
2551 tu_pipeline_builder_parse_rasterization(builder
, *pipeline
);
2552 tu_pipeline_builder_parse_depth_stencil(builder
, *pipeline
);
2553 tu_pipeline_builder_parse_multisample_and_color_blend(builder
, *pipeline
);
2554 tu6_emit_load_state(*pipeline
, false);
2556 /* we should have reserved enough space upfront such that the CS never
2559 assert((*pipeline
)->cs
.bo_count
== 1);
2565 tu_pipeline_builder_finish(struct tu_pipeline_builder
*builder
)
2567 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2568 if (!builder
->shaders
[i
])
2570 tu_shader_destroy(builder
->device
, builder
->shaders
[i
], builder
->alloc
);
2575 tu_pipeline_builder_init_graphics(
2576 struct tu_pipeline_builder
*builder
,
2577 struct tu_device
*dev
,
2578 struct tu_pipeline_cache
*cache
,
2579 const VkGraphicsPipelineCreateInfo
*create_info
,
2580 const VkAllocationCallbacks
*alloc
)
2582 TU_FROM_HANDLE(tu_pipeline_layout
, layout
, create_info
->layout
);
2584 *builder
= (struct tu_pipeline_builder
) {
2587 .create_info
= create_info
,
2592 builder
->rasterizer_discard
=
2593 create_info
->pRasterizationState
->rasterizerDiscardEnable
;
2595 if (builder
->rasterizer_discard
) {
2596 builder
->samples
= VK_SAMPLE_COUNT_1_BIT
;
2598 builder
->samples
= create_info
->pMultisampleState
->rasterizationSamples
;
2600 const struct tu_render_pass
*pass
=
2601 tu_render_pass_from_handle(create_info
->renderPass
);
2602 const struct tu_subpass
*subpass
=
2603 &pass
->subpasses
[create_info
->subpass
];
2605 const uint32_t a
= subpass
->depth_stencil_attachment
.attachment
;
2606 builder
->depth_attachment_format
= (a
!= VK_ATTACHMENT_UNUSED
) ?
2607 pass
->attachments
[a
].format
: VK_FORMAT_UNDEFINED
;
2609 assert(subpass
->color_count
== 0 ||
2610 !create_info
->pColorBlendState
||
2611 subpass
->color_count
== create_info
->pColorBlendState
->attachmentCount
);
2612 builder
->color_attachment_count
= subpass
->color_count
;
2613 for (uint32_t i
= 0; i
< subpass
->color_count
; i
++) {
2614 const uint32_t a
= subpass
->color_attachments
[i
].attachment
;
2615 if (a
== VK_ATTACHMENT_UNUSED
)
2618 builder
->color_attachment_formats
[i
] = pass
->attachments
[a
].format
;
2619 builder
->use_color_attachments
= true;
2620 builder
->render_components
|= 0xf << (i
* 4);
2623 if (tu_blend_state_is_dual_src(create_info
->pColorBlendState
)) {
2624 builder
->color_attachment_count
++;
2625 builder
->use_dual_src_blend
= true;
2626 /* dual source blending has an extra fs output in the 2nd slot */
2627 if (subpass
->color_attachments
[0].attachment
!= VK_ATTACHMENT_UNUSED
)
2628 builder
->render_components
|= 0xf << 4;
2634 tu_graphics_pipeline_create(VkDevice device
,
2635 VkPipelineCache pipelineCache
,
2636 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2637 const VkAllocationCallbacks
*pAllocator
,
2638 VkPipeline
*pPipeline
)
2640 TU_FROM_HANDLE(tu_device
, dev
, device
);
2641 TU_FROM_HANDLE(tu_pipeline_cache
, cache
, pipelineCache
);
2643 struct tu_pipeline_builder builder
;
2644 tu_pipeline_builder_init_graphics(&builder
, dev
, cache
,
2645 pCreateInfo
, pAllocator
);
2647 struct tu_pipeline
*pipeline
= NULL
;
2648 VkResult result
= tu_pipeline_builder_build(&builder
, &pipeline
);
2649 tu_pipeline_builder_finish(&builder
);
2651 if (result
== VK_SUCCESS
)
2652 *pPipeline
= tu_pipeline_to_handle(pipeline
);
2654 *pPipeline
= VK_NULL_HANDLE
;
2660 tu_CreateGraphicsPipelines(VkDevice device
,
2661 VkPipelineCache pipelineCache
,
2663 const VkGraphicsPipelineCreateInfo
*pCreateInfos
,
2664 const VkAllocationCallbacks
*pAllocator
,
2665 VkPipeline
*pPipelines
)
2667 VkResult final_result
= VK_SUCCESS
;
2669 for (uint32_t i
= 0; i
< count
; i
++) {
2670 VkResult result
= tu_graphics_pipeline_create(device
, pipelineCache
,
2671 &pCreateInfos
[i
], pAllocator
,
2674 if (result
!= VK_SUCCESS
)
2675 final_result
= result
;
2678 return final_result
;
2682 tu6_emit_compute_program(struct tu_cs
*cs
,
2683 struct tu_shader
*shader
,
2684 const struct tu_bo
*binary_bo
)
2686 const struct ir3_shader_variant
*v
= &shader
->variants
[0];
2688 tu6_emit_cs_config(cs
, shader
, v
);
2690 /* The compute program is the only one in the pipeline, so 0 offset. */
2691 tu6_emit_shader_object(cs
, MESA_SHADER_COMPUTE
, v
, binary_bo
, 0);
2693 tu6_emit_immediates(cs
, v
, CP_LOAD_STATE6_FRAG
, SB6_CS_SHADER
);
2697 tu_compute_upload_shader(VkDevice device
,
2698 struct tu_pipeline
*pipeline
,
2699 struct tu_shader
*shader
)
2701 TU_FROM_HANDLE(tu_device
, dev
, device
);
2702 struct tu_bo
*bo
= &pipeline
->program
.binary_bo
;
2703 struct ir3_shader_variant
*v
= &shader
->variants
[0];
2705 uint32_t shader_size
= sizeof(uint32_t) * v
->info
.sizedwords
;
2707 tu_bo_init_new(dev
, bo
, shader_size
);
2708 if (result
!= VK_SUCCESS
)
2711 result
= tu_bo_map(dev
, bo
);
2712 if (result
!= VK_SUCCESS
)
2715 memcpy(bo
->map
, shader
->binary
, shader_size
);
2722 tu_compute_pipeline_create(VkDevice device
,
2723 VkPipelineCache _cache
,
2724 const VkComputePipelineCreateInfo
*pCreateInfo
,
2725 const VkAllocationCallbacks
*pAllocator
,
2726 VkPipeline
*pPipeline
)
2728 TU_FROM_HANDLE(tu_device
, dev
, device
);
2729 TU_FROM_HANDLE(tu_pipeline_layout
, layout
, pCreateInfo
->layout
);
2730 const VkPipelineShaderStageCreateInfo
*stage_info
= &pCreateInfo
->stage
;
2733 struct tu_pipeline
*pipeline
;
2735 *pPipeline
= VK_NULL_HANDLE
;
2737 result
= tu_pipeline_create(dev
, layout
, true, pAllocator
, &pipeline
);
2738 if (result
!= VK_SUCCESS
)
2741 pipeline
->layout
= layout
;
2743 struct tu_shader_compile_options options
;
2744 tu_shader_compile_options_init(&options
, NULL
);
2746 struct tu_shader
*shader
=
2747 tu_shader_create(dev
, MESA_SHADER_COMPUTE
, stage_info
, layout
, pAllocator
);
2749 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2753 result
= tu_shader_compile(dev
, shader
, NULL
, &options
, pAllocator
);
2754 if (result
!= VK_SUCCESS
)
2757 struct ir3_shader_variant
*v
= &shader
->variants
[0];
2759 tu_pipeline_set_linkage(&pipeline
->program
.link
[MESA_SHADER_COMPUTE
],
2762 result
= tu_compute_upload_shader(device
, pipeline
, shader
);
2763 if (result
!= VK_SUCCESS
)
2766 for (int i
= 0; i
< 3; i
++)
2767 pipeline
->compute
.local_size
[i
] = v
->shader
->nir
->info
.cs
.local_size
[i
];
2769 struct tu_cs prog_cs
;
2770 tu_cs_begin_sub_stream(&pipeline
->cs
, 512, &prog_cs
);
2771 tu6_emit_compute_program(&prog_cs
, shader
, &pipeline
->program
.binary_bo
);
2772 pipeline
->program
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &prog_cs
);
2774 tu6_emit_load_state(pipeline
, true);
2776 *pPipeline
= tu_pipeline_to_handle(pipeline
);
2781 tu_shader_destroy(dev
, shader
, pAllocator
);
2783 tu_pipeline_finish(pipeline
, dev
, pAllocator
);
2784 vk_free2(&dev
->alloc
, pAllocator
, pipeline
);
2790 tu_CreateComputePipelines(VkDevice device
,
2791 VkPipelineCache pipelineCache
,
2793 const VkComputePipelineCreateInfo
*pCreateInfos
,
2794 const VkAllocationCallbacks
*pAllocator
,
2795 VkPipeline
*pPipelines
)
2797 VkResult final_result
= VK_SUCCESS
;
2799 for (uint32_t i
= 0; i
< count
; i
++) {
2800 VkResult result
= tu_compute_pipeline_create(device
, pipelineCache
,
2802 pAllocator
, &pPipelines
[i
]);
2803 if (result
!= VK_SUCCESS
)
2804 final_result
= result
;
2807 return final_result
;
2811 tu_DestroyPipeline(VkDevice _device
,
2812 VkPipeline _pipeline
,
2813 const VkAllocationCallbacks
*pAllocator
)
2815 TU_FROM_HANDLE(tu_device
, dev
, _device
);
2816 TU_FROM_HANDLE(tu_pipeline
, pipeline
, _pipeline
);
2821 tu_pipeline_finish(pipeline
, dev
, pAllocator
);
2822 vk_free2(&dev
->alloc
, pAllocator
, pipeline
);