2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 #include "tu_private.h"
30 #include "main/menums.h"
32 #include "nir/nir_builder.h"
33 #include "spirv/nir_spirv.h"
34 #include "util/debug.h"
35 #include "util/mesa-sha1.h"
36 #include "util/u_atomic.h"
37 #include "vk_format.h"
42 struct tu_pipeline_builder
44 struct tu_device
*device
;
45 struct tu_pipeline_cache
*cache
;
46 struct tu_pipeline_layout
*layout
;
47 const VkAllocationCallbacks
*alloc
;
48 const VkGraphicsPipelineCreateInfo
*create_info
;
50 struct tu_shader
*shaders
[MESA_SHADER_STAGES
];
51 uint32_t shader_offsets
[MESA_SHADER_STAGES
];
52 uint32_t binning_vs_offset
;
53 uint32_t shader_total_size
;
55 bool rasterizer_discard
;
56 /* these states are affectd by rasterizer_discard */
57 VkSampleCountFlagBits samples
;
58 bool use_depth_stencil_attachment
;
59 bool use_color_attachments
;
60 uint32_t color_attachment_count
;
61 VkFormat color_attachment_formats
[MAX_RTS
];
64 static enum tu_dynamic_state_bits
65 tu_dynamic_state_bit(VkDynamicState state
)
68 case VK_DYNAMIC_STATE_VIEWPORT
:
69 return TU_DYNAMIC_VIEWPORT
;
70 case VK_DYNAMIC_STATE_SCISSOR
:
71 return TU_DYNAMIC_SCISSOR
;
72 case VK_DYNAMIC_STATE_LINE_WIDTH
:
73 return TU_DYNAMIC_LINE_WIDTH
;
74 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
75 return TU_DYNAMIC_DEPTH_BIAS
;
76 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
77 return TU_DYNAMIC_BLEND_CONSTANTS
;
78 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
79 return TU_DYNAMIC_DEPTH_BOUNDS
;
80 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
81 return TU_DYNAMIC_STENCIL_COMPARE_MASK
;
82 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
83 return TU_DYNAMIC_STENCIL_WRITE_MASK
;
84 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
85 return TU_DYNAMIC_STENCIL_REFERENCE
;
87 unreachable("invalid dynamic state");
92 static gl_shader_stage
93 tu_shader_stage(VkShaderStageFlagBits stage
)
96 case VK_SHADER_STAGE_VERTEX_BIT
:
97 return MESA_SHADER_VERTEX
;
98 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
99 return MESA_SHADER_TESS_CTRL
;
100 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
101 return MESA_SHADER_TESS_EVAL
;
102 case VK_SHADER_STAGE_GEOMETRY_BIT
:
103 return MESA_SHADER_GEOMETRY
;
104 case VK_SHADER_STAGE_FRAGMENT_BIT
:
105 return MESA_SHADER_FRAGMENT
;
106 case VK_SHADER_STAGE_COMPUTE_BIT
:
107 return MESA_SHADER_COMPUTE
;
109 unreachable("invalid VkShaderStageFlagBits");
110 return MESA_SHADER_NONE
;
114 static const VkVertexInputAttributeDescription
*
115 tu_find_vertex_input_attribute(
116 const VkPipelineVertexInputStateCreateInfo
*vi_info
, uint32_t slot
)
118 assert(slot
>= VERT_ATTRIB_GENERIC0
);
119 slot
-= VERT_ATTRIB_GENERIC0
;
120 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
121 if (vi_info
->pVertexAttributeDescriptions
[i
].location
== slot
)
122 return &vi_info
->pVertexAttributeDescriptions
[i
];
127 static const VkVertexInputBindingDescription
*
128 tu_find_vertex_input_binding(
129 const VkPipelineVertexInputStateCreateInfo
*vi_info
,
130 const VkVertexInputAttributeDescription
*vi_attr
)
133 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
134 if (vi_info
->pVertexBindingDescriptions
[i
].binding
== vi_attr
->binding
)
135 return &vi_info
->pVertexBindingDescriptions
[i
];
141 tu_logic_op_reads_dst(VkLogicOp op
)
144 case VK_LOGIC_OP_CLEAR
:
145 case VK_LOGIC_OP_COPY
:
146 case VK_LOGIC_OP_COPY_INVERTED
:
147 case VK_LOGIC_OP_SET
:
155 tu_blend_factor_no_dst_alpha(VkBlendFactor factor
)
157 /* treat dst alpha as 1.0 and avoid reading it */
159 case VK_BLEND_FACTOR_DST_ALPHA
:
160 return VK_BLEND_FACTOR_ONE
;
161 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
162 return VK_BLEND_FACTOR_ZERO
;
168 static enum pc_di_primtype
169 tu6_primtype(VkPrimitiveTopology topology
)
172 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
173 return DI_PT_POINTLIST
;
174 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
175 return DI_PT_LINELIST
;
176 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
177 return DI_PT_LINESTRIP
;
178 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
179 return DI_PT_TRILIST
;
180 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
181 return DI_PT_TRISTRIP
;
182 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
184 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
185 return DI_PT_LINE_ADJ
;
186 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
187 return DI_PT_LINESTRIP_ADJ
;
188 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
189 return DI_PT_TRI_ADJ
;
190 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
191 return DI_PT_TRISTRIP_ADJ
;
192 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
194 unreachable("invalid primitive topology");
199 static enum adreno_compare_func
200 tu6_compare_func(VkCompareOp op
)
203 case VK_COMPARE_OP_NEVER
:
205 case VK_COMPARE_OP_LESS
:
207 case VK_COMPARE_OP_EQUAL
:
209 case VK_COMPARE_OP_LESS_OR_EQUAL
:
211 case VK_COMPARE_OP_GREATER
:
213 case VK_COMPARE_OP_NOT_EQUAL
:
214 return FUNC_NOTEQUAL
;
215 case VK_COMPARE_OP_GREATER_OR_EQUAL
:
217 case VK_COMPARE_OP_ALWAYS
:
220 unreachable("invalid VkCompareOp");
225 static enum adreno_stencil_op
226 tu6_stencil_op(VkStencilOp op
)
229 case VK_STENCIL_OP_KEEP
:
231 case VK_STENCIL_OP_ZERO
:
233 case VK_STENCIL_OP_REPLACE
:
234 return STENCIL_REPLACE
;
235 case VK_STENCIL_OP_INCREMENT_AND_CLAMP
:
236 return STENCIL_INCR_CLAMP
;
237 case VK_STENCIL_OP_DECREMENT_AND_CLAMP
:
238 return STENCIL_DECR_CLAMP
;
239 case VK_STENCIL_OP_INVERT
:
240 return STENCIL_INVERT
;
241 case VK_STENCIL_OP_INCREMENT_AND_WRAP
:
242 return STENCIL_INCR_WRAP
;
243 case VK_STENCIL_OP_DECREMENT_AND_WRAP
:
244 return STENCIL_DECR_WRAP
;
246 unreachable("invalid VkStencilOp");
251 static enum a3xx_rop_code
252 tu6_rop(VkLogicOp op
)
255 case VK_LOGIC_OP_CLEAR
:
257 case VK_LOGIC_OP_AND
:
259 case VK_LOGIC_OP_AND_REVERSE
:
260 return ROP_AND_REVERSE
;
261 case VK_LOGIC_OP_COPY
:
263 case VK_LOGIC_OP_AND_INVERTED
:
264 return ROP_AND_INVERTED
;
265 case VK_LOGIC_OP_NO_OP
:
267 case VK_LOGIC_OP_XOR
:
271 case VK_LOGIC_OP_NOR
:
273 case VK_LOGIC_OP_EQUIVALENT
:
275 case VK_LOGIC_OP_INVERT
:
277 case VK_LOGIC_OP_OR_REVERSE
:
278 return ROP_OR_REVERSE
;
279 case VK_LOGIC_OP_COPY_INVERTED
:
280 return ROP_COPY_INVERTED
;
281 case VK_LOGIC_OP_OR_INVERTED
:
282 return ROP_OR_INVERTED
;
283 case VK_LOGIC_OP_NAND
:
285 case VK_LOGIC_OP_SET
:
288 unreachable("invalid VkLogicOp");
293 static enum adreno_rb_blend_factor
294 tu6_blend_factor(VkBlendFactor factor
)
297 case VK_BLEND_FACTOR_ZERO
:
299 case VK_BLEND_FACTOR_ONE
:
301 case VK_BLEND_FACTOR_SRC_COLOR
:
302 return FACTOR_SRC_COLOR
;
303 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
304 return FACTOR_ONE_MINUS_SRC_COLOR
;
305 case VK_BLEND_FACTOR_DST_COLOR
:
306 return FACTOR_DST_COLOR
;
307 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
:
308 return FACTOR_ONE_MINUS_DST_COLOR
;
309 case VK_BLEND_FACTOR_SRC_ALPHA
:
310 return FACTOR_SRC_ALPHA
;
311 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
312 return FACTOR_ONE_MINUS_SRC_ALPHA
;
313 case VK_BLEND_FACTOR_DST_ALPHA
:
314 return FACTOR_DST_ALPHA
;
315 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
316 return FACTOR_ONE_MINUS_DST_ALPHA
;
317 case VK_BLEND_FACTOR_CONSTANT_COLOR
:
318 return FACTOR_CONSTANT_COLOR
;
319 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
:
320 return FACTOR_ONE_MINUS_CONSTANT_COLOR
;
321 case VK_BLEND_FACTOR_CONSTANT_ALPHA
:
322 return FACTOR_CONSTANT_ALPHA
;
323 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
:
324 return FACTOR_ONE_MINUS_CONSTANT_ALPHA
;
325 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
326 return FACTOR_SRC_ALPHA_SATURATE
;
327 case VK_BLEND_FACTOR_SRC1_COLOR
:
328 return FACTOR_SRC1_COLOR
;
329 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
330 return FACTOR_ONE_MINUS_SRC1_COLOR
;
331 case VK_BLEND_FACTOR_SRC1_ALPHA
:
332 return FACTOR_SRC1_ALPHA
;
333 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
334 return FACTOR_ONE_MINUS_SRC1_ALPHA
;
336 unreachable("invalid VkBlendFactor");
341 static enum a3xx_rb_blend_opcode
342 tu6_blend_op(VkBlendOp op
)
345 case VK_BLEND_OP_ADD
:
346 return BLEND_DST_PLUS_SRC
;
347 case VK_BLEND_OP_SUBTRACT
:
348 return BLEND_SRC_MINUS_DST
;
349 case VK_BLEND_OP_REVERSE_SUBTRACT
:
350 return BLEND_DST_MINUS_SRC
;
351 case VK_BLEND_OP_MIN
:
352 return BLEND_MIN_DST_SRC
;
353 case VK_BLEND_OP_MAX
:
354 return BLEND_MAX_DST_SRC
;
356 unreachable("invalid VkBlendOp");
357 return BLEND_DST_PLUS_SRC
;
362 tu_shader_nibo(const struct tu_shader
*shader
)
364 /* Don't use ir3_shader_nibo(), because that would include declared but
365 * unused storage images and SSBOs.
367 return shader
->ssbo_map
.num_desc
+ shader
->image_map
.num_desc
;
371 tu6_emit_vs_config(struct tu_cs
*cs
, struct tu_shader
*shader
,
372 const struct ir3_shader_variant
*vs
)
374 uint32_t sp_vs_ctrl
=
375 A6XX_SP_VS_CTRL_REG0_THREADSIZE(FOUR_QUADS
) |
376 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs
->info
.max_reg
+ 1) |
377 A6XX_SP_VS_CTRL_REG0_MERGEDREGS
|
378 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs
->branchstack
);
380 sp_vs_ctrl
|= A6XX_SP_VS_CTRL_REG0_PIXLODENABLE
;
381 if (vs
->need_fine_derivatives
)
382 sp_vs_ctrl
|= A6XX_SP_VS_CTRL_REG0_DIFF_FINE
;
384 uint32_t sp_vs_config
= A6XX_SP_VS_CONFIG_NTEX(shader
->texture_map
.num_desc
) |
385 A6XX_SP_VS_CONFIG_NSAMP(shader
->sampler_map
.num_desc
);
387 sp_vs_config
|= A6XX_SP_VS_CONFIG_ENABLED
;
389 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_VS_CTRL_REG0
, 1);
390 tu_cs_emit(cs
, sp_vs_ctrl
);
392 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_VS_CONFIG
, 2);
393 tu_cs_emit(cs
, sp_vs_config
);
394 tu_cs_emit(cs
, vs
->instrlen
);
396 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_VS_CNTL
, 1);
397 tu_cs_emit(cs
, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(vs
->constlen
, 4)) |
398 A6XX_HLSQ_VS_CNTL_ENABLED
);
402 tu6_emit_hs_config(struct tu_cs
*cs
, struct tu_shader
*shader
,
403 const struct ir3_shader_variant
*hs
)
405 uint32_t sp_hs_config
= 0;
407 sp_hs_config
|= A6XX_SP_HS_CONFIG_ENABLED
;
409 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_HS_UNKNOWN_A831
, 1);
412 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_HS_CONFIG
, 2);
413 tu_cs_emit(cs
, sp_hs_config
);
414 tu_cs_emit(cs
, hs
->instrlen
);
416 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_HS_CNTL
, 1);
417 tu_cs_emit(cs
, A6XX_HLSQ_HS_CNTL_CONSTLEN(align(hs
->constlen
, 4)));
421 tu6_emit_ds_config(struct tu_cs
*cs
, struct tu_shader
*shader
,
422 const struct ir3_shader_variant
*ds
)
424 uint32_t sp_ds_config
= 0;
426 sp_ds_config
|= A6XX_SP_DS_CONFIG_ENABLED
;
428 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_DS_CONFIG
, 2);
429 tu_cs_emit(cs
, sp_ds_config
);
430 tu_cs_emit(cs
, ds
->instrlen
);
432 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_DS_CNTL
, 1);
433 tu_cs_emit(cs
, A6XX_HLSQ_DS_CNTL_CONSTLEN(align(ds
->constlen
, 4)));
437 tu6_emit_gs_config(struct tu_cs
*cs
, struct tu_shader
*shader
,
438 const struct ir3_shader_variant
*gs
)
440 uint32_t sp_gs_config
= 0;
442 sp_gs_config
|= A6XX_SP_GS_CONFIG_ENABLED
;
444 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_GS_UNKNOWN_A871
, 1);
447 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_GS_CONFIG
, 2);
448 tu_cs_emit(cs
, sp_gs_config
);
449 tu_cs_emit(cs
, gs
->instrlen
);
451 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_GS_CNTL
, 1);
452 tu_cs_emit(cs
, A6XX_HLSQ_GS_CNTL_CONSTLEN(align(gs
->constlen
, 4)));
456 tu6_emit_fs_config(struct tu_cs
*cs
, struct tu_shader
*shader
,
457 const struct ir3_shader_variant
*fs
)
459 uint32_t sp_fs_ctrl
=
460 A6XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS
) | 0x1000000 |
461 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs
->info
.max_reg
+ 1) |
462 A6XX_SP_FS_CTRL_REG0_MERGEDREGS
|
463 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(fs
->branchstack
);
464 if (fs
->total_in
> 0)
465 sp_fs_ctrl
|= A6XX_SP_FS_CTRL_REG0_VARYING
;
467 sp_fs_ctrl
|= A6XX_SP_FS_CTRL_REG0_PIXLODENABLE
;
468 if (fs
->need_fine_derivatives
)
469 sp_fs_ctrl
|= A6XX_SP_FS_CTRL_REG0_DIFF_FINE
;
471 uint32_t sp_fs_config
= 0;
472 unsigned shader_nibo
= 0;
474 shader_nibo
= tu_shader_nibo(shader
);
475 sp_fs_config
= A6XX_SP_FS_CONFIG_NTEX(shader
->texture_map
.num_desc
) |
476 A6XX_SP_FS_CONFIG_NSAMP(shader
->sampler_map
.num_desc
) |
477 A6XX_SP_FS_CONFIG_NIBO(shader_nibo
);
481 sp_fs_config
|= A6XX_SP_FS_CONFIG_ENABLED
;
483 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_CTRL_REG0
, 1);
484 tu_cs_emit(cs
, sp_fs_ctrl
);
486 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_CONFIG
, 2);
487 tu_cs_emit(cs
, sp_fs_config
);
488 tu_cs_emit(cs
, fs
->instrlen
);
490 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_FS_CNTL
, 1);
491 tu_cs_emit(cs
, A6XX_HLSQ_FS_CNTL_CONSTLEN(align(fs
->constlen
, 4)) |
492 A6XX_HLSQ_FS_CNTL_ENABLED
);
494 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_IBO_COUNT
, 1);
495 tu_cs_emit(cs
, shader_nibo
);
499 tu6_emit_cs_config(struct tu_cs
*cs
, const struct tu_shader
*shader
,
500 const struct ir3_shader_variant
*v
)
502 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_UPDATE_CNTL
, 1);
503 tu_cs_emit(cs
, 0xff);
505 unsigned constlen
= align(v
->constlen
, 4);
506 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_CS_CNTL
, 1);
507 tu_cs_emit(cs
, A6XX_HLSQ_CS_CNTL_CONSTLEN(constlen
) |
508 A6XX_HLSQ_CS_CNTL_ENABLED
);
510 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_CS_CONFIG
, 2);
511 tu_cs_emit(cs
, A6XX_SP_CS_CONFIG_ENABLED
|
512 A6XX_SP_CS_CONFIG_NIBO(tu_shader_nibo(shader
)) |
513 A6XX_SP_CS_CONFIG_NTEX(shader
->texture_map
.num_desc
) |
514 A6XX_SP_CS_CONFIG_NSAMP(shader
->sampler_map
.num_desc
));
515 tu_cs_emit(cs
, v
->instrlen
);
517 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_CS_CTRL_REG0
, 1);
518 tu_cs_emit(cs
, A6XX_SP_CS_CTRL_REG0_THREADSIZE(FOUR_QUADS
) |
519 A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(v
->info
.max_reg
+ 1) |
520 A6XX_SP_CS_CTRL_REG0_MERGEDREGS
|
521 A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(v
->branchstack
) |
522 COND(v
->need_pixlod
, A6XX_SP_CS_CTRL_REG0_PIXLODENABLE
) |
523 COND(v
->need_fine_derivatives
, A6XX_SP_CS_CTRL_REG0_DIFF_FINE
));
525 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_CS_UNKNOWN_A9B1
, 1);
526 tu_cs_emit(cs
, 0x41);
528 uint32_t local_invocation_id
=
529 ir3_find_sysval_regid(v
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
);
530 uint32_t work_group_id
=
531 ir3_find_sysval_regid(v
, SYSTEM_VALUE_WORK_GROUP_ID
);
533 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_CS_CNTL_0
, 2);
535 A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id
) |
536 A6XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
537 A6XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
538 A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id
));
539 tu_cs_emit(cs
, 0x2fc); /* HLSQ_CS_UNKNOWN_B998 */
541 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_CS_IBO_COUNT
, 1);
542 tu_cs_emit(cs
, tu_shader_nibo(shader
));
546 tu6_emit_vs_system_values(struct tu_cs
*cs
,
547 const struct ir3_shader_variant
*vs
)
549 const uint32_t vertexid_regid
=
550 ir3_find_sysval_regid(vs
, SYSTEM_VALUE_VERTEX_ID
);
551 const uint32_t instanceid_regid
=
552 ir3_find_sysval_regid(vs
, SYSTEM_VALUE_INSTANCE_ID
);
554 tu_cs_emit_pkt4(cs
, REG_A6XX_VFD_CONTROL_1
, 6);
555 tu_cs_emit(cs
, A6XX_VFD_CONTROL_1_REGID4VTX(vertexid_regid
) |
556 A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid
) |
558 tu_cs_emit(cs
, 0x0000fcfc); /* VFD_CONTROL_2 */
559 tu_cs_emit(cs
, 0xfcfcfcfc); /* VFD_CONTROL_3 */
560 tu_cs_emit(cs
, 0x000000fc); /* VFD_CONTROL_4 */
561 tu_cs_emit(cs
, 0x0000fcfc); /* VFD_CONTROL_5 */
562 tu_cs_emit(cs
, 0x00000000); /* VFD_CONTROL_6 */
566 tu6_emit_vpc(struct tu_cs
*cs
,
567 const struct ir3_shader_variant
*vs
,
568 const struct ir3_shader_variant
*fs
,
571 struct ir3_shader_linkage linkage
= { 0 };
572 ir3_link_shaders(&linkage
, vs
, fs
);
574 if (vs
->shader
->stream_output
.num_outputs
&& !binning_pass
)
575 tu_finishme("stream output");
577 BITSET_DECLARE(vpc_var_enables
, 128) = { 0 };
578 for (uint32_t i
= 0; i
< linkage
.cnt
; i
++) {
579 const uint32_t comp_count
= util_last_bit(linkage
.var
[i
].compmask
);
580 for (uint32_t j
= 0; j
< comp_count
; j
++)
581 BITSET_SET(vpc_var_enables
, linkage
.var
[i
].loc
+ j
);
584 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_VAR_DISABLE(0), 4);
585 tu_cs_emit(cs
, ~vpc_var_enables
[0]);
586 tu_cs_emit(cs
, ~vpc_var_enables
[1]);
587 tu_cs_emit(cs
, ~vpc_var_enables
[2]);
588 tu_cs_emit(cs
, ~vpc_var_enables
[3]);
590 /* a6xx finds position/pointsize at the end */
591 const uint32_t position_regid
=
592 ir3_find_output_regid(vs
, VARYING_SLOT_POS
);
593 const uint32_t pointsize_regid
=
594 ir3_find_output_regid(vs
, VARYING_SLOT_PSIZ
);
595 uint32_t pointsize_loc
= 0xff, position_loc
= 0xff;
596 if (position_regid
!= regid(63, 0)) {
597 position_loc
= linkage
.max_loc
;
598 ir3_link_add(&linkage
, position_regid
, 0xf, linkage
.max_loc
);
600 if (pointsize_regid
!= regid(63, 0)) {
601 pointsize_loc
= linkage
.max_loc
;
602 ir3_link_add(&linkage
, pointsize_regid
, 0x1, linkage
.max_loc
);
605 /* map vs outputs to VPC */
606 assert(linkage
.cnt
<= 32);
607 const uint32_t sp_vs_out_count
= (linkage
.cnt
+ 1) / 2;
608 const uint32_t sp_vs_vpc_dst_count
= (linkage
.cnt
+ 3) / 4;
609 uint32_t sp_vs_out
[16];
610 uint32_t sp_vs_vpc_dst
[8];
611 sp_vs_out
[sp_vs_out_count
- 1] = 0;
612 sp_vs_vpc_dst
[sp_vs_vpc_dst_count
- 1] = 0;
613 for (uint32_t i
= 0; i
< linkage
.cnt
; i
++) {
614 ((uint16_t *) sp_vs_out
)[i
] =
615 A6XX_SP_VS_OUT_REG_A_REGID(linkage
.var
[i
].regid
) |
616 A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage
.var
[i
].compmask
);
617 ((uint8_t *) sp_vs_vpc_dst
)[i
] =
618 A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage
.var
[i
].loc
);
621 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_VS_OUT_REG(0), sp_vs_out_count
);
622 tu_cs_emit_array(cs
, sp_vs_out
, sp_vs_out_count
);
624 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_VS_VPC_DST_REG(0), sp_vs_vpc_dst_count
);
625 tu_cs_emit_array(cs
, sp_vs_vpc_dst
, sp_vs_vpc_dst_count
);
627 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_CNTL_0
, 1);
628 tu_cs_emit(cs
, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs
->total_in
) |
629 (fs
->total_in
> 0 ? A6XX_VPC_CNTL_0_VARYING
: 0) |
632 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_PACK
, 1);
633 tu_cs_emit(cs
, A6XX_VPC_PACK_POSITIONLOC(position_loc
) |
634 A6XX_VPC_PACK_PSIZELOC(pointsize_loc
) |
635 A6XX_VPC_PACK_STRIDE_IN_VPC(linkage
.max_loc
));
637 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_PRIMITIVE_CNTL
, 1);
638 tu_cs_emit(cs
, A6XX_SP_PRIMITIVE_CNTL_VSOUT(linkage
.cnt
));
640 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_1
, 1);
641 tu_cs_emit(cs
, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(linkage
.max_loc
) |
642 (vs
->writes_psize
? A6XX_PC_PRIMITIVE_CNTL_1_PSIZE
: 0));
646 tu6_vpc_varying_mode(const struct ir3_shader_variant
*fs
,
648 uint8_t *interp_mode
,
649 uint8_t *ps_repl_mode
)
663 PS_REPL_ONE_MINUS_T
= 3,
666 const uint32_t compmask
= fs
->inputs
[index
].compmask
;
668 /* NOTE: varyings are packed, so if compmask is 0xb then first, second, and
669 * fourth component occupy three consecutive varying slots
674 if (fs
->inputs
[index
].slot
== VARYING_SLOT_PNTC
) {
675 if (compmask
& 0x1) {
676 *ps_repl_mode
|= PS_REPL_S
<< shift
;
679 if (compmask
& 0x2) {
680 *ps_repl_mode
|= PS_REPL_T
<< shift
;
683 if (compmask
& 0x4) {
684 *interp_mode
|= INTERP_ZERO
<< shift
;
687 if (compmask
& 0x8) {
688 *interp_mode
|= INTERP_ONE
<< 6;
691 } else if ((fs
->inputs
[index
].interpolate
== INTERP_MODE_FLAT
) ||
692 fs
->inputs
[index
].rasterflat
) {
693 for (int i
= 0; i
< 4; i
++) {
694 if (compmask
& (1 << i
)) {
695 *interp_mode
|= INTERP_FLAT
<< shift
;
705 tu6_emit_vpc_varying_modes(struct tu_cs
*cs
,
706 const struct ir3_shader_variant
*fs
,
709 uint32_t interp_modes
[8] = { 0 };
710 uint32_t ps_repl_modes
[8] = { 0 };
714 (i
= ir3_next_varying(fs
, i
)) < (int) fs
->inputs_count
;) {
716 /* get the mode for input i */
718 uint8_t ps_repl_mode
;
720 tu6_vpc_varying_mode(fs
, i
, &interp_mode
, &ps_repl_mode
);
722 /* OR the mode into the array */
723 const uint32_t inloc
= fs
->inputs
[i
].inloc
* 2;
724 uint32_t n
= inloc
/ 32;
725 uint32_t shift
= inloc
% 32;
726 interp_modes
[n
] |= interp_mode
<< shift
;
727 ps_repl_modes
[n
] |= ps_repl_mode
<< shift
;
728 if (shift
+ bits
> 32) {
732 interp_modes
[n
] |= interp_mode
>> shift
;
733 ps_repl_modes
[n
] |= ps_repl_mode
>> shift
;
738 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
739 tu_cs_emit_array(cs
, interp_modes
, 8);
741 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
742 tu_cs_emit_array(cs
, ps_repl_modes
, 8);
746 tu6_emit_fs_inputs(struct tu_cs
*cs
, const struct ir3_shader_variant
*fs
)
748 uint32_t face_regid
, coord_regid
, zwcoord_regid
, samp_id_regid
;
749 uint32_t ij_pix_regid
, ij_samp_regid
, ij_cent_regid
, ij_size_regid
;
750 uint32_t smask_in_regid
;
752 bool sample_shading
= fs
->per_samp
; /* TODO | key->sample_shading; */
753 bool enable_varyings
= fs
->total_in
> 0;
755 samp_id_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_SAMPLE_ID
);
756 smask_in_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_SAMPLE_MASK_IN
);
757 face_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_FRONT_FACE
);
758 coord_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_FRAG_COORD
);
759 zwcoord_regid
= VALIDREG(coord_regid
) ? coord_regid
+ 2 : regid(63, 0);
760 ij_pix_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL
);
761 ij_samp_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE
);
762 ij_cent_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID
);
763 ij_size_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE
);
765 if (fs
->num_sampler_prefetch
> 0) {
766 assert(VALIDREG(ij_pix_regid
));
767 /* also, it seems like ij_pix is *required* to be r0.x */
768 assert(ij_pix_regid
== regid(0, 0));
771 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_PREFETCH_CNTL
, 1 + fs
->num_sampler_prefetch
);
772 tu_cs_emit(cs
, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs
->num_sampler_prefetch
) |
773 A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
775 for (int i
= 0; i
< fs
->num_sampler_prefetch
; i
++) {
776 const struct ir3_sampler_prefetch
*prefetch
= &fs
->sampler_prefetch
[i
];
777 tu_cs_emit(cs
, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch
->src
) |
778 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch
->samp_id
) |
779 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch
->tex_id
) |
780 A6XX_SP_FS_PREFETCH_CMD_DST(prefetch
->dst
) |
781 A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch
->wrmask
) |
782 COND(prefetch
->half_precision
, A6XX_SP_FS_PREFETCH_CMD_HALF
) |
783 A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch
->cmd
));
786 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_CONTROL_1_REG
, 5);
788 tu_cs_emit(cs
, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid
) |
789 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid
) |
790 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid
) |
791 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid
));
792 tu_cs_emit(cs
, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid
) |
793 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid
) |
795 tu_cs_emit(cs
, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid
) |
796 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid
) |
797 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid
) |
799 tu_cs_emit(cs
, 0xfc);
801 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_UNKNOWN_B980
, 1);
802 tu_cs_emit(cs
, enable_varyings
? 3 : 1);
804 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_UPDATE_CNTL
, 1);
805 tu_cs_emit(cs
, 0xff); /* XXX */
807 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_CNTL
, 1);
809 CONDREG(ij_pix_regid
, A6XX_GRAS_CNTL_VARYING
) |
810 CONDREG(ij_cent_regid
, A6XX_GRAS_CNTL_CENTROID
) |
811 CONDREG(ij_samp_regid
, A6XX_GRAS_CNTL_PERSAMP_VARYING
) |
812 COND(VALIDREG(ij_size_regid
) && !sample_shading
, A6XX_GRAS_CNTL_SIZE
) |
813 COND(VALIDREG(ij_size_regid
) && sample_shading
, A6XX_GRAS_CNTL_SIZE_PERSAMP
) |
815 A6XX_GRAS_CNTL_SIZE
|
816 A6XX_GRAS_CNTL_XCOORD
|
817 A6XX_GRAS_CNTL_YCOORD
|
818 A6XX_GRAS_CNTL_ZCOORD
|
819 A6XX_GRAS_CNTL_WCOORD
) |
820 COND(fs
->frag_face
, A6XX_GRAS_CNTL_SIZE
));
822 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_RENDER_CONTROL0
, 2);
824 CONDREG(ij_pix_regid
, A6XX_RB_RENDER_CONTROL0_VARYING
) |
825 CONDREG(ij_cent_regid
, A6XX_RB_RENDER_CONTROL0_CENTROID
) |
826 CONDREG(ij_samp_regid
, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING
) |
827 COND(enable_varyings
, A6XX_RB_RENDER_CONTROL0_UNK10
) |
828 COND(VALIDREG(ij_size_regid
) && !sample_shading
, A6XX_RB_RENDER_CONTROL0_SIZE
) |
829 COND(VALIDREG(ij_size_regid
) && sample_shading
, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP
) |
831 A6XX_RB_RENDER_CONTROL0_SIZE
|
832 A6XX_RB_RENDER_CONTROL0_XCOORD
|
833 A6XX_RB_RENDER_CONTROL0_YCOORD
|
834 A6XX_RB_RENDER_CONTROL0_ZCOORD
|
835 A6XX_RB_RENDER_CONTROL0_WCOORD
) |
836 COND(fs
->frag_face
, A6XX_RB_RENDER_CONTROL0_SIZE
));
838 CONDREG(smask_in_regid
, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK
) |
839 CONDREG(samp_id_regid
, A6XX_RB_RENDER_CONTROL1_SAMPLEID
) |
840 CONDREG(ij_size_regid
, A6XX_RB_RENDER_CONTROL1_SIZE
) |
841 COND(fs
->frag_face
, A6XX_RB_RENDER_CONTROL1_FACENESS
));
843 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_SAMPLE_CNTL
, 1);
844 tu_cs_emit(cs
, COND(sample_shading
, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE
));
846 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_UNKNOWN_8101
, 1);
847 tu_cs_emit(cs
, COND(sample_shading
, 0x6)); // XXX
849 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SAMPLE_CNTL
, 1);
850 tu_cs_emit(cs
, COND(sample_shading
, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE
));
854 tu6_emit_fs_outputs(struct tu_cs
*cs
,
855 const struct ir3_shader_variant
*fs
,
858 uint32_t smask_regid
, posz_regid
;
860 posz_regid
= ir3_find_output_regid(fs
, FRAG_RESULT_DEPTH
);
861 smask_regid
= ir3_find_output_regid(fs
, FRAG_RESULT_SAMPLE_MASK
);
863 uint32_t fragdata_regid
[8];
864 if (fs
->color0_mrt
) {
865 fragdata_regid
[0] = ir3_find_output_regid(fs
, FRAG_RESULT_COLOR
);
866 for (uint32_t i
= 1; i
< ARRAY_SIZE(fragdata_regid
); i
++)
867 fragdata_regid
[i
] = fragdata_regid
[0];
869 for (uint32_t i
= 0; i
< ARRAY_SIZE(fragdata_regid
); i
++)
870 fragdata_regid
[i
] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA0
+ i
);
873 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_OUTPUT_CNTL0
, 2);
874 tu_cs_emit(cs
, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid
) |
875 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid
) |
877 tu_cs_emit(cs
, A6XX_SP_FS_OUTPUT_CNTL1_MRT(mrt_count
));
879 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
880 for (uint32_t i
= 0; i
< ARRAY_SIZE(fragdata_regid
); i
++) {
881 // TODO we could have a mix of half and full precision outputs,
882 // we really need to figure out half-precision from IR3_REG_HALF
883 tu_cs_emit(cs
, A6XX_SP_FS_OUTPUT_REG_REGID(fragdata_regid
[i
]) |
884 (false ? A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION
: 0));
887 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_FS_OUTPUT_CNTL0
, 2);
888 tu_cs_emit(cs
, COND(fs
->writes_pos
, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z
) |
889 COND(fs
->writes_smask
, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK
));
890 tu_cs_emit(cs
, A6XX_RB_FS_OUTPUT_CNTL1_MRT(mrt_count
));
892 uint32_t gras_su_depth_plane_cntl
= 0;
893 uint32_t rb_depth_plane_cntl
= 0;
894 if (fs
->no_earlyz
|| fs
->writes_pos
) {
895 gras_su_depth_plane_cntl
|= A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z
;
896 rb_depth_plane_cntl
|= A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z
;
899 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL
, 1);
900 tu_cs_emit(cs
, gras_su_depth_plane_cntl
);
902 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_PLANE_CNTL
, 1);
903 tu_cs_emit(cs
, rb_depth_plane_cntl
);
907 tu6_emit_shader_object(struct tu_cs
*cs
,
908 gl_shader_stage stage
,
909 const struct ir3_shader_variant
*variant
,
910 const struct tu_bo
*binary_bo
,
911 uint32_t binary_offset
)
915 enum a6xx_state_block sb
;
917 case MESA_SHADER_VERTEX
:
918 reg
= REG_A6XX_SP_VS_OBJ_START_LO
;
919 opcode
= CP_LOAD_STATE6_GEOM
;
922 case MESA_SHADER_TESS_CTRL
:
923 reg
= REG_A6XX_SP_HS_OBJ_START_LO
;
924 opcode
= CP_LOAD_STATE6_GEOM
;
927 case MESA_SHADER_TESS_EVAL
:
928 reg
= REG_A6XX_SP_DS_OBJ_START_LO
;
929 opcode
= CP_LOAD_STATE6_GEOM
;
932 case MESA_SHADER_GEOMETRY
:
933 reg
= REG_A6XX_SP_GS_OBJ_START_LO
;
934 opcode
= CP_LOAD_STATE6_GEOM
;
937 case MESA_SHADER_FRAGMENT
:
938 reg
= REG_A6XX_SP_FS_OBJ_START_LO
;
939 opcode
= CP_LOAD_STATE6_FRAG
;
942 case MESA_SHADER_COMPUTE
:
943 reg
= REG_A6XX_SP_CS_OBJ_START_LO
;
944 opcode
= CP_LOAD_STATE6_FRAG
;
948 unreachable("invalid gl_shader_stage");
949 opcode
= CP_LOAD_STATE6_GEOM
;
954 if (!variant
->instrlen
) {
955 tu_cs_emit_pkt4(cs
, reg
, 2);
956 tu_cs_emit_qw(cs
, 0);
960 assert(variant
->type
== stage
);
962 const uint64_t binary_iova
= binary_bo
->iova
+ binary_offset
;
963 assert((binary_iova
& 0xf) == 0);
964 /* note: it looks like HW might try to read a few instructions beyond the instrlen size
965 * of the shader. this could be a potential source of problems at some point
966 * possibly this doesn't happen if shader iova is aligned enough (to 4k for example)
969 tu_cs_emit_pkt4(cs
, reg
, 2);
970 tu_cs_emit_qw(cs
, binary_iova
);
972 /* always indirect */
973 const bool indirect
= true;
975 tu_cs_emit_pkt7(cs
, opcode
, 3);
976 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(0) |
977 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER
) |
978 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
979 CP_LOAD_STATE6_0_STATE_BLOCK(sb
) |
980 CP_LOAD_STATE6_0_NUM_UNIT(variant
->instrlen
));
981 tu_cs_emit_qw(cs
, binary_iova
);
983 const void *binary
= binary_bo
->map
+ binary_offset
;
985 tu_cs_emit_pkt7(cs
, opcode
, 3 + variant
->info
.sizedwords
);
986 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(0) |
987 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER
) |
988 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
989 CP_LOAD_STATE6_0_STATE_BLOCK(sb
) |
990 CP_LOAD_STATE6_0_NUM_UNIT(variant
->instrlen
));
991 tu_cs_emit_qw(cs
, 0);
992 tu_cs_emit_array(cs
, binary
, variant
->info
.sizedwords
);
997 tu6_emit_immediates(struct tu_cs
*cs
, const struct ir3_shader_variant
*v
,
998 uint32_t opcode
, enum a6xx_state_block block
)
1004 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
1005 uint32_t base
= const_state
->offsets
.immediate
;
1006 int size
= const_state
->immediates_count
;
1008 /* truncate size to avoid writing constants that shader
1011 size
= MIN2(size
+ base
, v
->constlen
) - base
;
1016 tu_cs_emit_pkt7(cs
, opcode
, 3 + size
* 4);
1017 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(base
) |
1018 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
1019 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
1020 CP_LOAD_STATE6_0_STATE_BLOCK(block
) |
1021 CP_LOAD_STATE6_0_NUM_UNIT(size
));
1022 tu_cs_emit(cs
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
1023 tu_cs_emit(cs
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
1025 for (unsigned i
= 0; i
< size
; i
++) {
1026 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[0]);
1027 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[1]);
1028 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[2]);
1029 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[3]);
1034 tu6_emit_program(struct tu_cs
*cs
,
1035 const struct tu_pipeline_builder
*builder
,
1036 const struct tu_bo
*binary_bo
,
1039 static const struct ir3_shader_variant dummy_variant
= {
1040 .type
= MESA_SHADER_NONE
1042 assert(builder
->shaders
[MESA_SHADER_VERTEX
]);
1043 const struct ir3_shader_variant
*vs
=
1044 &builder
->shaders
[MESA_SHADER_VERTEX
]->variants
[0];
1045 const struct ir3_shader_variant
*hs
=
1046 builder
->shaders
[MESA_SHADER_TESS_CTRL
]
1047 ? &builder
->shaders
[MESA_SHADER_TESS_CTRL
]->variants
[0]
1049 const struct ir3_shader_variant
*ds
=
1050 builder
->shaders
[MESA_SHADER_TESS_EVAL
]
1051 ? &builder
->shaders
[MESA_SHADER_TESS_EVAL
]->variants
[0]
1053 const struct ir3_shader_variant
*gs
=
1054 builder
->shaders
[MESA_SHADER_GEOMETRY
]
1055 ? &builder
->shaders
[MESA_SHADER_GEOMETRY
]->variants
[0]
1057 const struct ir3_shader_variant
*fs
=
1058 builder
->shaders
[MESA_SHADER_FRAGMENT
]
1059 ? &builder
->shaders
[MESA_SHADER_FRAGMENT
]->variants
[0]
1063 vs
= &builder
->shaders
[MESA_SHADER_VERTEX
]->variants
[1];
1064 fs
= &dummy_variant
;
1067 tu6_emit_vs_config(cs
, builder
->shaders
[MESA_SHADER_VERTEX
], vs
);
1068 tu6_emit_hs_config(cs
, builder
->shaders
[MESA_SHADER_TESS_CTRL
], hs
);
1069 tu6_emit_ds_config(cs
, builder
->shaders
[MESA_SHADER_TESS_EVAL
], ds
);
1070 tu6_emit_gs_config(cs
, builder
->shaders
[MESA_SHADER_GEOMETRY
], gs
);
1071 tu6_emit_fs_config(cs
, builder
->shaders
[MESA_SHADER_FRAGMENT
], fs
);
1073 tu6_emit_vs_system_values(cs
, vs
);
1074 tu6_emit_vpc(cs
, vs
, fs
, binning_pass
);
1075 tu6_emit_vpc_varying_modes(cs
, fs
, binning_pass
);
1076 tu6_emit_fs_inputs(cs
, fs
);
1077 tu6_emit_fs_outputs(cs
, fs
, builder
->color_attachment_count
);
1079 tu6_emit_shader_object(cs
, MESA_SHADER_VERTEX
, vs
, binary_bo
,
1080 binning_pass
? builder
->binning_vs_offset
: builder
->shader_offsets
[MESA_SHADER_VERTEX
]);
1082 tu6_emit_shader_object(cs
, MESA_SHADER_FRAGMENT
, fs
, binary_bo
,
1083 builder
->shader_offsets
[MESA_SHADER_FRAGMENT
]);
1085 tu6_emit_immediates(cs
, vs
, CP_LOAD_STATE6_GEOM
, SB6_VS_SHADER
);
1087 tu6_emit_immediates(cs
, fs
, CP_LOAD_STATE6_FRAG
, SB6_FS_SHADER
);
1091 tu6_emit_vertex_input(struct tu_cs
*cs
,
1092 const struct ir3_shader_variant
*vs
,
1093 const VkPipelineVertexInputStateCreateInfo
*vi_info
,
1094 uint8_t bindings
[MAX_VERTEX_ATTRIBS
],
1095 uint16_t strides
[MAX_VERTEX_ATTRIBS
],
1096 uint16_t offsets
[MAX_VERTEX_ATTRIBS
],
1099 uint32_t vfd_decode_idx
= 0;
1101 for (uint32_t i
= 0; i
< vs
->inputs_count
; i
++) {
1102 if (vs
->inputs
[i
].sysval
|| !vs
->inputs
[i
].compmask
)
1105 const VkVertexInputAttributeDescription
*vi_attr
=
1106 tu_find_vertex_input_attribute(vi_info
, vs
->inputs
[i
].slot
);
1107 const VkVertexInputBindingDescription
*vi_binding
=
1108 tu_find_vertex_input_binding(vi_info
, vi_attr
);
1109 assert(vi_attr
&& vi_binding
);
1111 const struct tu_native_format format
= tu6_format_vtx(vi_attr
->format
);
1113 uint32_t vfd_decode
= A6XX_VFD_DECODE_INSTR_IDX(vfd_decode_idx
) |
1114 A6XX_VFD_DECODE_INSTR_FORMAT(format
.fmt
) |
1115 A6XX_VFD_DECODE_INSTR_SWAP(format
.swap
) |
1116 A6XX_VFD_DECODE_INSTR_UNK30
;
1117 if (vi_binding
->inputRate
== VK_VERTEX_INPUT_RATE_INSTANCE
)
1118 vfd_decode
|= A6XX_VFD_DECODE_INSTR_INSTANCED
;
1119 if (!vk_format_is_int(vi_attr
->format
))
1120 vfd_decode
|= A6XX_VFD_DECODE_INSTR_FLOAT
;
1122 const uint32_t vfd_decode_step_rate
= 1;
1124 const uint32_t vfd_dest_cntl
=
1125 A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vs
->inputs
[i
].compmask
) |
1126 A6XX_VFD_DEST_CNTL_INSTR_REGID(vs
->inputs
[i
].regid
);
1128 tu_cs_emit_pkt4(cs
, REG_A6XX_VFD_DECODE(vfd_decode_idx
), 2);
1129 tu_cs_emit(cs
, vfd_decode
);
1130 tu_cs_emit(cs
, vfd_decode_step_rate
);
1132 tu_cs_emit_pkt4(cs
, REG_A6XX_VFD_DEST_CNTL(vfd_decode_idx
), 1);
1133 tu_cs_emit(cs
, vfd_dest_cntl
);
1135 bindings
[vfd_decode_idx
] = vi_binding
->binding
;
1136 strides
[vfd_decode_idx
] = vi_binding
->stride
;
1137 offsets
[vfd_decode_idx
] = vi_attr
->offset
;
1140 assert(vfd_decode_idx
<= MAX_VERTEX_ATTRIBS
);
1143 tu_cs_emit_pkt4(cs
, REG_A6XX_VFD_CONTROL_0
, 1);
1145 cs
, A6XX_VFD_CONTROL_0_VTXCNT(vfd_decode_idx
) | (vfd_decode_idx
<< 8));
1147 *count
= vfd_decode_idx
;
1151 tu6_guardband_adj(uint32_t v
)
1154 return (uint32_t)(511.0 - 65.0 * (log2(v
) - 8.0));
1160 tu6_emit_viewport(struct tu_cs
*cs
, const VkViewport
*viewport
)
1164 scales
[0] = viewport
->width
/ 2.0f
;
1165 scales
[1] = viewport
->height
/ 2.0f
;
1166 scales
[2] = viewport
->maxDepth
- viewport
->minDepth
;
1167 offsets
[0] = viewport
->x
+ scales
[0];
1168 offsets
[1] = viewport
->y
+ scales
[1];
1169 offsets
[2] = viewport
->minDepth
;
1173 min
.x
= (int32_t) viewport
->x
;
1174 max
.x
= (int32_t) ceilf(viewport
->x
+ viewport
->width
);
1175 if (viewport
->height
>= 0.0f
) {
1176 min
.y
= (int32_t) viewport
->y
;
1177 max
.y
= (int32_t) ceilf(viewport
->y
+ viewport
->height
);
1179 min
.y
= (int32_t)(viewport
->y
+ viewport
->height
);
1180 max
.y
= (int32_t) ceilf(viewport
->y
);
1182 /* the spec allows viewport->height to be 0.0f */
1185 assert(min
.x
>= 0 && min
.x
< max
.x
);
1186 assert(min
.y
>= 0 && min
.y
< max
.y
);
1188 VkExtent2D guardband_adj
;
1189 guardband_adj
.width
= tu6_guardband_adj(max
.x
- min
.x
);
1190 guardband_adj
.height
= tu6_guardband_adj(max
.y
- min
.y
);
1192 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0
, 6);
1193 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_XOFFSET_0(offsets
[0]).value
);
1194 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_XSCALE_0(scales
[0]).value
);
1195 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_YOFFSET_0(offsets
[1]).value
);
1196 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_YSCALE_0(scales
[1]).value
);
1197 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_ZOFFSET_0(offsets
[2]).value
);
1198 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_ZSCALE_0(scales
[2]).value
);
1200 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0
, 2);
1201 tu_cs_emit(cs
, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(min
.x
) |
1202 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(min
.y
));
1203 tu_cs_emit(cs
, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(max
.x
- 1) |
1204 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(max
.y
- 1));
1206 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ
, 1);
1208 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_adj
.width
) |
1209 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_adj
.height
));
1213 tu6_emit_scissor(struct tu_cs
*cs
, const VkRect2D
*scissor
)
1215 const VkOffset2D min
= scissor
->offset
;
1216 const VkOffset2D max
= {
1217 scissor
->offset
.x
+ scissor
->extent
.width
,
1218 scissor
->offset
.y
+ scissor
->extent
.height
,
1221 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0
, 2);
1222 tu_cs_emit(cs
, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(min
.x
) |
1223 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(min
.y
));
1224 tu_cs_emit(cs
, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(max
.x
- 1) |
1225 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(max
.y
- 1));
1229 tu6_emit_gras_unknowns(struct tu_cs
*cs
)
1231 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_DISABLE_CNTL
, 1);
1232 tu_cs_emit(cs
, A6XX_GRAS_DISABLE_CNTL_VP_CLIP_CODE_IGNORE
);
1233 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_UNKNOWN_8001
, 1);
1234 tu_cs_emit(cs
, 0x0);
1235 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_LAYER_CNTL
, 1);
1236 tu_cs_emit(cs
, 0x0);
1240 tu6_emit_point_size(struct tu_cs
*cs
)
1242 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SU_POINT_MINMAX
, 2);
1243 tu_cs_emit(cs
, A6XX_GRAS_SU_POINT_MINMAX_MIN(1.0f
/ 16.0f
) |
1244 A6XX_GRAS_SU_POINT_MINMAX_MAX(4092.0f
));
1245 tu_cs_emit(cs
, A6XX_GRAS_SU_POINT_SIZE(1.0f
).value
);
1249 tu6_gras_su_cntl(const VkPipelineRasterizationStateCreateInfo
*rast_info
,
1250 VkSampleCountFlagBits samples
)
1252 uint32_t gras_su_cntl
= 0;
1254 if (rast_info
->cullMode
& VK_CULL_MODE_FRONT_BIT
)
1255 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_CULL_FRONT
;
1256 if (rast_info
->cullMode
& VK_CULL_MODE_BACK_BIT
)
1257 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_CULL_BACK
;
1259 if (rast_info
->frontFace
== VK_FRONT_FACE_CLOCKWISE
)
1260 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_FRONT_CW
;
1262 /* don't set A6XX_GRAS_SU_CNTL_LINEHALFWIDTH */
1264 if (rast_info
->depthBiasEnable
)
1265 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_POLY_OFFSET
;
1267 if (samples
> VK_SAMPLE_COUNT_1_BIT
)
1268 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_MSAA_ENABLE
;
1270 return gras_su_cntl
;
1274 tu6_emit_gras_su_cntl(struct tu_cs
*cs
,
1275 uint32_t gras_su_cntl
,
1278 assert((gras_su_cntl
& A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK
) == 0);
1279 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(line_width
/ 2.0f
);
1281 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SU_CNTL
, 1);
1282 tu_cs_emit(cs
, gras_su_cntl
);
1286 tu6_emit_depth_bias(struct tu_cs
*cs
,
1287 float constant_factor
,
1291 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE
, 3);
1292 tu_cs_emit(cs
, A6XX_GRAS_SU_POLY_OFFSET_SCALE(slope_factor
).value
);
1293 tu_cs_emit(cs
, A6XX_GRAS_SU_POLY_OFFSET_OFFSET(constant_factor
).value
);
1294 tu_cs_emit(cs
, A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(clamp
).value
);
1298 tu6_emit_alpha_control_disable(struct tu_cs
*cs
)
1300 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_ALPHA_CONTROL
, 1);
1305 tu6_emit_depth_control(struct tu_cs
*cs
,
1306 const VkPipelineDepthStencilStateCreateInfo
*ds_info
)
1308 assert(!ds_info
->depthBoundsTestEnable
);
1310 uint32_t rb_depth_cntl
= 0;
1311 if (ds_info
->depthTestEnable
) {
1313 A6XX_RB_DEPTH_CNTL_Z_ENABLE
|
1314 A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info
->depthCompareOp
)) |
1315 A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE
;
1317 if (ds_info
->depthWriteEnable
)
1318 rb_depth_cntl
|= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE
;
1321 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_CNTL
, 1);
1322 tu_cs_emit(cs
, rb_depth_cntl
);
1326 tu6_emit_stencil_control(struct tu_cs
*cs
,
1327 const VkPipelineDepthStencilStateCreateInfo
*ds_info
)
1329 uint32_t rb_stencil_control
= 0;
1330 if (ds_info
->stencilTestEnable
) {
1331 const VkStencilOpState
*front
= &ds_info
->front
;
1332 const VkStencilOpState
*back
= &ds_info
->back
;
1333 rb_stencil_control
|=
1334 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE
|
1335 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF
|
1336 A6XX_RB_STENCIL_CONTROL_STENCIL_READ
|
1337 A6XX_RB_STENCIL_CONTROL_FUNC(tu6_compare_func(front
->compareOp
)) |
1338 A6XX_RB_STENCIL_CONTROL_FAIL(tu6_stencil_op(front
->failOp
)) |
1339 A6XX_RB_STENCIL_CONTROL_ZPASS(tu6_stencil_op(front
->passOp
)) |
1340 A6XX_RB_STENCIL_CONTROL_ZFAIL(tu6_stencil_op(front
->depthFailOp
)) |
1341 A6XX_RB_STENCIL_CONTROL_FUNC_BF(tu6_compare_func(back
->compareOp
)) |
1342 A6XX_RB_STENCIL_CONTROL_FAIL_BF(tu6_stencil_op(back
->failOp
)) |
1343 A6XX_RB_STENCIL_CONTROL_ZPASS_BF(tu6_stencil_op(back
->passOp
)) |
1344 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(tu6_stencil_op(back
->depthFailOp
));
1347 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCIL_CONTROL
, 1);
1348 tu_cs_emit(cs
, rb_stencil_control
);
1352 tu6_emit_stencil_compare_mask(struct tu_cs
*cs
, uint32_t front
, uint32_t back
)
1354 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCILMASK
, 1);
1356 cs
, A6XX_RB_STENCILMASK_MASK(front
) | A6XX_RB_STENCILMASK_BFMASK(back
));
1360 tu6_emit_stencil_write_mask(struct tu_cs
*cs
, uint32_t front
, uint32_t back
)
1362 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCILWRMASK
, 1);
1363 tu_cs_emit(cs
, A6XX_RB_STENCILWRMASK_WRMASK(front
) |
1364 A6XX_RB_STENCILWRMASK_BFWRMASK(back
));
1368 tu6_emit_stencil_reference(struct tu_cs
*cs
, uint32_t front
, uint32_t back
)
1370 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCILREF
, 1);
1372 A6XX_RB_STENCILREF_REF(front
) | A6XX_RB_STENCILREF_BFREF(back
));
1376 tu6_rb_mrt_blend_control(const VkPipelineColorBlendAttachmentState
*att
,
1379 const enum a3xx_rb_blend_opcode color_op
= tu6_blend_op(att
->colorBlendOp
);
1380 const enum adreno_rb_blend_factor src_color_factor
= tu6_blend_factor(
1381 has_alpha
? att
->srcColorBlendFactor
1382 : tu_blend_factor_no_dst_alpha(att
->srcColorBlendFactor
));
1383 const enum adreno_rb_blend_factor dst_color_factor
= tu6_blend_factor(
1384 has_alpha
? att
->dstColorBlendFactor
1385 : tu_blend_factor_no_dst_alpha(att
->dstColorBlendFactor
));
1386 const enum a3xx_rb_blend_opcode alpha_op
= tu6_blend_op(att
->alphaBlendOp
);
1387 const enum adreno_rb_blend_factor src_alpha_factor
=
1388 tu6_blend_factor(att
->srcAlphaBlendFactor
);
1389 const enum adreno_rb_blend_factor dst_alpha_factor
=
1390 tu6_blend_factor(att
->dstAlphaBlendFactor
);
1392 return A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(src_color_factor
) |
1393 A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(color_op
) |
1394 A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(dst_color_factor
) |
1395 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(src_alpha_factor
) |
1396 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(alpha_op
) |
1397 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(dst_alpha_factor
);
1401 tu6_rb_mrt_control(const VkPipelineColorBlendAttachmentState
*att
,
1402 uint32_t rb_mrt_control_rop
,
1406 uint32_t rb_mrt_control
=
1407 A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(att
->colorWriteMask
);
1409 /* ignore blending and logic op for integer attachments */
1411 rb_mrt_control
|= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY
);
1412 return rb_mrt_control
;
1415 rb_mrt_control
|= rb_mrt_control_rop
;
1417 if (att
->blendEnable
) {
1418 rb_mrt_control
|= A6XX_RB_MRT_CONTROL_BLEND
;
1421 rb_mrt_control
|= A6XX_RB_MRT_CONTROL_BLEND2
;
1424 return rb_mrt_control
;
1428 tu6_emit_rb_mrt_controls(struct tu_cs
*cs
,
1429 const VkPipelineColorBlendStateCreateInfo
*blend_info
,
1430 const VkFormat attachment_formats
[MAX_RTS
],
1431 uint32_t *blend_enable_mask
)
1433 *blend_enable_mask
= 0;
1435 bool rop_reads_dst
= false;
1436 uint32_t rb_mrt_control_rop
= 0;
1437 if (blend_info
->logicOpEnable
) {
1438 rop_reads_dst
= tu_logic_op_reads_dst(blend_info
->logicOp
);
1439 rb_mrt_control_rop
=
1440 A6XX_RB_MRT_CONTROL_ROP_ENABLE
|
1441 A6XX_RB_MRT_CONTROL_ROP_CODE(tu6_rop(blend_info
->logicOp
));
1444 for (uint32_t i
= 0; i
< blend_info
->attachmentCount
; i
++) {
1445 const VkPipelineColorBlendAttachmentState
*att
=
1446 &blend_info
->pAttachments
[i
];
1447 const VkFormat format
= attachment_formats
[i
];
1449 uint32_t rb_mrt_control
= 0;
1450 uint32_t rb_mrt_blend_control
= 0;
1451 if (format
!= VK_FORMAT_UNDEFINED
) {
1452 const bool is_int
= vk_format_is_int(format
);
1453 const bool has_alpha
= vk_format_has_alpha(format
);
1456 tu6_rb_mrt_control(att
, rb_mrt_control_rop
, is_int
, has_alpha
);
1457 rb_mrt_blend_control
= tu6_rb_mrt_blend_control(att
, has_alpha
);
1459 if (att
->blendEnable
|| rop_reads_dst
)
1460 *blend_enable_mask
|= 1 << i
;
1463 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_MRT_CONTROL(i
), 2);
1464 tu_cs_emit(cs
, rb_mrt_control
);
1465 tu_cs_emit(cs
, rb_mrt_blend_control
);
1470 tu6_emit_blend_control(struct tu_cs
*cs
,
1471 uint32_t blend_enable_mask
,
1472 const VkPipelineMultisampleStateCreateInfo
*msaa_info
)
1474 assert(!msaa_info
->alphaToOneEnable
);
1476 uint32_t sp_blend_cntl
= A6XX_SP_BLEND_CNTL_UNK8
;
1477 if (blend_enable_mask
)
1478 sp_blend_cntl
|= A6XX_SP_BLEND_CNTL_ENABLED
;
1479 if (msaa_info
->alphaToCoverageEnable
)
1480 sp_blend_cntl
|= A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE
;
1482 const uint32_t sample_mask
=
1483 msaa_info
->pSampleMask
? *msaa_info
->pSampleMask
1484 : ((1 << msaa_info
->rasterizationSamples
) - 1);
1486 /* set A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND only when enabled? */
1487 uint32_t rb_blend_cntl
=
1488 A6XX_RB_BLEND_CNTL_ENABLE_BLEND(blend_enable_mask
) |
1489 A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND
|
1490 A6XX_RB_BLEND_CNTL_SAMPLE_MASK(sample_mask
);
1491 if (msaa_info
->alphaToCoverageEnable
)
1492 rb_blend_cntl
|= A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE
;
1494 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_BLEND_CNTL
, 1);
1495 tu_cs_emit(cs
, sp_blend_cntl
);
1497 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_BLEND_CNTL
, 1);
1498 tu_cs_emit(cs
, rb_blend_cntl
);
1502 tu6_emit_blend_constants(struct tu_cs
*cs
, const float constants
[4])
1504 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_BLEND_RED_F32
, 4);
1505 tu_cs_emit_array(cs
, (const uint32_t *) constants
, 4);
1509 tu_pipeline_create(struct tu_device
*dev
,
1510 const VkAllocationCallbacks
*pAllocator
,
1511 struct tu_pipeline
**out_pipeline
)
1513 struct tu_pipeline
*pipeline
=
1514 vk_zalloc2(&dev
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
1515 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1517 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1519 tu_cs_init(&pipeline
->cs
, dev
, TU_CS_MODE_SUB_STREAM
, 2048);
1521 /* reserve the space now such that tu_cs_begin_sub_stream never fails */
1522 VkResult result
= tu_cs_reserve_space(&pipeline
->cs
, 2048);
1523 if (result
!= VK_SUCCESS
) {
1524 vk_free2(&dev
->alloc
, pAllocator
, pipeline
);
1528 *out_pipeline
= pipeline
;
1534 tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder
*builder
)
1536 const VkPipelineShaderStageCreateInfo
*stage_infos
[MESA_SHADER_STAGES
] = {
1539 for (uint32_t i
= 0; i
< builder
->create_info
->stageCount
; i
++) {
1540 gl_shader_stage stage
=
1541 tu_shader_stage(builder
->create_info
->pStages
[i
].stage
);
1542 stage_infos
[stage
] = &builder
->create_info
->pStages
[i
];
1545 struct tu_shader_compile_options options
;
1546 tu_shader_compile_options_init(&options
, builder
->create_info
);
1548 /* compile shaders in reverse order */
1549 struct tu_shader
*next_stage_shader
= NULL
;
1550 for (gl_shader_stage stage
= MESA_SHADER_STAGES
- 1;
1551 stage
> MESA_SHADER_NONE
; stage
--) {
1552 const VkPipelineShaderStageCreateInfo
*stage_info
= stage_infos
[stage
];
1556 struct tu_shader
*shader
=
1557 tu_shader_create(builder
->device
, stage
, stage_info
, builder
->layout
,
1560 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1563 tu_shader_compile(builder
->device
, shader
, next_stage_shader
,
1564 &options
, builder
->alloc
);
1565 if (result
!= VK_SUCCESS
)
1568 builder
->shaders
[stage
] = shader
;
1569 builder
->shader_offsets
[stage
] = builder
->shader_total_size
;
1570 builder
->shader_total_size
+=
1571 sizeof(uint32_t) * shader
->variants
[0].info
.sizedwords
;
1573 next_stage_shader
= shader
;
1576 if (builder
->shaders
[MESA_SHADER_VERTEX
]->has_binning_pass
) {
1577 const struct tu_shader
*vs
= builder
->shaders
[MESA_SHADER_VERTEX
];
1578 builder
->binning_vs_offset
= builder
->shader_total_size
;
1579 builder
->shader_total_size
+=
1580 sizeof(uint32_t) * vs
->variants
[1].info
.sizedwords
;
1587 tu_pipeline_builder_upload_shaders(struct tu_pipeline_builder
*builder
,
1588 struct tu_pipeline
*pipeline
)
1590 struct tu_bo
*bo
= &pipeline
->program
.binary_bo
;
1593 tu_bo_init_new(builder
->device
, bo
, builder
->shader_total_size
);
1594 if (result
!= VK_SUCCESS
)
1597 result
= tu_bo_map(builder
->device
, bo
);
1598 if (result
!= VK_SUCCESS
)
1601 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
1602 const struct tu_shader
*shader
= builder
->shaders
[i
];
1606 memcpy(bo
->map
+ builder
->shader_offsets
[i
], shader
->binary
,
1607 sizeof(uint32_t) * shader
->variants
[0].info
.sizedwords
);
1610 if (builder
->shaders
[MESA_SHADER_VERTEX
]->has_binning_pass
) {
1611 const struct tu_shader
*vs
= builder
->shaders
[MESA_SHADER_VERTEX
];
1612 memcpy(bo
->map
+ builder
->binning_vs_offset
, vs
->binning_binary
,
1613 sizeof(uint32_t) * vs
->variants
[1].info
.sizedwords
);
1620 tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder
*builder
,
1621 struct tu_pipeline
*pipeline
)
1623 const VkPipelineDynamicStateCreateInfo
*dynamic_info
=
1624 builder
->create_info
->pDynamicState
;
1629 for (uint32_t i
= 0; i
< dynamic_info
->dynamicStateCount
; i
++) {
1630 pipeline
->dynamic_state
.mask
|=
1631 tu_dynamic_state_bit(dynamic_info
->pDynamicStates
[i
]);
1636 tu_pipeline_set_linkage(struct tu_program_descriptor_linkage
*link
,
1637 struct tu_shader
*shader
,
1638 struct ir3_shader_variant
*v
)
1640 link
->ubo_state
= v
->shader
->ubo_state
;
1641 link
->const_state
= v
->shader
->const_state
;
1642 link
->constlen
= v
->constlen
;
1643 link
->texture_map
= shader
->texture_map
;
1644 link
->sampler_map
= shader
->sampler_map
;
1645 link
->ubo_map
= shader
->ubo_map
;
1646 link
->ssbo_map
= shader
->ssbo_map
;
1647 link
->image_map
= shader
->image_map
;
1651 tu_pipeline_builder_parse_shader_stages(struct tu_pipeline_builder
*builder
,
1652 struct tu_pipeline
*pipeline
)
1654 struct tu_cs prog_cs
;
1655 tu_cs_begin_sub_stream(&pipeline
->cs
, 512, &prog_cs
);
1656 tu6_emit_program(&prog_cs
, builder
, &pipeline
->program
.binary_bo
, false);
1657 pipeline
->program
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &prog_cs
);
1659 tu_cs_begin_sub_stream(&pipeline
->cs
, 512, &prog_cs
);
1660 tu6_emit_program(&prog_cs
, builder
, &pipeline
->program
.binary_bo
, true);
1661 pipeline
->program
.binning_state_ib
=
1662 tu_cs_end_sub_stream(&pipeline
->cs
, &prog_cs
);
1664 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
1665 if (!builder
->shaders
[i
])
1668 tu_pipeline_set_linkage(&pipeline
->program
.link
[i
],
1669 builder
->shaders
[i
],
1670 &builder
->shaders
[i
]->variants
[0]);
1675 tu_pipeline_builder_parse_vertex_input(struct tu_pipeline_builder
*builder
,
1676 struct tu_pipeline
*pipeline
)
1678 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1679 builder
->create_info
->pVertexInputState
;
1680 const struct tu_shader
*vs
= builder
->shaders
[MESA_SHADER_VERTEX
];
1683 tu_cs_begin_sub_stream(&pipeline
->cs
,
1684 MAX_VERTEX_ATTRIBS
* 5 + 2, &vi_cs
);
1685 tu6_emit_vertex_input(&vi_cs
, &vs
->variants
[0], vi_info
,
1686 pipeline
->vi
.bindings
, pipeline
->vi
.strides
,
1687 pipeline
->vi
.offsets
, &pipeline
->vi
.count
);
1688 pipeline
->vi
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &vi_cs
);
1690 if (vs
->has_binning_pass
) {
1691 tu_cs_begin_sub_stream(&pipeline
->cs
,
1692 MAX_VERTEX_ATTRIBS
* 5 + 2, &vi_cs
);
1693 tu6_emit_vertex_input(
1694 &vi_cs
, &vs
->variants
[1], vi_info
, pipeline
->vi
.binning_bindings
,
1695 pipeline
->vi
.binning_strides
, pipeline
->vi
.binning_offsets
,
1696 &pipeline
->vi
.binning_count
);
1697 pipeline
->vi
.binning_state_ib
=
1698 tu_cs_end_sub_stream(&pipeline
->cs
, &vi_cs
);
1703 tu_pipeline_builder_parse_input_assembly(struct tu_pipeline_builder
*builder
,
1704 struct tu_pipeline
*pipeline
)
1706 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
1707 builder
->create_info
->pInputAssemblyState
;
1709 pipeline
->ia
.primtype
= tu6_primtype(ia_info
->topology
);
1710 pipeline
->ia
.primitive_restart
= ia_info
->primitiveRestartEnable
;
1714 tu_pipeline_builder_parse_viewport(struct tu_pipeline_builder
*builder
,
1715 struct tu_pipeline
*pipeline
)
1719 * pViewportState is a pointer to an instance of the
1720 * VkPipelineViewportStateCreateInfo structure, and is ignored if the
1721 * pipeline has rasterization disabled."
1723 * We leave the relevant registers stale in that case.
1725 if (builder
->rasterizer_discard
)
1728 const VkPipelineViewportStateCreateInfo
*vp_info
=
1729 builder
->create_info
->pViewportState
;
1732 tu_cs_begin_sub_stream(&pipeline
->cs
, 15, &vp_cs
);
1734 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_VIEWPORT
)) {
1735 assert(vp_info
->viewportCount
== 1);
1736 tu6_emit_viewport(&vp_cs
, vp_info
->pViewports
);
1739 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_SCISSOR
)) {
1740 assert(vp_info
->scissorCount
== 1);
1741 tu6_emit_scissor(&vp_cs
, vp_info
->pScissors
);
1744 pipeline
->vp
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &vp_cs
);
1748 tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder
*builder
,
1749 struct tu_pipeline
*pipeline
)
1751 const VkPipelineRasterizationStateCreateInfo
*rast_info
=
1752 builder
->create_info
->pRasterizationState
;
1754 assert(!rast_info
->depthClampEnable
);
1755 assert(rast_info
->polygonMode
== VK_POLYGON_MODE_FILL
);
1757 struct tu_cs rast_cs
;
1758 tu_cs_begin_sub_stream(&pipeline
->cs
, 20, &rast_cs
);
1760 /* move to hw ctx init? */
1761 tu6_emit_gras_unknowns(&rast_cs
);
1762 tu6_emit_point_size(&rast_cs
);
1764 const uint32_t gras_su_cntl
=
1765 tu6_gras_su_cntl(rast_info
, builder
->samples
);
1767 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_LINE_WIDTH
))
1768 tu6_emit_gras_su_cntl(&rast_cs
, gras_su_cntl
, rast_info
->lineWidth
);
1770 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_DEPTH_BIAS
)) {
1771 tu6_emit_depth_bias(&rast_cs
, rast_info
->depthBiasConstantFactor
,
1772 rast_info
->depthBiasClamp
,
1773 rast_info
->depthBiasSlopeFactor
);
1776 pipeline
->rast
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &rast_cs
);
1778 pipeline
->rast
.gras_su_cntl
= gras_su_cntl
;
1782 tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder
*builder
,
1783 struct tu_pipeline
*pipeline
)
1787 * pDepthStencilState is a pointer to an instance of the
1788 * VkPipelineDepthStencilStateCreateInfo structure, and is ignored if
1789 * the pipeline has rasterization disabled or if the subpass of the
1790 * render pass the pipeline is created against does not use a
1791 * depth/stencil attachment.
1793 * We disable both depth and stenil tests in those cases.
1795 static const VkPipelineDepthStencilStateCreateInfo dummy_ds_info
;
1796 const VkPipelineDepthStencilStateCreateInfo
*ds_info
=
1797 builder
->use_depth_stencil_attachment
1798 ? builder
->create_info
->pDepthStencilState
1802 tu_cs_begin_sub_stream(&pipeline
->cs
, 12, &ds_cs
);
1804 /* move to hw ctx init? */
1805 tu6_emit_alpha_control_disable(&ds_cs
);
1807 tu6_emit_depth_control(&ds_cs
, ds_info
);
1808 tu6_emit_stencil_control(&ds_cs
, ds_info
);
1810 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_COMPARE_MASK
)) {
1811 tu6_emit_stencil_compare_mask(&ds_cs
, ds_info
->front
.compareMask
,
1812 ds_info
->back
.compareMask
);
1814 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_WRITE_MASK
)) {
1815 tu6_emit_stencil_write_mask(&ds_cs
, ds_info
->front
.writeMask
,
1816 ds_info
->back
.writeMask
);
1818 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_REFERENCE
)) {
1819 tu6_emit_stencil_reference(&ds_cs
, ds_info
->front
.reference
,
1820 ds_info
->back
.reference
);
1823 pipeline
->ds
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &ds_cs
);
1827 tu_pipeline_builder_parse_multisample_and_color_blend(
1828 struct tu_pipeline_builder
*builder
, struct tu_pipeline
*pipeline
)
1832 * pMultisampleState is a pointer to an instance of the
1833 * VkPipelineMultisampleStateCreateInfo, and is ignored if the pipeline
1834 * has rasterization disabled.
1838 * pColorBlendState is a pointer to an instance of the
1839 * VkPipelineColorBlendStateCreateInfo structure, and is ignored if the
1840 * pipeline has rasterization disabled or if the subpass of the render
1841 * pass the pipeline is created against does not use any color
1844 * We leave the relevant registers stale when rasterization is disabled.
1846 if (builder
->rasterizer_discard
)
1849 static const VkPipelineColorBlendStateCreateInfo dummy_blend_info
;
1850 const VkPipelineMultisampleStateCreateInfo
*msaa_info
=
1851 builder
->create_info
->pMultisampleState
;
1852 const VkPipelineColorBlendStateCreateInfo
*blend_info
=
1853 builder
->use_color_attachments
? builder
->create_info
->pColorBlendState
1854 : &dummy_blend_info
;
1856 struct tu_cs blend_cs
;
1857 tu_cs_begin_sub_stream(&pipeline
->cs
, MAX_RTS
* 3 + 9, &blend_cs
);
1859 uint32_t blend_enable_mask
;
1860 tu6_emit_rb_mrt_controls(&blend_cs
, blend_info
,
1861 builder
->color_attachment_formats
,
1862 &blend_enable_mask
);
1864 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_BLEND_CONSTANTS
))
1865 tu6_emit_blend_constants(&blend_cs
, blend_info
->blendConstants
);
1867 tu6_emit_blend_control(&blend_cs
, blend_enable_mask
, msaa_info
);
1869 pipeline
->blend
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &blend_cs
);
1873 tu_pipeline_finish(struct tu_pipeline
*pipeline
,
1874 struct tu_device
*dev
,
1875 const VkAllocationCallbacks
*alloc
)
1877 tu_cs_finish(&pipeline
->cs
);
1879 if (pipeline
->program
.binary_bo
.gem_handle
)
1880 tu_bo_finish(dev
, &pipeline
->program
.binary_bo
);
1884 tu_pipeline_builder_build(struct tu_pipeline_builder
*builder
,
1885 struct tu_pipeline
**pipeline
)
1887 VkResult result
= tu_pipeline_create(builder
->device
, builder
->alloc
,
1889 if (result
!= VK_SUCCESS
)
1892 /* compile and upload shaders */
1893 result
= tu_pipeline_builder_compile_shaders(builder
);
1894 if (result
== VK_SUCCESS
)
1895 result
= tu_pipeline_builder_upload_shaders(builder
, *pipeline
);
1896 if (result
!= VK_SUCCESS
) {
1897 tu_pipeline_finish(*pipeline
, builder
->device
, builder
->alloc
);
1898 vk_free2(&builder
->device
->alloc
, builder
->alloc
, *pipeline
);
1899 *pipeline
= VK_NULL_HANDLE
;
1904 tu_pipeline_builder_parse_dynamic(builder
, *pipeline
);
1905 tu_pipeline_builder_parse_shader_stages(builder
, *pipeline
);
1906 tu_pipeline_builder_parse_vertex_input(builder
, *pipeline
);
1907 tu_pipeline_builder_parse_input_assembly(builder
, *pipeline
);
1908 tu_pipeline_builder_parse_viewport(builder
, *pipeline
);
1909 tu_pipeline_builder_parse_rasterization(builder
, *pipeline
);
1910 tu_pipeline_builder_parse_depth_stencil(builder
, *pipeline
);
1911 tu_pipeline_builder_parse_multisample_and_color_blend(builder
, *pipeline
);
1913 /* we should have reserved enough space upfront such that the CS never
1916 assert((*pipeline
)->cs
.bo_count
== 1);
1922 tu_pipeline_builder_finish(struct tu_pipeline_builder
*builder
)
1924 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
1925 if (!builder
->shaders
[i
])
1927 tu_shader_destroy(builder
->device
, builder
->shaders
[i
], builder
->alloc
);
1932 tu_pipeline_builder_init_graphics(
1933 struct tu_pipeline_builder
*builder
,
1934 struct tu_device
*dev
,
1935 struct tu_pipeline_cache
*cache
,
1936 const VkGraphicsPipelineCreateInfo
*create_info
,
1937 const VkAllocationCallbacks
*alloc
)
1939 TU_FROM_HANDLE(tu_pipeline_layout
, layout
, create_info
->layout
);
1941 *builder
= (struct tu_pipeline_builder
) {
1944 .create_info
= create_info
,
1949 builder
->rasterizer_discard
=
1950 create_info
->pRasterizationState
->rasterizerDiscardEnable
;
1952 if (builder
->rasterizer_discard
) {
1953 builder
->samples
= VK_SAMPLE_COUNT_1_BIT
;
1955 builder
->samples
= create_info
->pMultisampleState
->rasterizationSamples
;
1957 const struct tu_render_pass
*pass
=
1958 tu_render_pass_from_handle(create_info
->renderPass
);
1959 const struct tu_subpass
*subpass
=
1960 &pass
->subpasses
[create_info
->subpass
];
1962 builder
->use_depth_stencil_attachment
=
1963 subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
;
1965 assert(subpass
->color_count
== 0 ||
1966 !create_info
->pColorBlendState
||
1967 subpass
->color_count
== create_info
->pColorBlendState
->attachmentCount
);
1968 builder
->color_attachment_count
= subpass
->color_count
;
1969 for (uint32_t i
= 0; i
< subpass
->color_count
; i
++) {
1970 const uint32_t a
= subpass
->color_attachments
[i
].attachment
;
1971 if (a
== VK_ATTACHMENT_UNUSED
)
1974 builder
->color_attachment_formats
[i
] = pass
->attachments
[a
].format
;
1975 builder
->use_color_attachments
= true;
1981 tu_graphics_pipeline_create(VkDevice device
,
1982 VkPipelineCache pipelineCache
,
1983 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1984 const VkAllocationCallbacks
*pAllocator
,
1985 VkPipeline
*pPipeline
)
1987 TU_FROM_HANDLE(tu_device
, dev
, device
);
1988 TU_FROM_HANDLE(tu_pipeline_cache
, cache
, pipelineCache
);
1990 struct tu_pipeline_builder builder
;
1991 tu_pipeline_builder_init_graphics(&builder
, dev
, cache
,
1992 pCreateInfo
, pAllocator
);
1994 struct tu_pipeline
*pipeline
= NULL
;
1995 VkResult result
= tu_pipeline_builder_build(&builder
, &pipeline
);
1996 tu_pipeline_builder_finish(&builder
);
1998 if (result
== VK_SUCCESS
)
1999 *pPipeline
= tu_pipeline_to_handle(pipeline
);
2001 *pPipeline
= VK_NULL_HANDLE
;
2007 tu_CreateGraphicsPipelines(VkDevice device
,
2008 VkPipelineCache pipelineCache
,
2010 const VkGraphicsPipelineCreateInfo
*pCreateInfos
,
2011 const VkAllocationCallbacks
*pAllocator
,
2012 VkPipeline
*pPipelines
)
2014 VkResult final_result
= VK_SUCCESS
;
2016 for (uint32_t i
= 0; i
< count
; i
++) {
2017 VkResult result
= tu_graphics_pipeline_create(device
, pipelineCache
,
2018 &pCreateInfos
[i
], pAllocator
,
2021 if (result
!= VK_SUCCESS
)
2022 final_result
= result
;
2025 return final_result
;
2029 tu6_emit_compute_program(struct tu_cs
*cs
,
2030 struct tu_shader
*shader
,
2031 const struct tu_bo
*binary_bo
)
2033 const struct ir3_shader_variant
*v
= &shader
->variants
[0];
2035 tu6_emit_cs_config(cs
, shader
, v
);
2037 /* The compute program is the only one in the pipeline, so 0 offset. */
2038 tu6_emit_shader_object(cs
, MESA_SHADER_COMPUTE
, v
, binary_bo
, 0);
2040 tu6_emit_immediates(cs
, v
, CP_LOAD_STATE6_FRAG
, SB6_CS_SHADER
);
2044 tu_compute_upload_shader(VkDevice device
,
2045 struct tu_pipeline
*pipeline
,
2046 struct tu_shader
*shader
)
2048 TU_FROM_HANDLE(tu_device
, dev
, device
);
2049 struct tu_bo
*bo
= &pipeline
->program
.binary_bo
;
2050 struct ir3_shader_variant
*v
= &shader
->variants
[0];
2052 uint32_t shader_size
= sizeof(uint32_t) * v
->info
.sizedwords
;
2054 tu_bo_init_new(dev
, bo
, shader_size
);
2055 if (result
!= VK_SUCCESS
)
2058 result
= tu_bo_map(dev
, bo
);
2059 if (result
!= VK_SUCCESS
)
2062 memcpy(bo
->map
, shader
->binary
, shader_size
);
2069 tu_compute_pipeline_create(VkDevice device
,
2070 VkPipelineCache _cache
,
2071 const VkComputePipelineCreateInfo
*pCreateInfo
,
2072 const VkAllocationCallbacks
*pAllocator
,
2073 VkPipeline
*pPipeline
)
2075 TU_FROM_HANDLE(tu_device
, dev
, device
);
2076 TU_FROM_HANDLE(tu_pipeline_layout
, layout
, pCreateInfo
->layout
);
2077 const VkPipelineShaderStageCreateInfo
*stage_info
= &pCreateInfo
->stage
;
2080 struct tu_pipeline
*pipeline
;
2082 *pPipeline
= VK_NULL_HANDLE
;
2084 result
= tu_pipeline_create(dev
, pAllocator
, &pipeline
);
2085 if (result
!= VK_SUCCESS
)
2088 pipeline
->layout
= layout
;
2090 struct tu_shader_compile_options options
;
2091 tu_shader_compile_options_init(&options
, NULL
);
2093 struct tu_shader
*shader
=
2094 tu_shader_create(dev
, MESA_SHADER_COMPUTE
, stage_info
, layout
, pAllocator
);
2096 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2100 result
= tu_shader_compile(dev
, shader
, NULL
, &options
, pAllocator
);
2101 if (result
!= VK_SUCCESS
)
2104 struct ir3_shader_variant
*v
= &shader
->variants
[0];
2106 tu_pipeline_set_linkage(&pipeline
->program
.link
[MESA_SHADER_COMPUTE
],
2109 result
= tu_compute_upload_shader(device
, pipeline
, shader
);
2110 if (result
!= VK_SUCCESS
)
2113 for (int i
= 0; i
< 3; i
++)
2114 pipeline
->compute
.local_size
[i
] = v
->shader
->nir
->info
.cs
.local_size
[i
];
2116 struct tu_cs prog_cs
;
2117 tu_cs_begin_sub_stream(&pipeline
->cs
, 512, &prog_cs
);
2118 tu6_emit_compute_program(&prog_cs
, shader
, &pipeline
->program
.binary_bo
);
2119 pipeline
->program
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &prog_cs
);
2121 *pPipeline
= tu_pipeline_to_handle(pipeline
);
2126 tu_shader_destroy(dev
, shader
, pAllocator
);
2128 tu_pipeline_finish(pipeline
, dev
, pAllocator
);
2129 vk_free2(&dev
->alloc
, pAllocator
, pipeline
);
2135 tu_CreateComputePipelines(VkDevice device
,
2136 VkPipelineCache pipelineCache
,
2138 const VkComputePipelineCreateInfo
*pCreateInfos
,
2139 const VkAllocationCallbacks
*pAllocator
,
2140 VkPipeline
*pPipelines
)
2142 VkResult final_result
= VK_SUCCESS
;
2144 for (uint32_t i
= 0; i
< count
; i
++) {
2145 VkResult result
= tu_compute_pipeline_create(device
, pipelineCache
,
2147 pAllocator
, &pPipelines
[i
]);
2148 if (result
!= VK_SUCCESS
)
2149 final_result
= result
;
2152 return final_result
;
2156 tu_DestroyPipeline(VkDevice _device
,
2157 VkPipeline _pipeline
,
2158 const VkAllocationCallbacks
*pAllocator
)
2160 TU_FROM_HANDLE(tu_device
, dev
, _device
);
2161 TU_FROM_HANDLE(tu_pipeline
, pipeline
, _pipeline
);
2166 tu_pipeline_finish(pipeline
, dev
, pAllocator
);
2167 vk_free2(&dev
->alloc
, pAllocator
, pipeline
);