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freedreno: a2xx: ir2 cleanup
[mesa.git] / src / gallium / drivers / freedreno / a2xx / ir2_nir.c
1 /*
2 * Copyright (C) 2018 Jonathan Marek <jonathan@marek.ca>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Jonathan Marek <jonathan@marek.ca>
25 */
26
27 #include "ir2_private.h"
28 #include "nir/tgsi_to_nir.h"
29
30 #include "freedreno_util.h"
31 #include "fd2_program.h"
32
33 static const nir_shader_compiler_options options = {
34 .lower_fpow = true,
35 .lower_flrp32 = true,
36 .lower_fmod32 = true,
37 .lower_fdiv = true,
38 .lower_fceil = true,
39 .fuse_ffma = true,
40 /* .fdot_replicates = true, it is replicated, but it makes things worse */
41 .lower_all_io_to_temps = true,
42 .vertex_id_zero_based = true, /* its not implemented anyway */
43 };
44
45 struct nir_shader *
46 ir2_tgsi_to_nir(const struct tgsi_token *tokens)
47 {
48 return tgsi_to_nir(tokens, &options);
49 }
50
51 const nir_shader_compiler_options *
52 ir2_get_compiler_options(void)
53 {
54 return &options;
55 }
56
57 #define OPT(nir, pass, ...) ({ \
58 bool this_progress = false; \
59 NIR_PASS(this_progress, nir, pass, ##__VA_ARGS__); \
60 this_progress; \
61 })
62 #define OPT_V(nir, pass, ...) NIR_PASS_V(nir, pass, ##__VA_ARGS__)
63
64 static void
65 ir2_optimize_loop(nir_shader *s)
66 {
67 bool progress;
68 do {
69 progress = false;
70
71 OPT_V(s, nir_lower_vars_to_ssa);
72 progress |= OPT(s, nir_opt_copy_prop_vars);
73 progress |= OPT(s, nir_copy_prop);
74 progress |= OPT(s, nir_opt_dce);
75 progress |= OPT(s, nir_opt_cse);
76 /* progress |= OPT(s, nir_opt_gcm, true); */
77 progress |= OPT(s, nir_opt_peephole_select, UINT_MAX, true, true);
78 progress |= OPT(s, nir_opt_intrinsics);
79 progress |= OPT(s, nir_opt_algebraic);
80 progress |= OPT(s, nir_opt_constant_folding);
81 progress |= OPT(s, nir_opt_dead_cf);
82 if (OPT(s, nir_opt_trivial_continues)) {
83 progress |= true;
84 /* If nir_opt_trivial_continues makes progress, then we need to clean
85 * things up if we want any hope of nir_opt_if or nir_opt_loop_unroll
86 * to make progress.
87 */
88 OPT(s, nir_copy_prop);
89 OPT(s, nir_opt_dce);
90 }
91 progress |= OPT(s, nir_opt_loop_unroll, nir_var_all);
92 progress |= OPT(s, nir_opt_if);
93 progress |= OPT(s, nir_opt_remove_phis);
94 progress |= OPT(s, nir_opt_undef);
95
96 }
97 while (progress);
98 }
99
100 /* trig workarounds is the same as ir3.. but we don't want to include ir3 */
101 bool ir3_nir_apply_trig_workarounds(nir_shader * shader);
102
103 int
104 ir2_optimize_nir(nir_shader *s, bool lower)
105 {
106 struct nir_lower_tex_options tex_options = {
107 .lower_txp = ~0u,
108 .lower_rect = 0,
109 };
110
111 if (fd_mesa_debug & FD_DBG_DISASM) {
112 debug_printf("----------------------\n");
113 nir_print_shader(s, stdout);
114 debug_printf("----------------------\n");
115 }
116
117 OPT_V(s, nir_opt_global_to_local);
118 OPT_V(s, nir_lower_regs_to_ssa);
119 OPT_V(s, nir_lower_vars_to_ssa);
120 OPT_V(s, nir_lower_indirect_derefs, nir_var_shader_in | nir_var_shader_out);
121
122 if (lower) {
123 OPT_V(s, ir3_nir_apply_trig_workarounds);
124 OPT_V(s, nir_lower_tex, &tex_options);
125 }
126
127 ir2_optimize_loop(s);
128
129 OPT_V(s, nir_remove_dead_variables, nir_var_function_temp);
130 OPT_V(s, nir_move_load_const);
131
132 /* TODO we dont want to get shaders writing to depth for depth textures */
133 if (s->info.stage == MESA_SHADER_FRAGMENT) {
134 nir_foreach_variable(var, &s->outputs) {
135 if (var->data.location == FRAG_RESULT_DEPTH)
136 return -1;
137 }
138 }
139
140 return 0;
141 }
142
143 static struct ir2_src
144 load_const(struct ir2_context *ctx, float *value_f, unsigned ncomp)
145 {
146 struct fd2_shader_stateobj *so = ctx->so;
147 unsigned imm_ncomp, swiz, idx, i, j;
148 uint32_t *value = (uint32_t*) value_f;
149
150 /* try to merge with existing immediate (TODO: try with neg) */
151 for (idx = 0; idx < so->num_immediates; idx++) {
152 swiz = 0;
153 imm_ncomp = so->immediates[idx].ncomp;
154 for (i = 0; i < ncomp; i++) {
155 for (j = 0; j < imm_ncomp; j++) {
156 if (value[i] == so->immediates[idx].val[j])
157 break;
158 }
159 if (j == imm_ncomp) {
160 if (j == 4)
161 break;
162 so->immediates[idx].val[imm_ncomp++] = value[i];
163 }
164 swiz |= swiz_set(j, i);
165 }
166 /* matched all components */
167 if (i == ncomp)
168 break;
169 }
170
171 /* need to allocate new immediate */
172 if (idx == so->num_immediates) {
173 swiz = 0;
174 imm_ncomp = 0;
175 for (i = 0; i < ncomp; i++) {
176 for (j = 0; j < imm_ncomp; j++) {
177 if (value[i] == ctx->so->immediates[idx].val[j])
178 break;
179 }
180 if (j == imm_ncomp) {
181 so->immediates[idx].val[imm_ncomp++] = value[i];
182 }
183 swiz |= swiz_set(j, i);
184 }
185 so->num_immediates++;
186 }
187 so->immediates[idx].ncomp = imm_ncomp;
188
189 if (ncomp == 1)
190 swiz = swiz_merge(swiz, IR2_SWIZZLE_XXXX);
191
192 return ir2_src(so->first_immediate + idx, swiz, IR2_SRC_CONST);
193 }
194
195 struct ir2_src
196 ir2_zero(struct ir2_context *ctx)
197 {
198 return load_const(ctx, (float[]) {0.0f}, 1);
199 }
200
201 static void
202 update_range(struct ir2_context *ctx, struct ir2_reg *reg)
203 {
204 if (!reg->initialized) {
205 reg->initialized = true;
206 reg->loop_depth = ctx->loop_depth;
207 }
208
209 if (ctx->loop_depth > reg->loop_depth) {
210 reg->block_idx_free = ctx->loop_last_block[reg->loop_depth + 1];
211 } else {
212 reg->loop_depth = ctx->loop_depth;
213 reg->block_idx_free = -1;
214 }
215
216 /* for regs we want to free at the end of the loop in any case
217 * XXX dont do this for ssa
218 */
219 if (reg->loop_depth)
220 reg->block_idx_free = ctx->loop_last_block[reg->loop_depth];
221 }
222
223 static struct ir2_src
224 make_src(struct ir2_context *ctx, nir_src src)
225 {
226 struct ir2_src res = {};
227 struct ir2_reg *reg;
228
229 nir_const_value *const_value = nir_src_as_const_value(src);
230
231 if (const_value) {
232 assert(src.is_ssa);
233 return load_const(ctx, &const_value->f32[0], src.ssa->num_components);
234 }
235
236 if (!src.is_ssa) {
237 res.num = src.reg.reg->index;
238 res.type = IR2_SRC_REG;
239 reg = &ctx->reg[res.num];
240 } else {
241 assert(ctx->ssa_map[src.ssa->index] >= 0);
242 res.num = ctx->ssa_map[src.ssa->index];
243 res.type = IR2_SRC_SSA;
244 reg = &ctx->instr[res.num].ssa;
245 }
246
247 update_range(ctx, reg);
248 return res;
249 }
250
251 static void
252 set_index(struct ir2_context *ctx, nir_dest * dst,
253 struct ir2_instr *instr)
254 {
255 struct ir2_reg *reg = &instr->ssa;
256
257 if (dst->is_ssa) {
258 ctx->ssa_map[dst->ssa.index] = instr->idx;
259 } else {
260 assert(instr->is_ssa);
261 reg = &ctx->reg[dst->reg.reg->index];
262
263 instr->is_ssa = false;
264 instr->reg = reg;
265 }
266 update_range(ctx, reg);
267 }
268
269 static struct ir2_instr *
270 ir2_instr_create(struct ir2_context *ctx, int type)
271 {
272 struct ir2_instr *instr;
273
274 instr = &ctx->instr[ctx->instr_count++];
275 instr->idx = ctx->instr_count - 1;
276 instr->type = type;
277 instr->block_idx = ctx->block_idx;
278 instr->pred = ctx->pred;
279 instr->is_ssa = true;
280 return instr;
281 }
282
283 static struct ir2_instr *
284 instr_create_alu(struct ir2_context *ctx, nir_op opcode, unsigned ncomp)
285 {
286 /* emit_alu will fixup instrs that don't map directly */
287 static const struct ir2_opc {
288 int8_t scalar, vector;
289 } nir_ir2_opc[nir_num_opcodes+1] = {
290 [0 ... nir_num_opcodes - 1] = {-1, -1},
291
292 [nir_op_fmov] = {MAXs, MAXv},
293 [nir_op_fsign] = {-1, CNDGTEv},
294 [nir_op_fnot] = {SETEs, SETEv},
295 [nir_op_for] = {MAXs, MAXv},
296 [nir_op_fand] = {MINs, MINv},
297 [nir_op_fxor] = {-1, SETNEv},
298 [nir_op_fadd] = {ADDs, ADDv},
299 [nir_op_fsub] = {ADDs, ADDv},
300 [nir_op_fmul] = {MULs, MULv},
301 [nir_op_ffma] = {-1, MULADDv},
302 [nir_op_fmax] = {MAXs, MAXv},
303 [nir_op_fmin] = {MINs, MINv},
304 [nir_op_ffloor] = {FLOORs, FLOORv},
305 [nir_op_ffract] = {FRACs, FRACv},
306 [nir_op_ftrunc] = {TRUNCs, TRUNCv},
307 [nir_op_fdot2] = {-1, DOT2ADDv},
308 [nir_op_fdot3] = {-1, DOT3v},
309 [nir_op_fdot4] = {-1, DOT4v},
310 [nir_op_sge] = {-1, SETGTEv},
311 [nir_op_slt] = {-1, SETGTv},
312 [nir_op_sne] = {-1, SETNEv},
313 [nir_op_seq] = {-1, SETEv},
314 [nir_op_fcsel] = {-1, CNDEv},
315 [nir_op_frsq] = {RECIPSQ_IEEE, -1},
316 [nir_op_frcp] = {RECIP_IEEE, -1},
317 [nir_op_flog2] = {LOG_IEEE, -1},
318 [nir_op_fexp2] = {EXP_IEEE, -1},
319 [nir_op_fsqrt] = {SQRT_IEEE, -1},
320 [nir_op_fcos] = {COS, -1},
321 [nir_op_fsin] = {SIN, -1},
322 /* no fsat, fneg, fabs since source mods deal with those */
323
324 /* some nir passes still generate nir_op_imov */
325 [nir_op_imov] = {MAXs, MAXv},
326
327 /* so we can use this function with non-nir op */
328 #define ir2_op_cube nir_num_opcodes
329 [ir2_op_cube] = {-1, CUBEv},
330 };
331
332 struct ir2_opc op = nir_ir2_opc[opcode];
333 assert(op.vector >= 0 || op.scalar >= 0);
334
335 struct ir2_instr *instr = ir2_instr_create(ctx, IR2_ALU);
336 instr->alu.vector_opc = op.vector;
337 instr->alu.scalar_opc = op.scalar;
338 instr->alu.export = -1;
339 instr->alu.write_mask = (1 << ncomp) - 1;
340 instr->src_count = opcode == ir2_op_cube ? 2 :
341 nir_op_infos[opcode].num_inputs;
342 instr->ssa.ncomp = ncomp;
343 return instr;
344 }
345
346 static struct ir2_instr *
347 instr_create_alu_reg(struct ir2_context *ctx, nir_op opcode,
348 uint8_t write_mask, struct ir2_instr *share_reg)
349 {
350 struct ir2_instr *instr;
351 struct ir2_reg *reg;
352
353 reg = share_reg ? share_reg->reg : &ctx->reg[ctx->reg_count++];
354 reg->ncomp = MAX2(reg->ncomp, util_logbase2(write_mask) + 1);
355
356 instr = instr_create_alu(ctx, opcode, util_bitcount(write_mask));
357 instr->alu.write_mask = write_mask;
358 instr->reg = reg;
359 instr->is_ssa = false;
360 return instr;
361 }
362
363
364 static struct ir2_instr *
365 instr_create_alu_dest(struct ir2_context *ctx, nir_op opcode, nir_dest *dst)
366 {
367 struct ir2_instr *instr;
368 instr = instr_create_alu(ctx, opcode, nir_dest_num_components(*dst));
369 set_index(ctx, dst, instr);
370 return instr;
371 }
372
373 static struct ir2_instr *
374 ir2_instr_create_fetch(struct ir2_context *ctx, nir_dest *dst,
375 instr_fetch_opc_t opc)
376 {
377 struct ir2_instr *instr = ir2_instr_create(ctx, IR2_FETCH);
378 instr->fetch.opc = opc;
379 instr->src_count = 1;
380 instr->ssa.ncomp = nir_dest_num_components(*dst);
381 set_index(ctx, dst, instr);
382 return instr;
383 }
384
385 static struct ir2_src
386 make_src_noconst(struct ir2_context *ctx, nir_src src)
387 {
388 struct ir2_instr *instr;
389
390 if (nir_src_as_const_value(src)) {
391 assert(src.is_ssa);
392 instr = instr_create_alu(ctx, nir_op_fmov, src.ssa->num_components);
393 instr->src[0] = make_src(ctx, src);
394 return ir2_src(instr->idx, 0, IR2_SRC_SSA);
395 }
396
397 return make_src(ctx, src);
398 }
399
400 static void
401 emit_alu(struct ir2_context *ctx, nir_alu_instr * alu)
402 {
403 const nir_op_info *info = &nir_op_infos[alu->op];
404 nir_dest *dst = &alu->dest.dest;
405 struct ir2_instr *instr;
406 struct ir2_src tmp;
407 unsigned ncomp;
408
409 /* get the number of dst components */
410 if (dst->is_ssa) {
411 ncomp = dst->ssa.num_components;
412 } else {
413 ncomp = 0;
414 for (int i = 0; i < 4; i++)
415 ncomp += !!(alu->dest.write_mask & 1 << i);
416 }
417
418 instr = instr_create_alu(ctx, alu->op, ncomp);
419 set_index(ctx, dst, instr);
420 instr->alu.saturate = alu->dest.saturate;
421 instr->alu.write_mask = alu->dest.write_mask;
422
423 for (int i = 0; i < info->num_inputs; i++) {
424 nir_alu_src *src = &alu->src[i];
425
426 /* compress swizzle with writemask when applicable */
427 unsigned swiz = 0, j = 0;
428 for (int i = 0; i < 4; i++) {
429 if (!(alu->dest.write_mask & 1 << i) && !info->output_size)
430 continue;
431 swiz |= swiz_set(src->swizzle[i], j++);
432 }
433
434 instr->src[i] = make_src(ctx, src->src);
435 instr->src[i].swizzle = swiz_merge(instr->src[i].swizzle, swiz);
436 instr->src[i].negate = src->negate;
437 instr->src[i].abs = src->abs;
438 }
439
440 /* workarounds for NIR ops that don't map directly to a2xx ops */
441 switch (alu->op) {
442 case nir_op_slt:
443 tmp = instr->src[0];
444 instr->src[0] = instr->src[1];
445 instr->src[1] = tmp;
446 break;
447 case nir_op_fcsel:
448 tmp = instr->src[1];
449 instr->src[1] = instr->src[2];
450 instr->src[2] = tmp;
451 break;
452 case nir_op_fsub:
453 instr->src[1].negate = !instr->src[1].negate;
454 break;
455 case nir_op_fdot2:
456 instr->src_count = 3;
457 instr->src[2] = ir2_zero(ctx);
458 break;
459 case nir_op_fsign: {
460 /* we need an extra instruction to deal with the zero case */
461 struct ir2_instr *tmp;
462
463 /* tmp = x == 0 ? 0 : 1 */
464 tmp = instr_create_alu(ctx, nir_op_fcsel, ncomp);
465 tmp->src[0] = instr->src[0];
466 tmp->src[1] = ir2_zero(ctx);
467 tmp->src[2] = load_const(ctx, (float[]) {1.0f}, 1);
468
469 /* result = x >= 0 ? tmp : -tmp */
470 instr->src[1] = ir2_src(tmp->idx, 0, IR2_SRC_SSA);
471 instr->src[2] = instr->src[1];
472 instr->src[2].negate = true;
473 instr->src_count = 3;
474 } break;
475 default:
476 break;
477 }
478 }
479
480 static void
481 load_input(struct ir2_context *ctx, nir_dest *dst, unsigned idx)
482 {
483 struct ir2_instr *instr;
484 int slot = -1;
485
486 if (ctx->so->type == MESA_SHADER_VERTEX) {
487 instr = ir2_instr_create_fetch(ctx, dst, 0);
488 instr->src[0] = ir2_src(0, 0, IR2_SRC_INPUT);
489 instr->fetch.vtx.const_idx = 20 + (idx / 3);
490 instr->fetch.vtx.const_idx_sel = idx % 3;
491 return;
492 }
493
494 /* get slot from idx */
495 nir_foreach_variable(var, &ctx->nir->inputs) {
496 if (var->data.driver_location == idx) {
497 slot = var->data.location;
498 break;
499 }
500 }
501 assert(slot >= 0);
502
503 switch (slot) {
504 case VARYING_SLOT_PNTC:
505 /* need to extract with abs and invert y */
506 instr = instr_create_alu_dest(ctx, nir_op_ffma, dst);
507 instr->src[0] = ir2_src(ctx->f->inputs_count, IR2_SWIZZLE_ZW, IR2_SRC_INPUT);
508 instr->src[0].abs = true;
509 instr->src[1] = load_const(ctx, (float[]) {1.0f, -1.0f}, 2);
510 instr->src[2] = load_const(ctx, (float[]) {0.0f, 1.0f}, 2);
511 break;
512 case VARYING_SLOT_POS:
513 /* need to extract xy with abs and add tile offset on a20x
514 * zw from fragcoord input (w inverted in fragment shader)
515 * TODO: only components that are required by fragment shader
516 */
517 instr = instr_create_alu_reg(ctx,
518 ctx->so->is_a20x ? nir_op_fadd : nir_op_fmov, 3, NULL);
519 instr->src[0] = ir2_src(ctx->f->inputs_count, 0, IR2_SRC_INPUT);
520 instr->src[0].abs = true;
521 /* on a20x, C64 contains the tile offset */
522 instr->src[1] = ir2_src(64, 0, IR2_SRC_CONST);
523
524 instr = instr_create_alu_reg(ctx, nir_op_fmov, 4, instr);
525 instr->src[0] = ir2_src(ctx->f->fragcoord, 0, IR2_SRC_INPUT);
526
527 instr = instr_create_alu_reg(ctx, nir_op_frcp, 8, instr);
528 instr->src[0] = ir2_src(ctx->f->fragcoord, IR2_SWIZZLE_Y, IR2_SRC_INPUT);
529
530 unsigned reg_idx = instr->reg - ctx->reg; /* XXX */
531 instr = instr_create_alu_dest(ctx, nir_op_fmov, dst);
532 instr->src[0] = ir2_src(reg_idx, 0, IR2_SRC_REG);
533 break;
534 default:
535 instr = instr_create_alu_dest(ctx, nir_op_fmov, dst);
536 instr->src[0] = ir2_src(idx, 0, IR2_SRC_INPUT);
537 break;
538 }
539 }
540
541 static unsigned
542 output_slot(struct ir2_context *ctx, nir_intrinsic_instr *intr)
543 {
544 int slot = -1;
545 unsigned idx = nir_intrinsic_base(intr);
546 nir_foreach_variable(var, &ctx->nir->outputs) {
547 if (var->data.driver_location == idx) {
548 slot = var->data.location;
549 break;
550 }
551 }
552 assert(slot != -1);
553 return slot;
554 }
555
556 static void
557 store_output(struct ir2_context *ctx, nir_src src, unsigned slot, unsigned ncomp)
558 {
559 struct ir2_instr *instr;
560 unsigned idx = 0;
561
562 if (ctx->so->type == MESA_SHADER_VERTEX) {
563 switch (slot) {
564 case VARYING_SLOT_POS:
565 ctx->position = make_src(ctx, src);
566 idx = 62;
567 break;
568 case VARYING_SLOT_PSIZ:
569 ctx->so->writes_psize = true;
570 idx = 63;
571 break;
572 default:
573 /* find matching slot from fragment shader input */
574 for (idx = 0; idx < ctx->f->inputs_count; idx++)
575 if (ctx->f->inputs[idx].slot == slot)
576 break;
577 if (idx == ctx->f->inputs_count)
578 return;
579 }
580 } else if (slot != FRAG_RESULT_COLOR && slot != FRAG_RESULT_DATA0) {
581 /* only color output is implemented */
582 return;
583 }
584
585 instr = instr_create_alu(ctx, nir_op_fmov, ncomp);
586 instr->src[0] = make_src(ctx, src);
587 instr->alu.export = idx;
588 }
589
590 static void
591 emit_intrinsic(struct ir2_context *ctx, nir_intrinsic_instr *intr)
592 {
593 struct ir2_instr *instr;
594 nir_const_value *const_offset;
595 nir_deref_instr *deref;
596 unsigned idx;
597
598 switch (intr->intrinsic) {
599 case nir_intrinsic_load_input:
600 load_input(ctx, &intr->dest, nir_intrinsic_base(intr));
601 break;
602 case nir_intrinsic_store_output:
603 store_output(ctx, intr->src[0], output_slot(ctx, intr), intr->num_components);
604 break;
605 case nir_intrinsic_load_deref:
606 deref = nir_src_as_deref(intr->src[0]);
607 assert(deref->deref_type == nir_deref_type_var);
608 load_input(ctx, &intr->dest, deref->var->data.driver_location);
609 break;
610 case nir_intrinsic_store_deref:
611 deref = nir_src_as_deref(intr->src[0]);
612 assert(deref->deref_type == nir_deref_type_var);
613 store_output(ctx, intr->src[1], deref->var->data.location, intr->num_components);
614 break;
615 case nir_intrinsic_load_uniform:
616 const_offset = nir_src_as_const_value(intr->src[0]);
617 assert(const_offset); /* TODO can be false in ES2? */
618 idx = nir_intrinsic_base(intr);
619 idx += (uint32_t) nir_src_as_const_value(intr->src[0])->f32[0];
620 instr = instr_create_alu_dest(ctx, nir_op_fmov, &intr->dest);
621 instr->src[0] = ir2_src(idx, 0, IR2_SRC_CONST);
622 break;
623 case nir_intrinsic_discard:
624 case nir_intrinsic_discard_if:
625 instr = ir2_instr_create(ctx, IR2_ALU);
626 instr->alu.vector_opc = VECTOR_NONE;
627 if (intr->intrinsic == nir_intrinsic_discard_if) {
628 instr->alu.scalar_opc = KILLNEs;
629 instr->src[0] = make_src(ctx, intr->src[0]);
630 } else {
631 instr->alu.scalar_opc = KILLEs;
632 instr->src[0] = ir2_zero(ctx);
633 }
634 instr->alu.export = -1;
635 instr->src_count = 1;
636 break;
637 case nir_intrinsic_load_front_face:
638 /* gl_FrontFacing is in the sign of param.x
639 * rcp required because otherwise we can't differentiate -0.0 and +0.0
640 */
641 ctx->so->need_param = true;
642
643 struct ir2_instr *tmp = instr_create_alu(ctx, nir_op_frcp, 1);
644 tmp->src[0] = ir2_src(ctx->f->inputs_count, 0, IR2_SRC_INPUT);
645
646 instr = instr_create_alu_dest(ctx, nir_op_sge, &intr->dest);
647 instr->src[0] = ir2_src(tmp->idx, 0, IR2_SRC_SSA);
648 instr->src[1] = ir2_zero(ctx);
649 break;
650 default:
651 compile_error(ctx, "unimplemented intr %d\n", intr->intrinsic);
652 break;
653 }
654 }
655
656 static void
657 emit_tex(struct ir2_context *ctx, nir_tex_instr * tex)
658 {
659 bool is_rect = false, is_cube = false;
660 struct ir2_instr *instr;
661 nir_src *coord, *lod_bias;
662
663 coord = lod_bias = NULL;
664
665 for (unsigned i = 0; i < tex->num_srcs; i++) {
666 switch (tex->src[i].src_type) {
667 case nir_tex_src_coord:
668 coord = &tex->src[i].src;
669 break;
670 case nir_tex_src_bias:
671 case nir_tex_src_lod:
672 assert(!lod_bias);
673 lod_bias = &tex->src[i].src;
674 break;
675 default:
676 compile_error(ctx, "Unhandled NIR tex src type: %d\n",
677 tex->src[i].src_type);
678 return;
679 }
680 }
681
682 switch (tex->op) {
683 case nir_texop_tex:
684 case nir_texop_txb:
685 case nir_texop_txl:
686 break;
687 default:
688 compile_error(ctx, "unimplemented texop %d\n", tex->op);
689 return;
690 }
691
692 switch (tex->sampler_dim) {
693 case GLSL_SAMPLER_DIM_2D:
694 break;
695 case GLSL_SAMPLER_DIM_RECT:
696 is_rect = true;
697 break;
698 case GLSL_SAMPLER_DIM_CUBE:
699 is_cube = true;
700 break;
701 default:
702 compile_error(ctx, "unimplemented sampler %d\n", tex->sampler_dim);
703 return;
704 }
705
706 struct ir2_src src_coord = make_src_noconst(ctx, *coord);
707
708 /* for cube maps
709 * tmp = cube(coord)
710 * tmp.xy = tmp.xy / |tmp.z| + 1.5
711 * coord = tmp.xyw
712 */
713 if (is_cube) {
714 struct ir2_instr *rcp, *coord_xy;
715 unsigned reg_idx;
716
717 instr = instr_create_alu_reg(ctx, ir2_op_cube, 15, NULL);
718 instr->src[0] = src_coord;
719 instr->src[0].swizzle = IR2_SWIZZLE_ZZXY;
720 instr->src[1] = src_coord;
721 instr->src[1].swizzle = IR2_SWIZZLE_YXZZ;
722
723 reg_idx = instr->reg - ctx->reg; /* hacky */
724
725 rcp = instr_create_alu(ctx, nir_op_frcp, 1);
726 rcp->src[0] = ir2_src(reg_idx, IR2_SWIZZLE_Z, IR2_SRC_REG);
727 rcp->src[0].abs = true;
728
729 coord_xy = instr_create_alu_reg(ctx, nir_op_ffma, 3, instr);
730 coord_xy->src[0] = ir2_src(reg_idx, 0, IR2_SRC_REG);
731 coord_xy->src[1] = ir2_src(rcp->idx, IR2_SWIZZLE_XXXX, IR2_SRC_SSA);
732 coord_xy->src[2] = load_const(ctx, (float[]) {1.5f}, 1);
733
734 src_coord = ir2_src(reg_idx, 0, IR2_SRC_REG);
735 /* TODO: lod/bias transformed by src_coord.z ? */
736 }
737
738 instr = ir2_instr_create_fetch(ctx, &tex->dest, TEX_FETCH);
739 instr->src[0] = src_coord;
740 instr->src[0].swizzle = is_cube ? IR2_SWIZZLE_XYW : 0;
741 instr->fetch.tex.is_cube = is_cube;
742 instr->fetch.tex.is_rect = is_rect;
743 instr->fetch.tex.samp_id = tex->sampler_index;
744
745 /* for lod/bias, we insert an extra src for the backend to deal with */
746 if (lod_bias) {
747 instr->src[1] = make_src_noconst(ctx, *lod_bias);
748 /* backend will use 2-3 components so apply swizzle */
749 swiz_merge_p(&instr->src[1].swizzle, IR2_SWIZZLE_XXXX);
750 instr->src_count = 2;
751 }
752 }
753
754 static void
755 setup_input(struct ir2_context *ctx, nir_variable * in)
756 {
757 struct fd2_shader_stateobj *so = ctx->so;
758 unsigned array_len = MAX2(glsl_get_length(in->type), 1);
759 unsigned n = in->data.driver_location;
760 unsigned slot = in->data.location;
761
762 assert(array_len == 1);
763
764 /* handle later */
765 if (ctx->so->type == MESA_SHADER_VERTEX)
766 return;
767
768 if (ctx->so->type != MESA_SHADER_FRAGMENT)
769 compile_error(ctx, "unknown shader type: %d\n", ctx->so->type);
770
771 if (slot == VARYING_SLOT_PNTC) {
772 so->need_param = true;
773 return;
774 }
775
776 n = ctx->f->inputs_count++;
777
778 /* half of fragcoord from param reg, half from a varying */
779 if (slot == VARYING_SLOT_POS) {
780 ctx->f->fragcoord = n;
781 so->need_param = true;
782 }
783
784 ctx->f->inputs[n].slot = slot;
785 ctx->f->inputs[n].ncomp = glsl_get_components(in->type);
786
787 /* in->data.interpolation?
788 * opengl ES 2.0 can't do flat mode, but we still get it from GALLIUM_HUD
789 */
790 }
791
792 static void
793 emit_undef(struct ir2_context *ctx, nir_ssa_undef_instr * undef)
794 {
795 /* TODO we don't want to emit anything for undefs */
796
797 struct ir2_instr *instr;
798
799 instr = instr_create_alu_dest(ctx, nir_op_fmov,
800 &(nir_dest) {.ssa = undef->def,.is_ssa = true});
801 instr->src[0] = ir2_src(0, 0, IR2_SRC_CONST);
802 }
803
804 static void
805 emit_instr(struct ir2_context *ctx, nir_instr * instr)
806 {
807 switch (instr->type) {
808 case nir_instr_type_alu:
809 emit_alu(ctx, nir_instr_as_alu(instr));
810 break;
811 case nir_instr_type_deref:
812 /* ignored, handled as part of the intrinsic they are src to */
813 break;
814 case nir_instr_type_intrinsic:
815 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
816 break;
817 case nir_instr_type_load_const:
818 /* dealt with when using nir_src */
819 break;
820 case nir_instr_type_tex:
821 emit_tex(ctx, nir_instr_as_tex(instr));
822 break;
823 case nir_instr_type_jump:
824 ctx->block_has_jump[ctx->block_idx] = true;
825 break;
826 case nir_instr_type_ssa_undef:
827 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
828 break;
829 default:
830 break;
831 }
832 }
833
834 /* fragcoord.zw and a20x hw binning outputs */
835 static void
836 extra_position_exports(struct ir2_context *ctx, bool binning)
837 {
838 struct ir2_instr *instr, *rcp, *sc, *wincoord, *off;
839
840 if (ctx->f->fragcoord < 0 && !binning)
841 return;
842
843 instr = instr_create_alu(ctx, nir_op_fmax, 1);
844 instr->src[0] = ctx->position;
845 instr->src[0].swizzle = IR2_SWIZZLE_W;
846 instr->src[1] = ir2_zero(ctx);
847
848 rcp = instr_create_alu(ctx, nir_op_frcp, 1);
849 rcp->src[0] = ir2_src(instr->idx, 0, IR2_SRC_SSA);
850
851 sc = instr_create_alu(ctx, nir_op_fmul, 4);
852 sc->src[0] = ctx->position;
853 sc->src[1] = ir2_src(rcp->idx, IR2_SWIZZLE_XXXX, IR2_SRC_SSA);
854
855 wincoord = instr_create_alu(ctx, nir_op_ffma, 4);
856 wincoord->src[0] = ir2_src(66, 0, IR2_SRC_CONST);
857 wincoord->src[1] = ir2_src(sc->idx, 0, IR2_SRC_SSA);
858 wincoord->src[2] = ir2_src(65, 0, IR2_SRC_CONST);
859
860 /* fragcoord z/w */
861 if (ctx->f->fragcoord >= 0 && !binning) {
862 instr = instr_create_alu(ctx, nir_op_fmov, 1);
863 instr->src[0] = ir2_src(wincoord->idx, IR2_SWIZZLE_Z, IR2_SRC_SSA);
864 instr->alu.export = ctx->f->fragcoord;
865
866 instr = instr_create_alu(ctx, nir_op_fmov, 1);
867 instr->src[0] = ctx->position;
868 instr->src[0].swizzle = IR2_SWIZZLE_W;
869 instr->alu.export = ctx->f->fragcoord;
870 instr->alu.write_mask = 2;
871 }
872
873 if (!binning)
874 return;
875
876 off = instr_create_alu(ctx, nir_op_fadd, 1);
877 off->src[0] = ir2_src(64, 0, IR2_SRC_CONST);
878 off->src[1] = ir2_src(2, 0, IR2_SRC_INPUT);
879
880 /* 8 max set in freedreno_screen.. unneeded instrs patched out */
881 for (int i = 0; i < 8; i++) {
882 instr = instr_create_alu(ctx, nir_op_ffma, 4);
883 instr->src[0] = ir2_src(1, IR2_SWIZZLE_WYWW, IR2_SRC_CONST);
884 instr->src[1] = ir2_src(off->idx, IR2_SWIZZLE_XXXX, IR2_SRC_SSA);
885 instr->src[2] = ir2_src(3 + i, 0, IR2_SRC_CONST);
886 instr->alu.export = 32;
887
888 instr = instr_create_alu(ctx, nir_op_ffma, 4);
889 instr->src[0] = ir2_src(68 + i * 2, 0, IR2_SRC_CONST);
890 instr->src[1] = ir2_src(wincoord->idx, 0, IR2_SRC_SSA);
891 instr->src[2] = ir2_src(67 + i * 2, 0, IR2_SRC_CONST);
892 instr->alu.export = 33;
893 }
894 }
895
896 static bool emit_cf_list(struct ir2_context *ctx, struct exec_list *list);
897
898 static bool
899 emit_block(struct ir2_context *ctx, nir_block * block)
900 {
901 struct ir2_instr *instr;
902 nir_block *succs = block->successors[0];
903
904 ctx->block_idx = block->index;
905
906 nir_foreach_instr(instr, block)
907 emit_instr(ctx, instr);
908
909 if (!succs || !succs->index)
910 return false;
911
912 /* we want to be smart and always jump and have the backend cleanup
913 * but we are not, so there are two cases where jump is needed:
914 * loops (succs index lower)
915 * jumps (jump instruction seen in block)
916 */
917 if (succs->index > block->index && !ctx->block_has_jump[block->index])
918 return false;
919
920 assert(block->successors[1] == NULL);
921
922 instr = ir2_instr_create(ctx, IR2_CF);
923 instr->cf.block_idx = succs->index;
924 /* XXX can't jump to a block with different predicate */
925 return true;
926 }
927
928 static void
929 emit_if(struct ir2_context *ctx, nir_if * nif)
930 {
931 unsigned pred = ctx->pred, pred_idx = ctx->pred_idx;
932 struct ir2_instr *instr;
933
934 /* XXX: blob seems to always use same register for condition */
935
936 instr = ir2_instr_create(ctx, IR2_ALU);
937 instr->src[0] = make_src(ctx, nif->condition);
938 instr->src_count = 1;
939 instr->ssa.ncomp = 1;
940 instr->alu.vector_opc = VECTOR_NONE;
941 instr->alu.scalar_opc = SCALAR_NONE;
942 instr->alu.export = -1;
943 instr->alu.write_mask = 1;
944 instr->pred = 0;
945
946 /* if nested, use PRED_SETNE_PUSHv */
947 if (pred) {
948 instr->alu.vector_opc = PRED_SETNE_PUSHv;
949 instr->src[1] = instr->src[0];
950 instr->src[0] = ir2_src(pred_idx, 0, IR2_SRC_SSA);
951 instr->src[0].swizzle = IR2_SWIZZLE_XXXX;
952 instr->src[1].swizzle = IR2_SWIZZLE_XXXX;
953 instr->src_count = 2;
954 } else {
955 instr->alu.scalar_opc = PRED_SETNEs;
956 }
957
958 ctx->pred_idx = instr->idx;
959 ctx->pred = 3;
960
961 emit_cf_list(ctx, &nif->then_list);
962
963 /* TODO: if these is no else branch we don't need this
964 * and if the else branch is simple, can just flip ctx->pred instead
965 */
966 instr = ir2_instr_create(ctx, IR2_ALU);
967 instr->src[0] = ir2_src(ctx->pred_idx, 0, IR2_SRC_SSA);
968 instr->src_count = 1;
969 instr->ssa.ncomp = 1;
970 instr->alu.vector_opc = VECTOR_NONE;
971 instr->alu.scalar_opc = PRED_SET_INVs;
972 instr->alu.export = -1;
973 instr->alu.write_mask = 1;
974 instr->pred = 0;
975 ctx->pred_idx = instr->idx;
976
977 emit_cf_list(ctx, &nif->else_list);
978
979 /* restore predicate for nested predicates */
980 if (pred) {
981 instr = ir2_instr_create(ctx, IR2_ALU);
982 instr->src[0] = ir2_src(ctx->pred_idx, 0, IR2_SRC_SSA);
983 instr->src_count = 1;
984 instr->ssa.ncomp = 1;
985 instr->alu.vector_opc = VECTOR_NONE;
986 instr->alu.scalar_opc = PRED_SET_POPs;
987 instr->alu.export = -1;
988 instr->alu.write_mask = 1;
989 instr->pred = 0;
990 ctx->pred_idx = instr->idx;
991 }
992
993 /* restore ctx->pred */
994 ctx->pred = pred;
995 }
996
997 /* get the highest block idx in the loop, so we know when
998 * we can free registers that are allocated outside the loop
999 */
1000 static unsigned
1001 loop_last_block(struct exec_list *list)
1002 {
1003 nir_cf_node *node =
1004 exec_node_data(nir_cf_node, exec_list_get_tail(list), node);
1005 switch (node->type) {
1006 case nir_cf_node_block:
1007 return nir_cf_node_as_block(node)->index;
1008 case nir_cf_node_if:
1009 assert(0); /* XXX could this ever happen? */
1010 return 0;
1011 case nir_cf_node_loop:
1012 return loop_last_block(&nir_cf_node_as_loop(node)->body);
1013 default:
1014 compile_error(ctx, "Not supported\n");
1015 return 0;
1016 }
1017 }
1018
1019 static void
1020 emit_loop(struct ir2_context *ctx, nir_loop *nloop)
1021 {
1022 ctx->loop_last_block[++ctx->loop_depth] = loop_last_block(&nloop->body);
1023 emit_cf_list(ctx, &nloop->body);
1024 ctx->loop_depth--;
1025 }
1026
1027 static bool
1028 emit_cf_list(struct ir2_context *ctx, struct exec_list *list)
1029 {
1030 bool ret = false;
1031 foreach_list_typed(nir_cf_node, node, node, list) {
1032 ret = false;
1033 switch (node->type) {
1034 case nir_cf_node_block:
1035 ret = emit_block(ctx, nir_cf_node_as_block(node));
1036 break;
1037 case nir_cf_node_if:
1038 emit_if(ctx, nir_cf_node_as_if(node));
1039 break;
1040 case nir_cf_node_loop:
1041 emit_loop(ctx, nir_cf_node_as_loop(node));
1042 break;
1043 case nir_cf_node_function:
1044 compile_error(ctx, "Not supported\n");
1045 break;
1046 }
1047 }
1048 return ret;
1049 }
1050
1051 static void cleanup_binning(struct ir2_context *ctx)
1052 {
1053 assert(ctx->so->type == MESA_SHADER_VERTEX);
1054
1055 /* kill non-position outputs for binning variant */
1056 nir_foreach_block(block, nir_shader_get_entrypoint(ctx->nir)) {
1057 nir_foreach_instr_safe(instr, block) {
1058 if (instr->type != nir_instr_type_intrinsic)
1059 continue;
1060
1061 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
1062 unsigned slot;
1063 switch (intr->intrinsic) {
1064 case nir_intrinsic_store_deref: {
1065 nir_deref_instr *deref = nir_src_as_deref(intr->src[0]);
1066 assert(deref->deref_type == nir_deref_type_var);
1067 slot = deref->var->data.location;
1068 } break;
1069 case nir_intrinsic_store_output:
1070 slot = output_slot(ctx, intr);
1071 break;
1072 default:
1073 continue;
1074 }
1075
1076 if (slot != VARYING_SLOT_POS)
1077 nir_instr_remove(instr);
1078 }
1079 }
1080
1081 ir2_optimize_nir(ctx->nir, false);
1082 }
1083
1084 void
1085 ir2_nir_compile(struct ir2_context *ctx, bool binning)
1086 {
1087 struct fd2_shader_stateobj *so = ctx->so;
1088
1089 memset(ctx->ssa_map, 0xff, sizeof(ctx->ssa_map));
1090
1091 ctx->nir = nir_shader_clone(NULL, so->nir);
1092
1093 if (binning)
1094 cleanup_binning(ctx);
1095
1096 /* postprocess */
1097 OPT_V(ctx->nir, nir_opt_algebraic_late);
1098
1099 OPT_V(ctx->nir, nir_lower_to_source_mods, nir_lower_all_source_mods);
1100 OPT_V(ctx->nir, nir_copy_prop);
1101 OPT_V(ctx->nir, nir_opt_dce);
1102 OPT_V(ctx->nir, nir_opt_move_comparisons);
1103
1104 OPT_V(ctx->nir, nir_lower_bool_to_float);
1105
1106 /* lower to scalar instructions that can only be scalar on a2xx */
1107 OPT_V(ctx->nir, ir2_nir_lower_scalar);
1108
1109 OPT_V(ctx->nir, nir_lower_locals_to_regs);
1110
1111 OPT_V(ctx->nir, nir_convert_from_ssa, true);
1112
1113 OPT_V(ctx->nir, nir_move_vec_src_uses_to_dest);
1114 OPT_V(ctx->nir, nir_lower_vec_to_movs);
1115
1116 OPT_V(ctx->nir, nir_opt_dce);
1117
1118 nir_sweep(ctx->nir);
1119
1120 if (fd_mesa_debug & FD_DBG_DISASM) {
1121 debug_printf("----------------------\n");
1122 nir_print_shader(ctx->nir, stdout);
1123 debug_printf("----------------------\n");
1124 }
1125
1126 /* fd2_shader_stateobj init */
1127 if (so->type == MESA_SHADER_FRAGMENT) {
1128 ctx->f->fragcoord = -1;
1129 ctx->f->inputs_count = 0;
1130 memset(ctx->f->inputs, 0, sizeof(ctx->f->inputs));
1131 }
1132
1133 /* Setup inputs: */
1134 nir_foreach_variable(in, &ctx->nir->inputs)
1135 setup_input(ctx, in);
1136
1137 if (so->type == MESA_SHADER_FRAGMENT) {
1138 unsigned idx;
1139 for (idx = 0; idx < ctx->f->inputs_count; idx++) {
1140 ctx->input[idx].ncomp = ctx->f->inputs[idx].ncomp;
1141 update_range(ctx, &ctx->input[idx]);
1142 }
1143 /* assume we have param input and kill it later if not */
1144 ctx->input[idx].ncomp = 4;
1145 update_range(ctx, &ctx->input[idx]);
1146 } else {
1147 ctx->input[0].ncomp = 1;
1148 ctx->input[2].ncomp = 1;
1149 update_range(ctx, &ctx->input[0]);
1150 update_range(ctx, &ctx->input[2]);
1151 }
1152
1153 /* And emit the body: */
1154 nir_function_impl *fxn = nir_shader_get_entrypoint(ctx->nir);
1155
1156 nir_foreach_register(reg, &fxn->registers) {
1157 ctx->reg[reg->index].ncomp = reg->num_components;
1158 ctx->reg_count = MAX2(ctx->reg_count, reg->index + 1);
1159 }
1160
1161 nir_metadata_require(fxn, nir_metadata_block_index);
1162 emit_cf_list(ctx, &fxn->body);
1163 /* TODO emit_block(ctx, fxn->end_block); */
1164
1165 if (so->type == MESA_SHADER_VERTEX)
1166 extra_position_exports(ctx, binning);
1167
1168 ralloc_free(ctx->nir);
1169
1170 /* kill unused param input */
1171 if (so->type == MESA_SHADER_FRAGMENT && !so->need_param)
1172 ctx->input[ctx->f->inputs_count].initialized = false;
1173 }