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freedreno/a4xx: use generated headers for draw initiator
[mesa.git] / src / gallium / drivers / freedreno / a4xx / fd4_program.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_inlines.h"
33 #include "util/u_format.h"
34
35 #include "freedreno_program.h"
36
37 #include "fd4_program.h"
38 #include "fd4_emit.h"
39 #include "fd4_texture.h"
40 #include "fd4_format.h"
41
42 static void
43 delete_shader_stateobj(struct fd4_shader_stateobj *so)
44 {
45 ir3_shader_destroy(so->shader);
46 free(so);
47 }
48
49 static struct fd4_shader_stateobj *
50 create_shader_stateobj(struct pipe_context *pctx, const struct pipe_shader_state *cso,
51 enum shader_t type)
52 {
53 struct fd4_shader_stateobj *so = CALLOC_STRUCT(fd4_shader_stateobj);
54 struct ir3_compiler *compiler = fd_context(pctx)->screen->compiler;
55 so->shader = ir3_shader_create(compiler, cso, type);
56 return so;
57 }
58
59 static void *
60 fd4_fp_state_create(struct pipe_context *pctx,
61 const struct pipe_shader_state *cso)
62 {
63 return create_shader_stateobj(pctx, cso, SHADER_FRAGMENT);
64 }
65
66 static void
67 fd4_fp_state_delete(struct pipe_context *pctx, void *hwcso)
68 {
69 struct fd4_shader_stateobj *so = hwcso;
70 delete_shader_stateobj(so);
71 }
72
73 static void *
74 fd4_vp_state_create(struct pipe_context *pctx,
75 const struct pipe_shader_state *cso)
76 {
77 return create_shader_stateobj(pctx, cso, SHADER_VERTEX);
78 }
79
80 static void
81 fd4_vp_state_delete(struct pipe_context *pctx, void *hwcso)
82 {
83 struct fd4_shader_stateobj *so = hwcso;
84 delete_shader_stateobj(so);
85 }
86
87 static void
88 emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
89 {
90 const struct ir3_info *si = &so->info;
91 enum adreno_state_block sb;
92 enum adreno_state_src src;
93 uint32_t i, sz, *bin;
94
95 if (so->type == SHADER_VERTEX) {
96 sb = SB_VERT_SHADER;
97 } else {
98 sb = SB_FRAG_SHADER;
99 }
100
101 if (fd_mesa_debug & FD_DBG_DIRECT) {
102 sz = si->sizedwords;
103 src = SS_DIRECT;
104 bin = fd_bo_map(so->bo);
105 } else {
106 sz = 0;
107 src = 2; // enums different on a4xx..
108 bin = NULL;
109 }
110
111 OUT_PKT3(ring, CP_LOAD_STATE, 2 + sz);
112 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
113 CP_LOAD_STATE_0_STATE_SRC(src) |
114 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
115 CP_LOAD_STATE_0_NUM_UNIT(so->instrlen));
116 if (bin) {
117 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
118 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER));
119 } else {
120 OUT_RELOC(ring, so->bo, 0,
121 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER), 0);
122 }
123 for (i = 0; i < sz; i++) {
124 OUT_RING(ring, bin[i]);
125 }
126 }
127
128 struct stage {
129 const struct ir3_shader_variant *v;
130 const struct ir3_info *i;
131 /* const sizes are in units of 4 * vec4 */
132 uint8_t constoff;
133 uint8_t constlen;
134 /* instr sizes are in units of 16 instructions */
135 uint8_t instroff;
136 uint8_t instrlen;
137 };
138
139 enum {
140 VS = 0,
141 FS = 1,
142 HS = 2,
143 DS = 3,
144 GS = 4,
145 MAX_STAGES
146 };
147
148 static void
149 setup_stages(struct fd4_emit *emit, struct stage *s)
150 {
151 unsigned i;
152
153 s[VS].v = fd4_emit_get_vp(emit);
154 s[FS].v = fd4_emit_get_fp(emit);
155
156 s[HS].v = s[DS].v = s[GS].v = NULL; /* for now */
157
158 for (i = 0; i < MAX_STAGES; i++) {
159 if (s[i].v) {
160 s[i].i = &s[i].v->info;
161 /* constlen is in units of 4 * vec4: */
162 s[i].constlen = align(s[i].v->constlen, 4) / 4;
163 /* instrlen is already in units of 16 instr.. although
164 * probably we should ditch that and not make the compiler
165 * care about instruction group size of a3xx vs a4xx
166 */
167 s[i].instrlen = s[i].v->instrlen;
168 } else {
169 s[i].i = NULL;
170 s[i].constlen = 0;
171 s[i].instrlen = 0;
172 }
173 }
174
175 /* NOTE: at least for gles2, blob partitions VS at bottom of const
176 * space and FS taking entire remaining space. We probably don't
177 * need to do that the same way, but for now mimic what the blob
178 * does to make it easier to diff against register values from blob
179 *
180 * NOTE: if VS.instrlen + FS.instrlen > 64, then one or both shaders
181 * is run from external memory.
182 */
183 if ((s[VS].instrlen + s[FS].instrlen) > 64) {
184 /* prioritize FS for internal memory: */
185 if (s[FS].instrlen < 64) {
186 /* if FS can fit, kick VS out to external memory: */
187 s[VS].instrlen = 0;
188 } else if (s[VS].instrlen < 64) {
189 /* otherwise if VS can fit, kick out FS: */
190 s[FS].instrlen = 0;
191 } else {
192 /* neither can fit, run both from external memory: */
193 s[VS].instrlen = 0;
194 s[FS].instrlen = 0;
195 }
196 }
197 s[VS].constlen = 66;
198 s[FS].constlen = 128 - s[VS].constlen;
199 s[VS].instroff = 0;
200 s[VS].constoff = 0;
201 s[FS].instroff = 64 - s[FS].instrlen;
202 s[FS].constoff = s[VS].constlen;
203 s[HS].instroff = s[DS].instroff = s[GS].instroff = s[FS].instroff;
204 s[HS].constoff = s[DS].constoff = s[GS].constoff = s[FS].constoff;
205 }
206
207 void
208 fd4_program_emit(struct fd_ringbuffer *ring, struct fd4_emit *emit,
209 int nr, struct pipe_surface **bufs)
210 {
211 struct stage s[MAX_STAGES];
212 uint32_t pos_regid, posz_regid, psize_regid, color_regid[8];
213 uint32_t face_regid, coord_regid, zwcoord_regid;
214 enum a3xx_threadsize fssz;
215 int constmode;
216 int i, j, k;
217
218 debug_assert(nr <= ARRAY_SIZE(color_regid));
219
220 setup_stages(emit, s);
221
222 fssz = (s[FS].i->max_reg >= 24) ? TWO_QUADS : FOUR_QUADS;
223
224 /* blob seems to always use constmode currently: */
225 constmode = 1;
226
227 pos_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_POS);
228 posz_regid = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DEPTH);
229 psize_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_PSIZ);
230 if (s[FS].v->color0_mrt) {
231 color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
232 color_regid[4] = color_regid[5] = color_regid[6] = color_regid[7] =
233 ir3_find_output_regid(s[FS].v, FRAG_RESULT_COLOR);
234 } else {
235 color_regid[0] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA0);
236 color_regid[1] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA1);
237 color_regid[2] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA2);
238 color_regid[3] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA3);
239 color_regid[4] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA4);
240 color_regid[5] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA5);
241 color_regid[6] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA6);
242 color_regid[7] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA7);
243 }
244
245 /* TODO get these dynamically: */
246 face_regid = s[FS].v->frag_face ? regid(0,0) : regid(63,0);
247 coord_regid = s[FS].v->frag_coord ? regid(0,0) : regid(63,0);
248 zwcoord_regid = s[FS].v->frag_coord ? regid(0,2) : regid(63,0);
249
250 /* we could probably divide this up into things that need to be
251 * emitted if frag-prog is dirty vs if vert-prog is dirty..
252 */
253
254 OUT_PKT0(ring, REG_A4XX_HLSQ_UPDATE_CONTROL, 1);
255 OUT_RING(ring, 0x00000003);
256
257 OUT_PKT0(ring, REG_A4XX_HLSQ_CONTROL_0_REG, 5);
258 OUT_RING(ring, A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(fssz) |
259 A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(constmode) |
260 A4XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE |
261 /* NOTE: I guess SHADERRESTART and CONSTFULLUPDATE maybe
262 * flush some caches? I think we only need to set those
263 * bits if we have updated const or shader..
264 */
265 A4XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART |
266 A4XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE);
267 OUT_RING(ring, A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
268 A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE |
269 A4XX_HLSQ_CONTROL_1_REG_COORDREGID(coord_regid) |
270 A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID(zwcoord_regid));
271 OUT_RING(ring, A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(63) |
272 0x3f3f000 | /* XXX */
273 A4XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid));
274 OUT_RING(ring, A4XX_HLSQ_CONTROL_3_REG_REGID(s[FS].v->pos_regid) |
275 0xfcfcfc00);
276 OUT_RING(ring, 0x00fcfcfc); /* XXX HLSQ_CONTROL_4 */
277
278 OUT_PKT0(ring, REG_A4XX_HLSQ_VS_CONTROL_REG, 5);
279 OUT_RING(ring, A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(s[VS].constlen) |
280 A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(s[VS].constoff) |
281 A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(s[VS].instrlen) |
282 A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(s[VS].instroff));
283 OUT_RING(ring, A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(s[FS].constlen) |
284 A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(s[FS].constoff) |
285 A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(s[FS].instrlen) |
286 A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(s[FS].instroff));
287 OUT_RING(ring, A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(s[HS].constlen) |
288 A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(s[HS].constoff) |
289 A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(s[HS].instrlen) |
290 A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(s[HS].instroff));
291 OUT_RING(ring, A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(s[DS].constlen) |
292 A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(s[DS].constoff) |
293 A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(s[DS].instrlen) |
294 A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(s[DS].instroff));
295 OUT_RING(ring, A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(s[GS].constlen) |
296 A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(s[GS].constoff) |
297 A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(s[GS].instrlen) |
298 A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(s[GS].instroff));
299
300 OUT_PKT0(ring, REG_A4XX_SP_SP_CTRL_REG, 1);
301 OUT_RING(ring, 0x140010 | /* XXX */
302 COND(emit->key.binning_pass, A4XX_SP_SP_CTRL_REG_BINNING_PASS));
303
304 OUT_PKT0(ring, REG_A4XX_SP_INSTR_CACHE_CTRL, 1);
305 OUT_RING(ring, 0x7f | /* XXX */
306 COND(s[VS].instrlen, A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER) |
307 COND(s[FS].instrlen, A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER) |
308 COND(s[VS].instrlen && s[FS].instrlen,
309 A4XX_SP_INSTR_CACHE_CTRL_INSTR_BUFFER));
310
311 OUT_PKT0(ring, REG_A4XX_SP_VS_LENGTH_REG, 1);
312 OUT_RING(ring, s[VS].v->instrlen); /* SP_VS_LENGTH_REG */
313
314 OUT_PKT0(ring, REG_A4XX_SP_VS_CTRL_REG0, 3);
315 OUT_RING(ring, A4XX_SP_VS_CTRL_REG0_THREADMODE(MULTI) |
316 A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(s[VS].i->max_half_reg + 1) |
317 A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(s[VS].i->max_reg + 1) |
318 A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(0) |
319 A4XX_SP_VS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
320 A4XX_SP_VS_CTRL_REG0_SUPERTHREADMODE |
321 COND(s[VS].v->has_samp, A4XX_SP_VS_CTRL_REG0_PIXLODENABLE));
322 OUT_RING(ring, A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(s[VS].constlen) |
323 A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(s[VS].v->total_in));
324 OUT_RING(ring, A4XX_SP_VS_PARAM_REG_POSREGID(pos_regid) |
325 A4XX_SP_VS_PARAM_REG_PSIZEREGID(psize_regid) |
326 A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(s[FS].v->varying_in));
327
328 for (i = 0, j = -1; (i < 16) && (j < (int)s[FS].v->inputs_count); i++) {
329 uint32_t reg = 0;
330
331 OUT_PKT0(ring, REG_A4XX_SP_VS_OUT_REG(i), 1);
332
333 j = ir3_next_varying(s[FS].v, j);
334 if (j < s[FS].v->inputs_count) {
335 k = ir3_find_output(s[VS].v, s[FS].v->inputs[j].slot);
336 reg |= A4XX_SP_VS_OUT_REG_A_REGID(s[VS].v->outputs[k].regid);
337 reg |= A4XX_SP_VS_OUT_REG_A_COMPMASK(s[FS].v->inputs[j].compmask);
338 }
339
340 j = ir3_next_varying(s[FS].v, j);
341 if (j < s[FS].v->inputs_count) {
342 k = ir3_find_output(s[VS].v, s[FS].v->inputs[j].slot);
343 reg |= A4XX_SP_VS_OUT_REG_B_REGID(s[VS].v->outputs[k].regid);
344 reg |= A4XX_SP_VS_OUT_REG_B_COMPMASK(s[FS].v->inputs[j].compmask);
345 }
346
347 OUT_RING(ring, reg);
348 }
349
350 for (i = 0, j = -1; (i < 8) && (j < (int)s[FS].v->inputs_count); i++) {
351 uint32_t reg = 0;
352
353 OUT_PKT0(ring, REG_A4XX_SP_VS_VPC_DST_REG(i), 1);
354
355 j = ir3_next_varying(s[FS].v, j);
356 if (j < s[FS].v->inputs_count)
357 reg |= A4XX_SP_VS_VPC_DST_REG_OUTLOC0(s[FS].v->inputs[j].inloc);
358 j = ir3_next_varying(s[FS].v, j);
359 if (j < s[FS].v->inputs_count)
360 reg |= A4XX_SP_VS_VPC_DST_REG_OUTLOC1(s[FS].v->inputs[j].inloc);
361 j = ir3_next_varying(s[FS].v, j);
362 if (j < s[FS].v->inputs_count)
363 reg |= A4XX_SP_VS_VPC_DST_REG_OUTLOC2(s[FS].v->inputs[j].inloc);
364 j = ir3_next_varying(s[FS].v, j);
365 if (j < s[FS].v->inputs_count)
366 reg |= A4XX_SP_VS_VPC_DST_REG_OUTLOC3(s[FS].v->inputs[j].inloc);
367
368 OUT_RING(ring, reg);
369 }
370
371 OUT_PKT0(ring, REG_A4XX_SP_VS_OBJ_OFFSET_REG, 2);
372 OUT_RING(ring, A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[VS].constoff) |
373 A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[VS].instroff));
374 OUT_RELOC(ring, s[VS].v->bo, 0, 0, 0); /* SP_VS_OBJ_START_REG */
375
376 OUT_PKT0(ring, REG_A4XX_SP_FS_LENGTH_REG, 1);
377 OUT_RING(ring, s[FS].v->instrlen); /* SP_FS_LENGTH_REG */
378
379 OUT_PKT0(ring, REG_A4XX_SP_FS_CTRL_REG0, 2);
380 OUT_RING(ring, A4XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
381 COND(s[FS].v->total_in > 0, A4XX_SP_FS_CTRL_REG0_VARYING) |
382 A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(s[FS].i->max_half_reg + 1) |
383 A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s[FS].i->max_reg + 1) |
384 A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(1) |
385 A4XX_SP_FS_CTRL_REG0_THREADSIZE(fssz) |
386 A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE |
387 COND(s[FS].v->has_samp, A4XX_SP_FS_CTRL_REG0_PIXLODENABLE));
388 OUT_RING(ring, A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(s[FS].constlen) |
389 0x80000000 | /* XXX */
390 COND(s[FS].v->frag_face, A4XX_SP_FS_CTRL_REG1_FACENESS) |
391 COND(s[FS].v->total_in > 0, A4XX_SP_FS_CTRL_REG1_VARYING) |
392 COND(s[FS].v->frag_coord, A4XX_SP_FS_CTRL_REG1_FRAGCOORD));
393
394 OUT_PKT0(ring, REG_A4XX_SP_FS_OBJ_OFFSET_REG, 2);
395 OUT_RING(ring, A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[FS].constoff) |
396 A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[FS].instroff));
397 if (emit->key.binning_pass)
398 OUT_RING(ring, 0x00000000);
399 else
400 OUT_RELOC(ring, s[FS].v->bo, 0, 0, 0); /* SP_FS_OBJ_START_REG */
401
402 OUT_PKT0(ring, REG_A4XX_SP_HS_OBJ_OFFSET_REG, 1);
403 OUT_RING(ring, A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[HS].constoff) |
404 A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[HS].instroff));
405
406 OUT_PKT0(ring, REG_A4XX_SP_DS_OBJ_OFFSET_REG, 1);
407 OUT_RING(ring, A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[DS].constoff) |
408 A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[DS].instroff));
409
410 OUT_PKT0(ring, REG_A4XX_SP_GS_OBJ_OFFSET_REG, 1);
411 OUT_RING(ring, A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[GS].constoff) |
412 A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[GS].instroff));
413
414 OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL2, 1);
415 OUT_RING(ring, A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(0) |
416 COND(s[FS].v->total_in > 0, A4XX_RB_RENDER_CONTROL2_VARYING) |
417 COND(s[FS].v->frag_face, A4XX_RB_RENDER_CONTROL2_FACENESS) |
418 COND(s[FS].v->frag_coord, A4XX_RB_RENDER_CONTROL2_XCOORD |
419 A4XX_RB_RENDER_CONTROL2_YCOORD |
420 A4XX_RB_RENDER_CONTROL2_ZCOORD |
421 A4XX_RB_RENDER_CONTROL2_WCOORD));
422
423 OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT_REG, 1);
424 OUT_RING(ring, A4XX_RB_FS_OUTPUT_REG_MRT(MAX2(1, nr)) |
425 COND(s[FS].v->writes_pos, A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z));
426
427 OUT_PKT0(ring, REG_A4XX_SP_FS_OUTPUT_REG, 1);
428 OUT_RING(ring, A4XX_SP_FS_OUTPUT_REG_MRT(MAX2(1, nr)) |
429 COND(s[FS].v->writes_pos, A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE) |
430 A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(posz_regid));
431
432 OUT_PKT0(ring, REG_A4XX_SP_FS_MRT_REG(0), 8);
433 for (i = 0; i < 8; i++) {
434 enum a4xx_color_fmt format = 0;
435 bool srgb = false;
436 if (i < nr) {
437 format = fd4_emit_format(bufs[i]);
438 if (bufs[i] && !emit->no_decode_srgb)
439 srgb = util_format_is_srgb(bufs[i]->format);
440 }
441 OUT_RING(ring, A4XX_SP_FS_MRT_REG_REGID(color_regid[i]) |
442 A4XX_SP_FS_MRT_REG_MRTFORMAT(format) |
443 COND(srgb, A4XX_SP_FS_MRT_REG_COLOR_SRGB) |
444 COND(emit->key.half_precision,
445 A4XX_SP_FS_MRT_REG_HALF_PRECISION));
446 }
447
448 if (emit->key.binning_pass) {
449 OUT_PKT0(ring, REG_A4XX_VPC_ATTR, 2);
450 OUT_RING(ring, A4XX_VPC_ATTR_THRDASSIGN(1) |
451 0x40000000 | /* XXX */
452 COND(s[VS].v->writes_psize, A4XX_VPC_ATTR_PSIZE));
453 OUT_RING(ring, 0x00000000);
454 } else {
455 uint32_t vinterp[8], vpsrepl[8];
456
457 memset(vinterp, 0, sizeof(vinterp));
458 memset(vpsrepl, 0, sizeof(vpsrepl));
459
460 /* looks like we need to do int varyings in the frag
461 * shader on a4xx (no flatshad reg? or a420.0 bug?):
462 *
463 * (sy)(ss)nop
464 * (sy)ldlv.u32 r0.x,l[r0.x], 1
465 * ldlv.u32 r0.y,l[r0.x+1], 1
466 * (ss)bary.f (ei)r63.x, 0, r0.x
467 * (ss)(rpt1)cov.s32f16 hr0.x, (r)r0.x
468 * (rpt5)nop
469 * sam (f16)(xyzw)hr0.x, hr0.x, s#0, t#0
470 *
471 * Possibly on later a4xx variants we'll be able to use
472 * something like the code below instead of workaround
473 * in the shader:
474 */
475 /* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
476 for (j = -1; (j = ir3_next_varying(s[FS].v, j)) < (int)s[FS].v->inputs_count; ) {
477 /* NOTE: varyings are packed, so if compmask is 0xb
478 * then first, third, and fourth component occupy
479 * three consecutive varying slots:
480 */
481 unsigned compmask = s[FS].v->inputs[j].compmask;
482
483 /* TODO might be cleaner to just +8 in SP_VS_VPC_DST_REG
484 * instead.. rather than -8 everywhere else..
485 */
486 uint32_t inloc = s[FS].v->inputs[j].inloc - 8;
487
488 if ((s[FS].v->inputs[j].interpolate == INTERP_QUALIFIER_FLAT) ||
489 (s[FS].v->inputs[j].rasterflat && emit->rasterflat)) {
490 uint32_t loc = inloc;
491
492 for (i = 0; i < 4; i++) {
493 if (compmask & (1 << i)) {
494 vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
495 //flatshade[loc / 32] |= 1 << (loc % 32);
496 loc++;
497 }
498 }
499 }
500
501 gl_varying_slot slot = s[FS].v->inputs[j].slot;
502
503 /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
504 if (slot >= VARYING_SLOT_VAR0) {
505 unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
506 /* Replace the .xy coordinates with S/T from the point sprite. Set
507 * interpolation bits for .zw such that they become .01
508 */
509 if (emit->sprite_coord_enable & texmask) {
510 /* mask is two 2-bit fields, where:
511 * '01' -> S
512 * '10' -> T
513 * '11' -> 1 - T (flip mode)
514 */
515 unsigned mask = emit->sprite_coord_mode ? 0b1101 : 0b1001;
516 uint32_t loc = inloc;
517 if (compmask & 0x1) {
518 vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
519 loc++;
520 }
521 if (compmask & 0x2) {
522 vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
523 loc++;
524 }
525 if (compmask & 0x4) {
526 /* .z <- 0.0f */
527 vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
528 loc++;
529 }
530 if (compmask & 0x8) {
531 /* .w <- 1.0f */
532 vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
533 loc++;
534 }
535 }
536 }
537 }
538
539 OUT_PKT0(ring, REG_A4XX_VPC_ATTR, 2);
540 OUT_RING(ring, A4XX_VPC_ATTR_TOTALATTR(s[FS].v->total_in) |
541 A4XX_VPC_ATTR_THRDASSIGN(1) |
542 COND(s[FS].v->total_in > 0, A4XX_VPC_ATTR_ENABLE) |
543 0x40000000 | /* XXX */
544 COND(s[VS].v->writes_psize, A4XX_VPC_ATTR_PSIZE));
545 OUT_RING(ring, A4XX_VPC_PACK_NUMFPNONPOSVAR(s[FS].v->total_in) |
546 A4XX_VPC_PACK_NUMNONPOSVSVAR(s[FS].v->total_in));
547
548 OUT_PKT0(ring, REG_A4XX_VPC_VARYING_INTERP_MODE(0), 8);
549 for (i = 0; i < 8; i++)
550 OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
551
552 OUT_PKT0(ring, REG_A4XX_VPC_VARYING_PS_REPL_MODE(0), 8);
553 for (i = 0; i < 8; i++)
554 OUT_RING(ring, vpsrepl[i]); /* VPC_VARYING_PS_REPL[i] */
555 }
556
557 if (s[VS].instrlen)
558 emit_shader(ring, s[VS].v);
559
560 if (!emit->key.binning_pass)
561 if (s[FS].instrlen)
562 emit_shader(ring, s[FS].v);
563 }
564
565 void
566 fd4_prog_init(struct pipe_context *pctx)
567 {
568 pctx->create_fs_state = fd4_fp_state_create;
569 pctx->delete_fs_state = fd4_fp_state_delete;
570
571 pctx->create_vs_state = fd4_vp_state_create;
572 pctx->delete_vs_state = fd4_vp_state_delete;
573
574 fd_prog_init(pctx);
575 }