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Added few more stubs so that control reaches to DestroyDevice().
[mesa.git] / src / gallium / drivers / freedreno / a4xx / fd4_program.c
1 /*
2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_inlines.h"
31 #include "util/format/u_format.h"
32
33 #include "freedreno_program.h"
34
35 #include "fd4_program.h"
36 #include "fd4_emit.h"
37 #include "fd4_texture.h"
38 #include "fd4_format.h"
39
40 static void
41 emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
42 {
43 const struct ir3_info *si = &so->info;
44 enum a4xx_state_block sb = fd4_stage2shadersb(so->type);
45 enum a4xx_state_src src;
46 uint32_t i, sz, *bin;
47
48 if (fd_mesa_debug & FD_DBG_DIRECT) {
49 sz = si->sizedwords;
50 src = SS4_DIRECT;
51 bin = fd_bo_map(so->bo);
52 } else {
53 sz = 0;
54 src = SS4_INDIRECT;
55 bin = NULL;
56 }
57
58 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + sz);
59 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
60 CP_LOAD_STATE4_0_STATE_SRC(src) |
61 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
62 CP_LOAD_STATE4_0_NUM_UNIT(so->instrlen));
63 if (bin) {
64 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
65 CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER));
66 } else {
67 OUT_RELOC(ring, so->bo, 0,
68 CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER), 0);
69 }
70
71 /* for how clever coverity is, it is sometimes rather dull, and
72 * doesn't realize that the only case where bin==NULL, sz==0:
73 */
74 assume(bin || (sz == 0));
75
76 for (i = 0; i < sz; i++) {
77 OUT_RING(ring, bin[i]);
78 }
79 }
80
81 struct stage {
82 const struct ir3_shader_variant *v;
83 const struct ir3_info *i;
84 /* const sizes are in units of 4 * vec4 */
85 uint8_t constoff;
86 uint8_t constlen;
87 /* instr sizes are in units of 16 instructions */
88 uint8_t instroff;
89 uint8_t instrlen;
90 };
91
92 enum {
93 VS = 0,
94 FS = 1,
95 HS = 2,
96 DS = 3,
97 GS = 4,
98 MAX_STAGES
99 };
100
101 static void
102 setup_stages(struct fd4_emit *emit, struct stage *s)
103 {
104 unsigned i;
105
106 s[VS].v = fd4_emit_get_vp(emit);
107 s[FS].v = fd4_emit_get_fp(emit);
108
109 s[HS].v = s[DS].v = s[GS].v = NULL; /* for now */
110
111 for (i = 0; i < MAX_STAGES; i++) {
112 if (s[i].v) {
113 s[i].i = &s[i].v->info;
114 /* constlen is in units of 4 * vec4: */
115 assert(s[i].v->constlen % 4 == 0);
116 s[i].constlen = s[i].v->constlen / 4;
117 /* instrlen is already in units of 16 instr.. although
118 * probably we should ditch that and not make the compiler
119 * care about instruction group size of a3xx vs a4xx
120 */
121 s[i].instrlen = s[i].v->instrlen;
122 } else {
123 s[i].i = NULL;
124 s[i].constlen = 0;
125 s[i].instrlen = 0;
126 }
127 }
128
129 /* NOTE: at least for gles2, blob partitions VS at bottom of const
130 * space and FS taking entire remaining space. We probably don't
131 * need to do that the same way, but for now mimic what the blob
132 * does to make it easier to diff against register values from blob
133 *
134 * NOTE: if VS.instrlen + FS.instrlen > 64, then one or both shaders
135 * is run from external memory.
136 */
137 if ((s[VS].instrlen + s[FS].instrlen) > 64) {
138 /* prioritize FS for internal memory: */
139 if (s[FS].instrlen < 64) {
140 /* if FS can fit, kick VS out to external memory: */
141 s[VS].instrlen = 0;
142 } else if (s[VS].instrlen < 64) {
143 /* otherwise if VS can fit, kick out FS: */
144 s[FS].instrlen = 0;
145 } else {
146 /* neither can fit, run both from external memory: */
147 s[VS].instrlen = 0;
148 s[FS].instrlen = 0;
149 }
150 }
151 s[VS].constlen = 66;
152 s[FS].constlen = 128 - s[VS].constlen;
153 s[VS].instroff = 0;
154 s[VS].constoff = 0;
155 s[FS].instroff = 64 - s[FS].instrlen;
156 s[FS].constoff = s[VS].constlen;
157 s[HS].instroff = s[DS].instroff = s[GS].instroff = s[FS].instroff;
158 s[HS].constoff = s[DS].constoff = s[GS].constoff = s[FS].constoff;
159 }
160
161 void
162 fd4_program_emit(struct fd_ringbuffer *ring, struct fd4_emit *emit,
163 int nr, struct pipe_surface **bufs)
164 {
165 struct stage s[MAX_STAGES];
166 uint32_t pos_regid, posz_regid, psize_regid, color_regid[8];
167 uint32_t face_regid, coord_regid, zwcoord_regid, ij_regid[IJ_COUNT];
168 enum a3xx_threadsize fssz;
169 int constmode;
170 int i, j;
171
172 debug_assert(nr <= ARRAY_SIZE(color_regid));
173
174 if (emit->binning_pass)
175 nr = 0;
176
177 setup_stages(emit, s);
178
179 fssz = (s[FS].i->max_reg >= 24) ? TWO_QUADS : FOUR_QUADS;
180
181 /* blob seems to always use constmode currently: */
182 constmode = 1;
183
184 pos_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_POS);
185 if (pos_regid == regid(63, 0)) {
186 /* hw dislikes when there is no position output, which can
187 * happen for transform-feedback vertex shaders. Just tell
188 * the hw to use r0.x, with whatever random value is there:
189 */
190 pos_regid = regid(0, 0);
191 }
192 posz_regid = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DEPTH);
193 psize_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_PSIZ);
194 if (s[FS].v->color0_mrt) {
195 color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
196 color_regid[4] = color_regid[5] = color_regid[6] = color_regid[7] =
197 ir3_find_output_regid(s[FS].v, FRAG_RESULT_COLOR);
198 } else {
199 color_regid[0] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA0);
200 color_regid[1] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA1);
201 color_regid[2] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA2);
202 color_regid[3] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA3);
203 color_regid[4] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA4);
204 color_regid[5] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA5);
205 color_regid[6] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA6);
206 color_regid[7] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA7);
207 }
208
209 face_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_FRONT_FACE);
210 coord_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_FRAG_COORD);
211 zwcoord_regid = (coord_regid == regid(63,0)) ? regid(63,0) : (coord_regid + 2);
212 for (unsigned i = 0; i < ARRAY_SIZE(ij_regid); i++)
213 ij_regid[i] = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL + i);
214
215 /* we could probably divide this up into things that need to be
216 * emitted if frag-prog is dirty vs if vert-prog is dirty..
217 */
218
219 OUT_PKT0(ring, REG_A4XX_HLSQ_UPDATE_CONTROL, 1);
220 OUT_RING(ring, 0x00000003);
221
222 OUT_PKT0(ring, REG_A4XX_HLSQ_CONTROL_0_REG, 5);
223 OUT_RING(ring, A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(fssz) |
224 A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(constmode) |
225 A4XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE |
226 /* NOTE: I guess SHADERRESTART and CONSTFULLUPDATE maybe
227 * flush some caches? I think we only need to set those
228 * bits if we have updated const or shader..
229 */
230 A4XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART |
231 A4XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE);
232 OUT_RING(ring, A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
233 A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE |
234 A4XX_HLSQ_CONTROL_1_REG_COORDREGID(coord_regid) |
235 A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID(zwcoord_regid));
236 OUT_RING(ring, A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(63) |
237 0x3f3f000 | /* XXX */
238 A4XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid));
239 /* XXX left out centroid/sample for now */
240 OUT_RING(ring, A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(ij_regid[IJ_PERSP_PIXEL]) |
241 A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(ij_regid[IJ_LINEAR_PIXEL]) |
242 A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(ij_regid[IJ_PERSP_CENTROID]) |
243 A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(ij_regid[IJ_LINEAR_CENTROID]));
244 OUT_RING(ring, 0x00fcfcfc); /* XXX HLSQ_CONTROL_4 */
245
246 OUT_PKT0(ring, REG_A4XX_HLSQ_VS_CONTROL_REG, 5);
247 OUT_RING(ring, A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(s[VS].constlen) |
248 A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(s[VS].constoff) |
249 A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(s[VS].instrlen) |
250 A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(s[VS].instroff));
251 OUT_RING(ring, A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(s[FS].constlen) |
252 A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(s[FS].constoff) |
253 A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(s[FS].instrlen) |
254 A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(s[FS].instroff));
255 OUT_RING(ring, A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(s[HS].constlen) |
256 A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(s[HS].constoff) |
257 A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(s[HS].instrlen) |
258 A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(s[HS].instroff));
259 OUT_RING(ring, A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(s[DS].constlen) |
260 A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(s[DS].constoff) |
261 A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(s[DS].instrlen) |
262 A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(s[DS].instroff));
263 OUT_RING(ring, A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(s[GS].constlen) |
264 A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(s[GS].constoff) |
265 A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(s[GS].instrlen) |
266 A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(s[GS].instroff));
267
268 OUT_PKT0(ring, REG_A4XX_SP_SP_CTRL_REG, 1);
269 OUT_RING(ring, 0x140010 | /* XXX */
270 COND(emit->binning_pass, A4XX_SP_SP_CTRL_REG_BINNING_PASS));
271
272 OUT_PKT0(ring, REG_A4XX_SP_INSTR_CACHE_CTRL, 1);
273 OUT_RING(ring, 0x7f | /* XXX */
274 COND(s[VS].instrlen, A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER) |
275 COND(s[FS].instrlen, A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER) |
276 COND(s[VS].instrlen && s[FS].instrlen,
277 A4XX_SP_INSTR_CACHE_CTRL_INSTR_BUFFER));
278
279 OUT_PKT0(ring, REG_A4XX_SP_VS_LENGTH_REG, 1);
280 OUT_RING(ring, s[VS].v->instrlen); /* SP_VS_LENGTH_REG */
281
282 OUT_PKT0(ring, REG_A4XX_SP_VS_CTRL_REG0, 3);
283 OUT_RING(ring, A4XX_SP_VS_CTRL_REG0_THREADMODE(MULTI) |
284 A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(s[VS].i->max_half_reg + 1) |
285 A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(s[VS].i->max_reg + 1) |
286 A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(0) |
287 A4XX_SP_VS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
288 A4XX_SP_VS_CTRL_REG0_SUPERTHREADMODE |
289 COND(s[VS].v->need_pixlod, A4XX_SP_VS_CTRL_REG0_PIXLODENABLE));
290 OUT_RING(ring, A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(s[VS].constlen) |
291 A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(s[VS].v->total_in));
292 OUT_RING(ring, A4XX_SP_VS_PARAM_REG_POSREGID(pos_regid) |
293 A4XX_SP_VS_PARAM_REG_PSIZEREGID(psize_regid) |
294 A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(s[FS].v->varying_in));
295
296 struct ir3_shader_linkage l = {0};
297 ir3_link_shaders(&l, s[VS].v, s[FS].v, false);
298
299 for (i = 0, j = 0; (i < 16) && (j < l.cnt); i++) {
300 uint32_t reg = 0;
301
302 OUT_PKT0(ring, REG_A4XX_SP_VS_OUT_REG(i), 1);
303
304 reg |= A4XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid);
305 reg |= A4XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask);
306 j++;
307
308 reg |= A4XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid);
309 reg |= A4XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask);
310 j++;
311
312 OUT_RING(ring, reg);
313 }
314
315 for (i = 0, j = 0; (i < 8) && (j < l.cnt); i++) {
316 uint32_t reg = 0;
317
318 OUT_PKT0(ring, REG_A4XX_SP_VS_VPC_DST_REG(i), 1);
319
320 reg |= A4XX_SP_VS_VPC_DST_REG_OUTLOC0(l.var[j++].loc + 8);
321 reg |= A4XX_SP_VS_VPC_DST_REG_OUTLOC1(l.var[j++].loc + 8);
322 reg |= A4XX_SP_VS_VPC_DST_REG_OUTLOC2(l.var[j++].loc + 8);
323 reg |= A4XX_SP_VS_VPC_DST_REG_OUTLOC3(l.var[j++].loc + 8);
324
325 OUT_RING(ring, reg);
326 }
327
328 OUT_PKT0(ring, REG_A4XX_SP_VS_OBJ_OFFSET_REG, 2);
329 OUT_RING(ring, A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[VS].constoff) |
330 A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[VS].instroff));
331 OUT_RELOC(ring, s[VS].v->bo, 0, 0, 0); /* SP_VS_OBJ_START_REG */
332
333 if (emit->binning_pass) {
334 OUT_PKT0(ring, REG_A4XX_SP_FS_LENGTH_REG, 1);
335 OUT_RING(ring, 0x00000000); /* SP_FS_LENGTH_REG */
336
337 OUT_PKT0(ring, REG_A4XX_SP_FS_CTRL_REG0, 2);
338 OUT_RING(ring, A4XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
339 COND(s[FS].v->total_in > 0, A4XX_SP_FS_CTRL_REG0_VARYING) |
340 A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(0) |
341 A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(0) |
342 A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(1) |
343 A4XX_SP_FS_CTRL_REG0_THREADSIZE(fssz) |
344 A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE);
345 OUT_RING(ring, A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(s[FS].constlen) |
346 0x80000000);
347
348 OUT_PKT0(ring, REG_A4XX_SP_FS_OBJ_OFFSET_REG, 2);
349 OUT_RING(ring, A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[FS].constoff) |
350 A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[FS].instroff));
351 OUT_RING(ring, 0x00000000);
352 } else {
353 OUT_PKT0(ring, REG_A4XX_SP_FS_LENGTH_REG, 1);
354 OUT_RING(ring, s[FS].v->instrlen); /* SP_FS_LENGTH_REG */
355
356 OUT_PKT0(ring, REG_A4XX_SP_FS_CTRL_REG0, 2);
357 OUT_RING(ring, A4XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
358 COND(s[FS].v->total_in > 0, A4XX_SP_FS_CTRL_REG0_VARYING) |
359 A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(s[FS].i->max_half_reg + 1) |
360 A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s[FS].i->max_reg + 1) |
361 A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(1) |
362 A4XX_SP_FS_CTRL_REG0_THREADSIZE(fssz) |
363 A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE |
364 COND(s[FS].v->need_pixlod, A4XX_SP_FS_CTRL_REG0_PIXLODENABLE));
365 OUT_RING(ring, A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(s[FS].constlen) |
366 0x80000000 | /* XXX */
367 COND(s[FS].v->frag_face, A4XX_SP_FS_CTRL_REG1_FACENESS) |
368 COND(s[FS].v->total_in > 0, A4XX_SP_FS_CTRL_REG1_VARYING) |
369 COND(s[FS].v->fragcoord_compmask != 0, A4XX_SP_FS_CTRL_REG1_FRAGCOORD));
370
371 OUT_PKT0(ring, REG_A4XX_SP_FS_OBJ_OFFSET_REG, 2);
372 OUT_RING(ring, A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[FS].constoff) |
373 A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[FS].instroff));
374 OUT_RELOC(ring, s[FS].v->bo, 0, 0, 0); /* SP_FS_OBJ_START_REG */
375 }
376
377 OUT_PKT0(ring, REG_A4XX_SP_HS_OBJ_OFFSET_REG, 1);
378 OUT_RING(ring, A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[HS].constoff) |
379 A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[HS].instroff));
380
381 OUT_PKT0(ring, REG_A4XX_SP_DS_OBJ_OFFSET_REG, 1);
382 OUT_RING(ring, A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[DS].constoff) |
383 A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[DS].instroff));
384
385 OUT_PKT0(ring, REG_A4XX_SP_GS_OBJ_OFFSET_REG, 1);
386 OUT_RING(ring, A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[GS].constoff) |
387 A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[GS].instroff));
388
389 OUT_PKT0(ring, REG_A4XX_GRAS_CNTL, 1);
390 OUT_RING(ring,
391 CONDREG(face_regid, A4XX_GRAS_CNTL_IJ_PERSP) |
392 CONDREG(zwcoord_regid, A4XX_GRAS_CNTL_IJ_PERSP) |
393 CONDREG(ij_regid[IJ_PERSP_PIXEL], A4XX_GRAS_CNTL_IJ_PERSP) |
394 CONDREG(ij_regid[IJ_LINEAR_PIXEL], A4XX_GRAS_CNTL_IJ_LINEAR) |
395 CONDREG(ij_regid[IJ_PERSP_CENTROID], A4XX_GRAS_CNTL_IJ_PERSP));
396
397 OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL2, 1);
398 OUT_RING(ring, A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(0) |
399 CONDREG(ij_regid[IJ_PERSP_PIXEL], A4XX_RB_RENDER_CONTROL2_IJ_PERSP_PIXEL) |
400 CONDREG(ij_regid[IJ_PERSP_CENTROID], A4XX_RB_RENDER_CONTROL2_IJ_PERSP_CENTROID) |
401 CONDREG(ij_regid[IJ_LINEAR_PIXEL], A4XX_RB_RENDER_CONTROL2_SIZE) |
402 COND(s[FS].v->frag_face, A4XX_RB_RENDER_CONTROL2_FACENESS) |
403 COND(s[FS].v->fragcoord_compmask != 0,
404 A4XX_RB_RENDER_CONTROL2_COORD_MASK(s[FS].v->fragcoord_compmask)));
405
406 OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT_REG, 1);
407 OUT_RING(ring, A4XX_RB_FS_OUTPUT_REG_MRT(nr) |
408 COND(s[FS].v->writes_pos, A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z));
409
410 OUT_PKT0(ring, REG_A4XX_SP_FS_OUTPUT_REG, 1);
411 OUT_RING(ring, A4XX_SP_FS_OUTPUT_REG_MRT(nr) |
412 COND(s[FS].v->writes_pos, A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE) |
413 A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(posz_regid));
414
415 OUT_PKT0(ring, REG_A4XX_SP_FS_MRT_REG(0), 8);
416 for (i = 0; i < 8; i++) {
417 enum a4xx_color_fmt format = 0;
418 bool srgb = false;
419 if (i < nr) {
420 format = fd4_emit_format(bufs[i]);
421 if (bufs[i] && !emit->no_decode_srgb)
422 srgb = util_format_is_srgb(bufs[i]->format);
423 }
424 OUT_RING(ring, A4XX_SP_FS_MRT_REG_REGID(color_regid[i]) |
425 A4XX_SP_FS_MRT_REG_MRTFORMAT(format) |
426 COND(srgb, A4XX_SP_FS_MRT_REG_COLOR_SRGB) |
427 COND(color_regid[i] & HALF_REG_ID,
428 A4XX_SP_FS_MRT_REG_HALF_PRECISION));
429 }
430
431 if (emit->binning_pass) {
432 OUT_PKT0(ring, REG_A4XX_VPC_ATTR, 2);
433 OUT_RING(ring, A4XX_VPC_ATTR_THRDASSIGN(1) |
434 0x40000000 | /* XXX */
435 COND(s[VS].v->writes_psize, A4XX_VPC_ATTR_PSIZE));
436 OUT_RING(ring, 0x00000000);
437 } else {
438 uint32_t vinterp[8], vpsrepl[8];
439
440 memset(vinterp, 0, sizeof(vinterp));
441 memset(vpsrepl, 0, sizeof(vpsrepl));
442
443 /* looks like we need to do int varyings in the frag
444 * shader on a4xx (no flatshad reg? or a420.0 bug?):
445 *
446 * (sy)(ss)nop
447 * (sy)ldlv.u32 r0.x,l[r0.x], 1
448 * ldlv.u32 r0.y,l[r0.x+1], 1
449 * (ss)bary.f (ei)r63.x, 0, r0.x
450 * (ss)(rpt1)cov.s32f16 hr0.x, (r)r0.x
451 * (rpt5)nop
452 * sam (f16)(xyzw)hr0.x, hr0.x, s#0, t#0
453 *
454 * Possibly on later a4xx variants we'll be able to use
455 * something like the code below instead of workaround
456 * in the shader:
457 */
458 /* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
459 for (j = -1; (j = ir3_next_varying(s[FS].v, j)) < (int)s[FS].v->inputs_count; ) {
460 /* NOTE: varyings are packed, so if compmask is 0xb
461 * then first, third, and fourth component occupy
462 * three consecutive varying slots:
463 */
464 unsigned compmask = s[FS].v->inputs[j].compmask;
465
466 uint32_t inloc = s[FS].v->inputs[j].inloc;
467
468 if (s[FS].v->inputs[j].flat ||
469 (s[FS].v->inputs[j].rasterflat && emit->rasterflat)) {
470 uint32_t loc = inloc;
471
472 for (i = 0; i < 4; i++) {
473 if (compmask & (1 << i)) {
474 vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
475 //flatshade[loc / 32] |= 1 << (loc % 32);
476 loc++;
477 }
478 }
479 }
480
481 bool coord_mode = emit->sprite_coord_mode;
482 if (ir3_point_sprite(s[FS].v, j, emit->sprite_coord_enable, &coord_mode)) {
483 /* mask is two 2-bit fields, where:
484 * '01' -> S
485 * '10' -> T
486 * '11' -> 1 - T (flip mode)
487 */
488 unsigned mask = coord_mode ? 0b1101 : 0b1001;
489 uint32_t loc = inloc;
490 if (compmask & 0x1) {
491 vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
492 loc++;
493 }
494 if (compmask & 0x2) {
495 vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
496 loc++;
497 }
498 if (compmask & 0x4) {
499 /* .z <- 0.0f */
500 vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
501 loc++;
502 }
503 if (compmask & 0x8) {
504 /* .w <- 1.0f */
505 vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
506 loc++;
507 }
508 }
509 }
510
511 OUT_PKT0(ring, REG_A4XX_VPC_ATTR, 2);
512 OUT_RING(ring, A4XX_VPC_ATTR_TOTALATTR(s[FS].v->total_in) |
513 A4XX_VPC_ATTR_THRDASSIGN(1) |
514 COND(s[FS].v->total_in > 0, A4XX_VPC_ATTR_ENABLE) |
515 0x40000000 | /* XXX */
516 COND(s[VS].v->writes_psize, A4XX_VPC_ATTR_PSIZE));
517 OUT_RING(ring, A4XX_VPC_PACK_NUMFPNONPOSVAR(s[FS].v->total_in) |
518 A4XX_VPC_PACK_NUMNONPOSVSVAR(s[FS].v->total_in));
519
520 OUT_PKT0(ring, REG_A4XX_VPC_VARYING_INTERP_MODE(0), 8);
521 for (i = 0; i < 8; i++)
522 OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
523
524 OUT_PKT0(ring, REG_A4XX_VPC_VARYING_PS_REPL_MODE(0), 8);
525 for (i = 0; i < 8; i++)
526 OUT_RING(ring, vpsrepl[i]); /* VPC_VARYING_PS_REPL[i] */
527 }
528
529 if (s[VS].instrlen)
530 emit_shader(ring, s[VS].v);
531
532 if (!emit->binning_pass)
533 if (s[FS].instrlen)
534 emit_shader(ring, s[FS].v);
535 }
536
537 void
538 fd4_prog_init(struct pipe_context *pctx)
539 {
540 ir3_prog_init(pctx);
541 fd_prog_init(pctx);
542 }