2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_inlines.h"
31 #include "util/format/u_format.h"
33 #include "freedreno_program.h"
35 #include "fd4_program.h"
37 #include "fd4_texture.h"
38 #include "fd4_format.h"
41 emit_shader(struct fd_ringbuffer
*ring
, const struct ir3_shader_variant
*so
)
43 const struct ir3_info
*si
= &so
->info
;
44 enum a4xx_state_block sb
= fd4_stage2shadersb(so
->type
);
45 enum a4xx_state_src src
;
48 if (fd_mesa_debug
& FD_DBG_DIRECT
) {
51 bin
= fd_bo_map(so
->bo
);
58 OUT_PKT3(ring
, CP_LOAD_STATE4
, 2 + sz
);
59 OUT_RING(ring
, CP_LOAD_STATE4_0_DST_OFF(0) |
60 CP_LOAD_STATE4_0_STATE_SRC(src
) |
61 CP_LOAD_STATE4_0_STATE_BLOCK(sb
) |
62 CP_LOAD_STATE4_0_NUM_UNIT(so
->instrlen
));
64 OUT_RING(ring
, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
65 CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER
));
67 OUT_RELOC(ring
, so
->bo
, 0,
68 CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER
), 0);
71 /* for how clever coverity is, it is sometimes rather dull, and
72 * doesn't realize that the only case where bin==NULL, sz==0:
74 assume(bin
|| (sz
== 0));
76 for (i
= 0; i
< sz
; i
++) {
77 OUT_RING(ring
, bin
[i
]);
82 const struct ir3_shader_variant
*v
;
83 const struct ir3_info
*i
;
84 /* const sizes are in units of 4 * vec4 */
87 /* instr sizes are in units of 16 instructions */
102 setup_stages(struct fd4_emit
*emit
, struct stage
*s
)
106 s
[VS
].v
= fd4_emit_get_vp(emit
);
107 s
[FS
].v
= fd4_emit_get_fp(emit
);
109 s
[HS
].v
= s
[DS
].v
= s
[GS
].v
= NULL
; /* for now */
111 for (i
= 0; i
< MAX_STAGES
; i
++) {
113 s
[i
].i
= &s
[i
].v
->info
;
114 /* constlen is in units of 4 * vec4: */
115 assert(s
[i
].v
->constlen
% 4 == 0);
116 s
[i
].constlen
= s
[i
].v
->constlen
/ 4;
117 /* instrlen is already in units of 16 instr.. although
118 * probably we should ditch that and not make the compiler
119 * care about instruction group size of a3xx vs a4xx
121 s
[i
].instrlen
= s
[i
].v
->instrlen
;
129 /* NOTE: at least for gles2, blob partitions VS at bottom of const
130 * space and FS taking entire remaining space. We probably don't
131 * need to do that the same way, but for now mimic what the blob
132 * does to make it easier to diff against register values from blob
134 * NOTE: if VS.instrlen + FS.instrlen > 64, then one or both shaders
135 * is run from external memory.
137 if ((s
[VS
].instrlen
+ s
[FS
].instrlen
) > 64) {
138 /* prioritize FS for internal memory: */
139 if (s
[FS
].instrlen
< 64) {
140 /* if FS can fit, kick VS out to external memory: */
142 } else if (s
[VS
].instrlen
< 64) {
143 /* otherwise if VS can fit, kick out FS: */
146 /* neither can fit, run both from external memory: */
152 s
[FS
].constlen
= 128 - s
[VS
].constlen
;
155 s
[FS
].instroff
= 64 - s
[FS
].instrlen
;
156 s
[FS
].constoff
= s
[VS
].constlen
;
157 s
[HS
].instroff
= s
[DS
].instroff
= s
[GS
].instroff
= s
[FS
].instroff
;
158 s
[HS
].constoff
= s
[DS
].constoff
= s
[GS
].constoff
= s
[FS
].constoff
;
162 fd4_program_emit(struct fd_ringbuffer
*ring
, struct fd4_emit
*emit
,
163 int nr
, struct pipe_surface
**bufs
)
165 struct stage s
[MAX_STAGES
];
166 uint32_t pos_regid
, posz_regid
, psize_regid
, color_regid
[8];
167 uint32_t face_regid
, coord_regid
, zwcoord_regid
, vcoord_regid
, lcoord_regid
;
168 enum a3xx_threadsize fssz
;
172 debug_assert(nr
<= ARRAY_SIZE(color_regid
));
174 if (emit
->binning_pass
)
177 setup_stages(emit
, s
);
179 fssz
= (s
[FS
].i
->max_reg
>= 24) ? TWO_QUADS
: FOUR_QUADS
;
181 /* blob seems to always use constmode currently: */
184 pos_regid
= ir3_find_output_regid(s
[VS
].v
, VARYING_SLOT_POS
);
185 if (pos_regid
== regid(63, 0)) {
186 /* hw dislikes when there is no position output, which can
187 * happen for transform-feedback vertex shaders. Just tell
188 * the hw to use r0.x, with whatever random value is there:
190 pos_regid
= regid(0, 0);
192 posz_regid
= ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DEPTH
);
193 psize_regid
= ir3_find_output_regid(s
[VS
].v
, VARYING_SLOT_PSIZ
);
194 if (s
[FS
].v
->color0_mrt
) {
195 color_regid
[0] = color_regid
[1] = color_regid
[2] = color_regid
[3] =
196 color_regid
[4] = color_regid
[5] = color_regid
[6] = color_regid
[7] =
197 ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_COLOR
);
199 color_regid
[0] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA0
);
200 color_regid
[1] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA1
);
201 color_regid
[2] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA2
);
202 color_regid
[3] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA3
);
203 color_regid
[4] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA4
);
204 color_regid
[5] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA5
);
205 color_regid
[6] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA6
);
206 color_regid
[7] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA7
);
209 face_regid
= ir3_find_sysval_regid(s
[FS
].v
, SYSTEM_VALUE_FRONT_FACE
);
210 coord_regid
= ir3_find_sysval_regid(s
[FS
].v
, SYSTEM_VALUE_FRAG_COORD
);
211 zwcoord_regid
= (coord_regid
== regid(63,0)) ? regid(63,0) : (coord_regid
+ 2);
212 vcoord_regid
= ir3_find_sysval_regid(s
[FS
].v
, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL
);
213 lcoord_regid
= ir3_find_sysval_regid(s
[FS
].v
, SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL
);
215 /* XXX since we don't know how to support noperspective varyings on a4xx,
216 * use this little hack to support u_blitter, which should be the only
217 * case with noperspective varyings on a4xx:
219 if (VALIDREG(lcoord_regid
)) {
220 assert(!VALIDREG(vcoord_regid
));
221 vcoord_regid
= lcoord_regid
;
224 /* we could probably divide this up into things that need to be
225 * emitted if frag-prog is dirty vs if vert-prog is dirty..
228 OUT_PKT0(ring
, REG_A4XX_HLSQ_UPDATE_CONTROL
, 1);
229 OUT_RING(ring
, 0x00000003);
231 OUT_PKT0(ring
, REG_A4XX_HLSQ_CONTROL_0_REG
, 5);
232 OUT_RING(ring
, A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(fssz
) |
233 A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(constmode
) |
234 A4XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE
|
235 /* NOTE: I guess SHADERRESTART and CONSTFULLUPDATE maybe
236 * flush some caches? I think we only need to set those
237 * bits if we have updated const or shader..
239 A4XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART
|
240 A4XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE
);
241 OUT_RING(ring
, A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS
) |
242 A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE
|
243 A4XX_HLSQ_CONTROL_1_REG_COORDREGID(coord_regid
) |
244 A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID(zwcoord_regid
));
245 OUT_RING(ring
, A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(63) |
246 0x3f3f000 | /* XXX */
247 A4XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid
));
248 OUT_RING(ring
, A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(vcoord_regid
) |
250 OUT_RING(ring
, 0x00fcfcfc); /* XXX HLSQ_CONTROL_4 */
252 OUT_PKT0(ring
, REG_A4XX_HLSQ_VS_CONTROL_REG
, 5);
253 OUT_RING(ring
, A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(s
[VS
].constlen
) |
254 A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(s
[VS
].constoff
) |
255 A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(s
[VS
].instrlen
) |
256 A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(s
[VS
].instroff
));
257 OUT_RING(ring
, A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(s
[FS
].constlen
) |
258 A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(s
[FS
].constoff
) |
259 A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(s
[FS
].instrlen
) |
260 A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(s
[FS
].instroff
));
261 OUT_RING(ring
, A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(s
[HS
].constlen
) |
262 A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(s
[HS
].constoff
) |
263 A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(s
[HS
].instrlen
) |
264 A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(s
[HS
].instroff
));
265 OUT_RING(ring
, A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(s
[DS
].constlen
) |
266 A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(s
[DS
].constoff
) |
267 A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(s
[DS
].instrlen
) |
268 A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(s
[DS
].instroff
));
269 OUT_RING(ring
, A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(s
[GS
].constlen
) |
270 A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(s
[GS
].constoff
) |
271 A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(s
[GS
].instrlen
) |
272 A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(s
[GS
].instroff
));
274 OUT_PKT0(ring
, REG_A4XX_SP_SP_CTRL_REG
, 1);
275 OUT_RING(ring
, 0x140010 | /* XXX */
276 COND(emit
->binning_pass
, A4XX_SP_SP_CTRL_REG_BINNING_PASS
));
278 OUT_PKT0(ring
, REG_A4XX_SP_INSTR_CACHE_CTRL
, 1);
279 OUT_RING(ring
, 0x7f | /* XXX */
280 COND(s
[VS
].instrlen
, A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER
) |
281 COND(s
[FS
].instrlen
, A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER
) |
282 COND(s
[VS
].instrlen
&& s
[FS
].instrlen
,
283 A4XX_SP_INSTR_CACHE_CTRL_INSTR_BUFFER
));
285 OUT_PKT0(ring
, REG_A4XX_SP_VS_LENGTH_REG
, 1);
286 OUT_RING(ring
, s
[VS
].v
->instrlen
); /* SP_VS_LENGTH_REG */
288 OUT_PKT0(ring
, REG_A4XX_SP_VS_CTRL_REG0
, 3);
289 OUT_RING(ring
, A4XX_SP_VS_CTRL_REG0_THREADMODE(MULTI
) |
290 A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(s
[VS
].i
->max_half_reg
+ 1) |
291 A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(s
[VS
].i
->max_reg
+ 1) |
292 A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(0) |
293 A4XX_SP_VS_CTRL_REG0_THREADSIZE(TWO_QUADS
) |
294 A4XX_SP_VS_CTRL_REG0_SUPERTHREADMODE
|
295 COND(s
[VS
].v
->need_pixlod
, A4XX_SP_VS_CTRL_REG0_PIXLODENABLE
));
296 OUT_RING(ring
, A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(s
[VS
].constlen
) |
297 A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(s
[VS
].v
->total_in
));
298 OUT_RING(ring
, A4XX_SP_VS_PARAM_REG_POSREGID(pos_regid
) |
299 A4XX_SP_VS_PARAM_REG_PSIZEREGID(psize_regid
) |
300 A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(s
[FS
].v
->varying_in
));
302 struct ir3_shader_linkage l
= {0};
303 ir3_link_shaders(&l
, s
[VS
].v
, s
[FS
].v
, false);
305 for (i
= 0, j
= 0; (i
< 16) && (j
< l
.cnt
); i
++) {
308 OUT_PKT0(ring
, REG_A4XX_SP_VS_OUT_REG(i
), 1);
310 reg
|= A4XX_SP_VS_OUT_REG_A_REGID(l
.var
[j
].regid
);
311 reg
|= A4XX_SP_VS_OUT_REG_A_COMPMASK(l
.var
[j
].compmask
);
314 reg
|= A4XX_SP_VS_OUT_REG_B_REGID(l
.var
[j
].regid
);
315 reg
|= A4XX_SP_VS_OUT_REG_B_COMPMASK(l
.var
[j
].compmask
);
321 for (i
= 0, j
= 0; (i
< 8) && (j
< l
.cnt
); i
++) {
324 OUT_PKT0(ring
, REG_A4XX_SP_VS_VPC_DST_REG(i
), 1);
326 reg
|= A4XX_SP_VS_VPC_DST_REG_OUTLOC0(l
.var
[j
++].loc
+ 8);
327 reg
|= A4XX_SP_VS_VPC_DST_REG_OUTLOC1(l
.var
[j
++].loc
+ 8);
328 reg
|= A4XX_SP_VS_VPC_DST_REG_OUTLOC2(l
.var
[j
++].loc
+ 8);
329 reg
|= A4XX_SP_VS_VPC_DST_REG_OUTLOC3(l
.var
[j
++].loc
+ 8);
334 OUT_PKT0(ring
, REG_A4XX_SP_VS_OBJ_OFFSET_REG
, 2);
335 OUT_RING(ring
, A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s
[VS
].constoff
) |
336 A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s
[VS
].instroff
));
337 OUT_RELOC(ring
, s
[VS
].v
->bo
, 0, 0, 0); /* SP_VS_OBJ_START_REG */
339 if (emit
->binning_pass
) {
340 OUT_PKT0(ring
, REG_A4XX_SP_FS_LENGTH_REG
, 1);
341 OUT_RING(ring
, 0x00000000); /* SP_FS_LENGTH_REG */
343 OUT_PKT0(ring
, REG_A4XX_SP_FS_CTRL_REG0
, 2);
344 OUT_RING(ring
, A4XX_SP_FS_CTRL_REG0_THREADMODE(MULTI
) |
345 COND(s
[FS
].v
->total_in
> 0, A4XX_SP_FS_CTRL_REG0_VARYING
) |
346 A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(0) |
347 A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(0) |
348 A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(1) |
349 A4XX_SP_FS_CTRL_REG0_THREADSIZE(fssz
) |
350 A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE
);
351 OUT_RING(ring
, A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(s
[FS
].constlen
) |
354 OUT_PKT0(ring
, REG_A4XX_SP_FS_OBJ_OFFSET_REG
, 2);
355 OUT_RING(ring
, A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s
[FS
].constoff
) |
356 A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s
[FS
].instroff
));
357 OUT_RING(ring
, 0x00000000);
359 OUT_PKT0(ring
, REG_A4XX_SP_FS_LENGTH_REG
, 1);
360 OUT_RING(ring
, s
[FS
].v
->instrlen
); /* SP_FS_LENGTH_REG */
362 OUT_PKT0(ring
, REG_A4XX_SP_FS_CTRL_REG0
, 2);
363 OUT_RING(ring
, A4XX_SP_FS_CTRL_REG0_THREADMODE(MULTI
) |
364 COND(s
[FS
].v
->total_in
> 0, A4XX_SP_FS_CTRL_REG0_VARYING
) |
365 A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(s
[FS
].i
->max_half_reg
+ 1) |
366 A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s
[FS
].i
->max_reg
+ 1) |
367 A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(1) |
368 A4XX_SP_FS_CTRL_REG0_THREADSIZE(fssz
) |
369 A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE
|
370 COND(s
[FS
].v
->need_pixlod
, A4XX_SP_FS_CTRL_REG0_PIXLODENABLE
));
371 OUT_RING(ring
, A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(s
[FS
].constlen
) |
372 0x80000000 | /* XXX */
373 COND(s
[FS
].v
->frag_face
, A4XX_SP_FS_CTRL_REG1_FACENESS
) |
374 COND(s
[FS
].v
->total_in
> 0, A4XX_SP_FS_CTRL_REG1_VARYING
) |
375 COND(s
[FS
].v
->fragcoord_compmask
!= 0, A4XX_SP_FS_CTRL_REG1_FRAGCOORD
));
377 OUT_PKT0(ring
, REG_A4XX_SP_FS_OBJ_OFFSET_REG
, 2);
378 OUT_RING(ring
, A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s
[FS
].constoff
) |
379 A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s
[FS
].instroff
));
380 OUT_RELOC(ring
, s
[FS
].v
->bo
, 0, 0, 0); /* SP_FS_OBJ_START_REG */
383 OUT_PKT0(ring
, REG_A4XX_SP_HS_OBJ_OFFSET_REG
, 1);
384 OUT_RING(ring
, A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s
[HS
].constoff
) |
385 A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s
[HS
].instroff
));
387 OUT_PKT0(ring
, REG_A4XX_SP_DS_OBJ_OFFSET_REG
, 1);
388 OUT_RING(ring
, A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s
[DS
].constoff
) |
389 A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s
[DS
].instroff
));
391 OUT_PKT0(ring
, REG_A4XX_SP_GS_OBJ_OFFSET_REG
, 1);
392 OUT_RING(ring
, A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s
[GS
].constoff
) |
393 A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s
[GS
].instroff
));
395 OUT_PKT0(ring
, REG_A4XX_RB_RENDER_CONTROL2
, 1);
396 OUT_RING(ring
, A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(0) |
397 COND(s
[FS
].v
->total_in
> 0, A4XX_RB_RENDER_CONTROL2_VARYING
) |
398 COND(s
[FS
].v
->frag_face
, A4XX_RB_RENDER_CONTROL2_FACENESS
) |
399 COND(s
[FS
].v
->fragcoord_compmask
!= 0,
400 A4XX_RB_RENDER_CONTROL2_COORD_MASK(s
[FS
].v
->fragcoord_compmask
)));
402 OUT_PKT0(ring
, REG_A4XX_RB_FS_OUTPUT_REG
, 1);
403 OUT_RING(ring
, A4XX_RB_FS_OUTPUT_REG_MRT(nr
) |
404 COND(s
[FS
].v
->writes_pos
, A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z
));
406 OUT_PKT0(ring
, REG_A4XX_SP_FS_OUTPUT_REG
, 1);
407 OUT_RING(ring
, A4XX_SP_FS_OUTPUT_REG_MRT(nr
) |
408 COND(s
[FS
].v
->writes_pos
, A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE
) |
409 A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(posz_regid
));
411 OUT_PKT0(ring
, REG_A4XX_SP_FS_MRT_REG(0), 8);
412 for (i
= 0; i
< 8; i
++) {
413 enum a4xx_color_fmt format
= 0;
416 format
= fd4_emit_format(bufs
[i
]);
417 if (bufs
[i
] && !emit
->no_decode_srgb
)
418 srgb
= util_format_is_srgb(bufs
[i
]->format
);
420 OUT_RING(ring
, A4XX_SP_FS_MRT_REG_REGID(color_regid
[i
]) |
421 A4XX_SP_FS_MRT_REG_MRTFORMAT(format
) |
422 COND(srgb
, A4XX_SP_FS_MRT_REG_COLOR_SRGB
) |
423 COND(color_regid
[i
] & HALF_REG_ID
,
424 A4XX_SP_FS_MRT_REG_HALF_PRECISION
));
427 if (emit
->binning_pass
) {
428 OUT_PKT0(ring
, REG_A4XX_VPC_ATTR
, 2);
429 OUT_RING(ring
, A4XX_VPC_ATTR_THRDASSIGN(1) |
430 0x40000000 | /* XXX */
431 COND(s
[VS
].v
->writes_psize
, A4XX_VPC_ATTR_PSIZE
));
432 OUT_RING(ring
, 0x00000000);
434 uint32_t vinterp
[8], vpsrepl
[8];
436 memset(vinterp
, 0, sizeof(vinterp
));
437 memset(vpsrepl
, 0, sizeof(vpsrepl
));
439 /* looks like we need to do int varyings in the frag
440 * shader on a4xx (no flatshad reg? or a420.0 bug?):
443 * (sy)ldlv.u32 r0.x,l[r0.x], 1
444 * ldlv.u32 r0.y,l[r0.x+1], 1
445 * (ss)bary.f (ei)r63.x, 0, r0.x
446 * (ss)(rpt1)cov.s32f16 hr0.x, (r)r0.x
448 * sam (f16)(xyzw)hr0.x, hr0.x, s#0, t#0
450 * Possibly on later a4xx variants we'll be able to use
451 * something like the code below instead of workaround
454 /* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
455 for (j
= -1; (j
= ir3_next_varying(s
[FS
].v
, j
)) < (int)s
[FS
].v
->inputs_count
; ) {
456 /* NOTE: varyings are packed, so if compmask is 0xb
457 * then first, third, and fourth component occupy
458 * three consecutive varying slots:
460 unsigned compmask
= s
[FS
].v
->inputs
[j
].compmask
;
462 uint32_t inloc
= s
[FS
].v
->inputs
[j
].inloc
;
464 if ((s
[FS
].v
->inputs
[j
].interpolate
== INTERP_MODE_FLAT
) ||
465 (s
[FS
].v
->inputs
[j
].rasterflat
&& emit
->rasterflat
)) {
466 uint32_t loc
= inloc
;
468 for (i
= 0; i
< 4; i
++) {
469 if (compmask
& (1 << i
)) {
470 vinterp
[loc
/ 16] |= 1 << ((loc
% 16) * 2);
471 //flatshade[loc / 32] |= 1 << (loc % 32);
477 bool coord_mode
= emit
->sprite_coord_mode
;
478 if (ir3_point_sprite(s
[FS
].v
, j
, emit
->sprite_coord_enable
, &coord_mode
)) {
479 /* mask is two 2-bit fields, where:
482 * '11' -> 1 - T (flip mode)
484 unsigned mask
= coord_mode
? 0b1101 : 0b1001;
485 uint32_t loc
= inloc
;
486 if (compmask
& 0x1) {
487 vpsrepl
[loc
/ 16] |= ((mask
>> 0) & 0x3) << ((loc
% 16) * 2);
490 if (compmask
& 0x2) {
491 vpsrepl
[loc
/ 16] |= ((mask
>> 2) & 0x3) << ((loc
% 16) * 2);
494 if (compmask
& 0x4) {
496 vinterp
[loc
/ 16] |= 0b10 << ((loc
% 16) * 2);
499 if (compmask
& 0x8) {
501 vinterp
[loc
/ 16] |= 0b11 << ((loc
% 16) * 2);
507 OUT_PKT0(ring
, REG_A4XX_VPC_ATTR
, 2);
508 OUT_RING(ring
, A4XX_VPC_ATTR_TOTALATTR(s
[FS
].v
->total_in
) |
509 A4XX_VPC_ATTR_THRDASSIGN(1) |
510 COND(s
[FS
].v
->total_in
> 0, A4XX_VPC_ATTR_ENABLE
) |
511 0x40000000 | /* XXX */
512 COND(s
[VS
].v
->writes_psize
, A4XX_VPC_ATTR_PSIZE
));
513 OUT_RING(ring
, A4XX_VPC_PACK_NUMFPNONPOSVAR(s
[FS
].v
->total_in
) |
514 A4XX_VPC_PACK_NUMNONPOSVSVAR(s
[FS
].v
->total_in
));
516 OUT_PKT0(ring
, REG_A4XX_VPC_VARYING_INTERP_MODE(0), 8);
517 for (i
= 0; i
< 8; i
++)
518 OUT_RING(ring
, vinterp
[i
]); /* VPC_VARYING_INTERP[i].MODE */
520 OUT_PKT0(ring
, REG_A4XX_VPC_VARYING_PS_REPL_MODE(0), 8);
521 for (i
= 0; i
< 8; i
++)
522 OUT_RING(ring
, vpsrepl
[i
]); /* VPC_VARYING_PS_REPL[i] */
526 emit_shader(ring
, s
[VS
].v
);
528 if (!emit
->binning_pass
)
530 emit_shader(ring
, s
[FS
].v
);
534 fd4_prog_init(struct pipe_context
*pctx
)