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util: Move gallium's PIPE_FORMAT utils to /util/format/
[mesa.git] / src / gallium / drivers / freedreno / a4xx / fd4_program.c
1 /*
2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_inlines.h"
31 #include "util/format/u_format.h"
32
33 #include "freedreno_program.h"
34
35 #include "fd4_program.h"
36 #include "fd4_emit.h"
37 #include "fd4_texture.h"
38 #include "fd4_format.h"
39
40 static void
41 emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
42 {
43 const struct ir3_info *si = &so->info;
44 enum a4xx_state_block sb = fd4_stage2shadersb(so->type);
45 enum a4xx_state_src src;
46 uint32_t i, sz, *bin;
47
48 if (fd_mesa_debug & FD_DBG_DIRECT) {
49 sz = si->sizedwords;
50 src = SS4_DIRECT;
51 bin = fd_bo_map(so->bo);
52 } else {
53 sz = 0;
54 src = SS4_INDIRECT;
55 bin = NULL;
56 }
57
58 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + sz);
59 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
60 CP_LOAD_STATE4_0_STATE_SRC(src) |
61 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
62 CP_LOAD_STATE4_0_NUM_UNIT(so->instrlen));
63 if (bin) {
64 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
65 CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER));
66 } else {
67 OUT_RELOCD(ring, so->bo, 0,
68 CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER), 0);
69 }
70
71 /* for how clever coverity is, it is sometimes rather dull, and
72 * doesn't realize that the only case where bin==NULL, sz==0:
73 */
74 assume(bin || (sz == 0));
75
76 for (i = 0; i < sz; i++) {
77 OUT_RING(ring, bin[i]);
78 }
79 }
80
81 struct stage {
82 const struct ir3_shader_variant *v;
83 const struct ir3_info *i;
84 /* const sizes are in units of 4 * vec4 */
85 uint8_t constoff;
86 uint8_t constlen;
87 /* instr sizes are in units of 16 instructions */
88 uint8_t instroff;
89 uint8_t instrlen;
90 };
91
92 enum {
93 VS = 0,
94 FS = 1,
95 HS = 2,
96 DS = 3,
97 GS = 4,
98 MAX_STAGES
99 };
100
101 static void
102 setup_stages(struct fd4_emit *emit, struct stage *s)
103 {
104 unsigned i;
105
106 s[VS].v = fd4_emit_get_vp(emit);
107 s[FS].v = fd4_emit_get_fp(emit);
108
109 s[HS].v = s[DS].v = s[GS].v = NULL; /* for now */
110
111 for (i = 0; i < MAX_STAGES; i++) {
112 if (s[i].v) {
113 s[i].i = &s[i].v->info;
114 /* constlen is in units of 4 * vec4: */
115 s[i].constlen = align(s[i].v->constlen, 4) / 4;
116 /* instrlen is already in units of 16 instr.. although
117 * probably we should ditch that and not make the compiler
118 * care about instruction group size of a3xx vs a4xx
119 */
120 s[i].instrlen = s[i].v->instrlen;
121 } else {
122 s[i].i = NULL;
123 s[i].constlen = 0;
124 s[i].instrlen = 0;
125 }
126 }
127
128 /* NOTE: at least for gles2, blob partitions VS at bottom of const
129 * space and FS taking entire remaining space. We probably don't
130 * need to do that the same way, but for now mimic what the blob
131 * does to make it easier to diff against register values from blob
132 *
133 * NOTE: if VS.instrlen + FS.instrlen > 64, then one or both shaders
134 * is run from external memory.
135 */
136 if ((s[VS].instrlen + s[FS].instrlen) > 64) {
137 /* prioritize FS for internal memory: */
138 if (s[FS].instrlen < 64) {
139 /* if FS can fit, kick VS out to external memory: */
140 s[VS].instrlen = 0;
141 } else if (s[VS].instrlen < 64) {
142 /* otherwise if VS can fit, kick out FS: */
143 s[FS].instrlen = 0;
144 } else {
145 /* neither can fit, run both from external memory: */
146 s[VS].instrlen = 0;
147 s[FS].instrlen = 0;
148 }
149 }
150 s[VS].constlen = 66;
151 s[FS].constlen = 128 - s[VS].constlen;
152 s[VS].instroff = 0;
153 s[VS].constoff = 0;
154 s[FS].instroff = 64 - s[FS].instrlen;
155 s[FS].constoff = s[VS].constlen;
156 s[HS].instroff = s[DS].instroff = s[GS].instroff = s[FS].instroff;
157 s[HS].constoff = s[DS].constoff = s[GS].constoff = s[FS].constoff;
158 }
159
160 void
161 fd4_program_emit(struct fd_ringbuffer *ring, struct fd4_emit *emit,
162 int nr, struct pipe_surface **bufs)
163 {
164 struct stage s[MAX_STAGES];
165 uint32_t pos_regid, posz_regid, psize_regid, color_regid[8];
166 uint32_t face_regid, coord_regid, zwcoord_regid, vcoord_regid;
167 enum a3xx_threadsize fssz;
168 int constmode;
169 int i, j;
170
171 debug_assert(nr <= ARRAY_SIZE(color_regid));
172
173 if (emit->binning_pass)
174 nr = 0;
175
176 setup_stages(emit, s);
177
178 fssz = (s[FS].i->max_reg >= 24) ? TWO_QUADS : FOUR_QUADS;
179
180 /* blob seems to always use constmode currently: */
181 constmode = 1;
182
183 pos_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_POS);
184 if (pos_regid == regid(63, 0)) {
185 /* hw dislikes when there is no position output, which can
186 * happen for transform-feedback vertex shaders. Just tell
187 * the hw to use r0.x, with whatever random value is there:
188 */
189 pos_regid = regid(0, 0);
190 }
191 posz_regid = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DEPTH);
192 psize_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_PSIZ);
193 if (s[FS].v->color0_mrt) {
194 color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
195 color_regid[4] = color_regid[5] = color_regid[6] = color_regid[7] =
196 ir3_find_output_regid(s[FS].v, FRAG_RESULT_COLOR);
197 } else {
198 color_regid[0] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA0);
199 color_regid[1] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA1);
200 color_regid[2] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA2);
201 color_regid[3] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA3);
202 color_regid[4] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA4);
203 color_regid[5] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA5);
204 color_regid[6] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA6);
205 color_regid[7] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA7);
206 }
207
208 face_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_FRONT_FACE);
209 coord_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_FRAG_COORD);
210 zwcoord_regid = (coord_regid == regid(63,0)) ? regid(63,0) : (coord_regid + 2);
211 vcoord_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_BARYCENTRIC_PIXEL);
212
213 /* we could probably divide this up into things that need to be
214 * emitted if frag-prog is dirty vs if vert-prog is dirty..
215 */
216
217 OUT_PKT0(ring, REG_A4XX_HLSQ_UPDATE_CONTROL, 1);
218 OUT_RING(ring, 0x00000003);
219
220 OUT_PKT0(ring, REG_A4XX_HLSQ_CONTROL_0_REG, 5);
221 OUT_RING(ring, A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(fssz) |
222 A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(constmode) |
223 A4XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE |
224 /* NOTE: I guess SHADERRESTART and CONSTFULLUPDATE maybe
225 * flush some caches? I think we only need to set those
226 * bits if we have updated const or shader..
227 */
228 A4XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART |
229 A4XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE);
230 OUT_RING(ring, A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
231 A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE |
232 A4XX_HLSQ_CONTROL_1_REG_COORDREGID(coord_regid) |
233 A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID(zwcoord_regid));
234 OUT_RING(ring, A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(63) |
235 0x3f3f000 | /* XXX */
236 A4XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid));
237 OUT_RING(ring, A4XX_HLSQ_CONTROL_3_REG_REGID(vcoord_regid) |
238 0xfcfcfc00);
239 OUT_RING(ring, 0x00fcfcfc); /* XXX HLSQ_CONTROL_4 */
240
241 OUT_PKT0(ring, REG_A4XX_HLSQ_VS_CONTROL_REG, 5);
242 OUT_RING(ring, A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(s[VS].constlen) |
243 A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(s[VS].constoff) |
244 A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(s[VS].instrlen) |
245 A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(s[VS].instroff));
246 OUT_RING(ring, A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(s[FS].constlen) |
247 A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(s[FS].constoff) |
248 A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(s[FS].instrlen) |
249 A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(s[FS].instroff));
250 OUT_RING(ring, A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(s[HS].constlen) |
251 A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(s[HS].constoff) |
252 A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(s[HS].instrlen) |
253 A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(s[HS].instroff));
254 OUT_RING(ring, A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(s[DS].constlen) |
255 A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(s[DS].constoff) |
256 A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(s[DS].instrlen) |
257 A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(s[DS].instroff));
258 OUT_RING(ring, A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(s[GS].constlen) |
259 A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(s[GS].constoff) |
260 A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(s[GS].instrlen) |
261 A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(s[GS].instroff));
262
263 OUT_PKT0(ring, REG_A4XX_SP_SP_CTRL_REG, 1);
264 OUT_RING(ring, 0x140010 | /* XXX */
265 COND(emit->binning_pass, A4XX_SP_SP_CTRL_REG_BINNING_PASS));
266
267 OUT_PKT0(ring, REG_A4XX_SP_INSTR_CACHE_CTRL, 1);
268 OUT_RING(ring, 0x7f | /* XXX */
269 COND(s[VS].instrlen, A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER) |
270 COND(s[FS].instrlen, A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER) |
271 COND(s[VS].instrlen && s[FS].instrlen,
272 A4XX_SP_INSTR_CACHE_CTRL_INSTR_BUFFER));
273
274 OUT_PKT0(ring, REG_A4XX_SP_VS_LENGTH_REG, 1);
275 OUT_RING(ring, s[VS].v->instrlen); /* SP_VS_LENGTH_REG */
276
277 OUT_PKT0(ring, REG_A4XX_SP_VS_CTRL_REG0, 3);
278 OUT_RING(ring, A4XX_SP_VS_CTRL_REG0_THREADMODE(MULTI) |
279 A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(s[VS].i->max_half_reg + 1) |
280 A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(s[VS].i->max_reg + 1) |
281 A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(0) |
282 A4XX_SP_VS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
283 A4XX_SP_VS_CTRL_REG0_SUPERTHREADMODE |
284 COND(s[VS].v->num_samp > 0, A4XX_SP_VS_CTRL_REG0_PIXLODENABLE));
285 OUT_RING(ring, A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(s[VS].constlen) |
286 A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(s[VS].v->total_in));
287 OUT_RING(ring, A4XX_SP_VS_PARAM_REG_POSREGID(pos_regid) |
288 A4XX_SP_VS_PARAM_REG_PSIZEREGID(psize_regid) |
289 A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(s[FS].v->varying_in));
290
291 struct ir3_shader_linkage l = {0};
292 ir3_link_shaders(&l, s[VS].v, s[FS].v);
293
294 for (i = 0, j = 0; (i < 16) && (j < l.cnt); i++) {
295 uint32_t reg = 0;
296
297 OUT_PKT0(ring, REG_A4XX_SP_VS_OUT_REG(i), 1);
298
299 reg |= A4XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid);
300 reg |= A4XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask);
301 j++;
302
303 reg |= A4XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid);
304 reg |= A4XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask);
305 j++;
306
307 OUT_RING(ring, reg);
308 }
309
310 for (i = 0, j = 0; (i < 8) && (j < l.cnt); i++) {
311 uint32_t reg = 0;
312
313 OUT_PKT0(ring, REG_A4XX_SP_VS_VPC_DST_REG(i), 1);
314
315 reg |= A4XX_SP_VS_VPC_DST_REG_OUTLOC0(l.var[j++].loc + 8);
316 reg |= A4XX_SP_VS_VPC_DST_REG_OUTLOC1(l.var[j++].loc + 8);
317 reg |= A4XX_SP_VS_VPC_DST_REG_OUTLOC2(l.var[j++].loc + 8);
318 reg |= A4XX_SP_VS_VPC_DST_REG_OUTLOC3(l.var[j++].loc + 8);
319
320 OUT_RING(ring, reg);
321 }
322
323 OUT_PKT0(ring, REG_A4XX_SP_VS_OBJ_OFFSET_REG, 2);
324 OUT_RING(ring, A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[VS].constoff) |
325 A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[VS].instroff));
326 OUT_RELOC(ring, s[VS].v->bo, 0, 0, 0); /* SP_VS_OBJ_START_REG */
327
328 if (emit->binning_pass) {
329 OUT_PKT0(ring, REG_A4XX_SP_FS_LENGTH_REG, 1);
330 OUT_RING(ring, 0x00000000); /* SP_FS_LENGTH_REG */
331
332 OUT_PKT0(ring, REG_A4XX_SP_FS_CTRL_REG0, 2);
333 OUT_RING(ring, A4XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
334 COND(s[FS].v->total_in > 0, A4XX_SP_FS_CTRL_REG0_VARYING) |
335 A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(0) |
336 A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(0) |
337 A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(1) |
338 A4XX_SP_FS_CTRL_REG0_THREADSIZE(fssz) |
339 A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE);
340 OUT_RING(ring, A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(s[FS].constlen) |
341 0x80000000);
342
343 OUT_PKT0(ring, REG_A4XX_SP_FS_OBJ_OFFSET_REG, 2);
344 OUT_RING(ring, A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[FS].constoff) |
345 A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[FS].instroff));
346 OUT_RING(ring, 0x00000000);
347 } else {
348 OUT_PKT0(ring, REG_A4XX_SP_FS_LENGTH_REG, 1);
349 OUT_RING(ring, s[FS].v->instrlen); /* SP_FS_LENGTH_REG */
350
351 OUT_PKT0(ring, REG_A4XX_SP_FS_CTRL_REG0, 2);
352 OUT_RING(ring, A4XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
353 COND(s[FS].v->total_in > 0, A4XX_SP_FS_CTRL_REG0_VARYING) |
354 A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(s[FS].i->max_half_reg + 1) |
355 A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s[FS].i->max_reg + 1) |
356 A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(1) |
357 A4XX_SP_FS_CTRL_REG0_THREADSIZE(fssz) |
358 A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE |
359 COND(s[FS].v->num_samp > 0, A4XX_SP_FS_CTRL_REG0_PIXLODENABLE));
360 OUT_RING(ring, A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(s[FS].constlen) |
361 0x80000000 | /* XXX */
362 COND(s[FS].v->frag_face, A4XX_SP_FS_CTRL_REG1_FACENESS) |
363 COND(s[FS].v->total_in > 0, A4XX_SP_FS_CTRL_REG1_VARYING) |
364 COND(s[FS].v->frag_coord, A4XX_SP_FS_CTRL_REG1_FRAGCOORD));
365
366 OUT_PKT0(ring, REG_A4XX_SP_FS_OBJ_OFFSET_REG, 2);
367 OUT_RING(ring, A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[FS].constoff) |
368 A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[FS].instroff));
369 OUT_RELOC(ring, s[FS].v->bo, 0, 0, 0); /* SP_FS_OBJ_START_REG */
370 }
371
372 OUT_PKT0(ring, REG_A4XX_SP_HS_OBJ_OFFSET_REG, 1);
373 OUT_RING(ring, A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[HS].constoff) |
374 A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[HS].instroff));
375
376 OUT_PKT0(ring, REG_A4XX_SP_DS_OBJ_OFFSET_REG, 1);
377 OUT_RING(ring, A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[DS].constoff) |
378 A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[DS].instroff));
379
380 OUT_PKT0(ring, REG_A4XX_SP_GS_OBJ_OFFSET_REG, 1);
381 OUT_RING(ring, A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[GS].constoff) |
382 A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[GS].instroff));
383
384 OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL2, 1);
385 OUT_RING(ring, A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(0) |
386 COND(s[FS].v->total_in > 0, A4XX_RB_RENDER_CONTROL2_VARYING) |
387 COND(s[FS].v->frag_face, A4XX_RB_RENDER_CONTROL2_FACENESS) |
388 COND(s[FS].v->frag_coord, A4XX_RB_RENDER_CONTROL2_XCOORD |
389 A4XX_RB_RENDER_CONTROL2_YCOORD |
390 A4XX_RB_RENDER_CONTROL2_ZCOORD |
391 A4XX_RB_RENDER_CONTROL2_WCOORD));
392
393 OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT_REG, 1);
394 OUT_RING(ring, A4XX_RB_FS_OUTPUT_REG_MRT(nr) |
395 COND(s[FS].v->writes_pos, A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z));
396
397 OUT_PKT0(ring, REG_A4XX_SP_FS_OUTPUT_REG, 1);
398 OUT_RING(ring, A4XX_SP_FS_OUTPUT_REG_MRT(nr) |
399 COND(s[FS].v->writes_pos, A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE) |
400 A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(posz_regid));
401
402 OUT_PKT0(ring, REG_A4XX_SP_FS_MRT_REG(0), 8);
403 for (i = 0; i < 8; i++) {
404 enum a4xx_color_fmt format = 0;
405 bool srgb = false;
406 if (i < nr) {
407 format = fd4_emit_format(bufs[i]);
408 if (bufs[i] && !emit->no_decode_srgb)
409 srgb = util_format_is_srgb(bufs[i]->format);
410 }
411 OUT_RING(ring, A4XX_SP_FS_MRT_REG_REGID(color_regid[i]) |
412 A4XX_SP_FS_MRT_REG_MRTFORMAT(format) |
413 COND(srgb, A4XX_SP_FS_MRT_REG_COLOR_SRGB) |
414 COND(color_regid[i] & HALF_REG_ID,
415 A4XX_SP_FS_MRT_REG_HALF_PRECISION));
416 }
417
418 if (emit->binning_pass) {
419 OUT_PKT0(ring, REG_A4XX_VPC_ATTR, 2);
420 OUT_RING(ring, A4XX_VPC_ATTR_THRDASSIGN(1) |
421 0x40000000 | /* XXX */
422 COND(s[VS].v->writes_psize, A4XX_VPC_ATTR_PSIZE));
423 OUT_RING(ring, 0x00000000);
424 } else {
425 uint32_t vinterp[8], vpsrepl[8];
426
427 memset(vinterp, 0, sizeof(vinterp));
428 memset(vpsrepl, 0, sizeof(vpsrepl));
429
430 /* looks like we need to do int varyings in the frag
431 * shader on a4xx (no flatshad reg? or a420.0 bug?):
432 *
433 * (sy)(ss)nop
434 * (sy)ldlv.u32 r0.x,l[r0.x], 1
435 * ldlv.u32 r0.y,l[r0.x+1], 1
436 * (ss)bary.f (ei)r63.x, 0, r0.x
437 * (ss)(rpt1)cov.s32f16 hr0.x, (r)r0.x
438 * (rpt5)nop
439 * sam (f16)(xyzw)hr0.x, hr0.x, s#0, t#0
440 *
441 * Possibly on later a4xx variants we'll be able to use
442 * something like the code below instead of workaround
443 * in the shader:
444 */
445 /* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
446 for (j = -1; (j = ir3_next_varying(s[FS].v, j)) < (int)s[FS].v->inputs_count; ) {
447 /* NOTE: varyings are packed, so if compmask is 0xb
448 * then first, third, and fourth component occupy
449 * three consecutive varying slots:
450 */
451 unsigned compmask = s[FS].v->inputs[j].compmask;
452
453 uint32_t inloc = s[FS].v->inputs[j].inloc;
454
455 if ((s[FS].v->inputs[j].interpolate == INTERP_MODE_FLAT) ||
456 (s[FS].v->inputs[j].rasterflat && emit->rasterflat)) {
457 uint32_t loc = inloc;
458
459 for (i = 0; i < 4; i++) {
460 if (compmask & (1 << i)) {
461 vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
462 //flatshade[loc / 32] |= 1 << (loc % 32);
463 loc++;
464 }
465 }
466 }
467
468 gl_varying_slot slot = s[FS].v->inputs[j].slot;
469
470 /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
471 if (slot >= VARYING_SLOT_VAR0) {
472 unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
473 /* Replace the .xy coordinates with S/T from the point sprite. Set
474 * interpolation bits for .zw such that they become .01
475 */
476 if (emit->sprite_coord_enable & texmask) {
477 /* mask is two 2-bit fields, where:
478 * '01' -> S
479 * '10' -> T
480 * '11' -> 1 - T (flip mode)
481 */
482 unsigned mask = emit->sprite_coord_mode ? 0b1101 : 0b1001;
483 uint32_t loc = inloc;
484 if (compmask & 0x1) {
485 vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
486 loc++;
487 }
488 if (compmask & 0x2) {
489 vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
490 loc++;
491 }
492 if (compmask & 0x4) {
493 /* .z <- 0.0f */
494 vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
495 loc++;
496 }
497 if (compmask & 0x8) {
498 /* .w <- 1.0f */
499 vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
500 loc++;
501 }
502 }
503 }
504 }
505
506 OUT_PKT0(ring, REG_A4XX_VPC_ATTR, 2);
507 OUT_RING(ring, A4XX_VPC_ATTR_TOTALATTR(s[FS].v->total_in) |
508 A4XX_VPC_ATTR_THRDASSIGN(1) |
509 COND(s[FS].v->total_in > 0, A4XX_VPC_ATTR_ENABLE) |
510 0x40000000 | /* XXX */
511 COND(s[VS].v->writes_psize, A4XX_VPC_ATTR_PSIZE));
512 OUT_RING(ring, A4XX_VPC_PACK_NUMFPNONPOSVAR(s[FS].v->total_in) |
513 A4XX_VPC_PACK_NUMNONPOSVSVAR(s[FS].v->total_in));
514
515 OUT_PKT0(ring, REG_A4XX_VPC_VARYING_INTERP_MODE(0), 8);
516 for (i = 0; i < 8; i++)
517 OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
518
519 OUT_PKT0(ring, REG_A4XX_VPC_VARYING_PS_REPL_MODE(0), 8);
520 for (i = 0; i < 8; i++)
521 OUT_RING(ring, vpsrepl[i]); /* VPC_VARYING_PS_REPL[i] */
522 }
523
524 if (s[VS].instrlen)
525 emit_shader(ring, s[VS].v);
526
527 if (!emit->binning_pass)
528 if (s[FS].instrlen)
529 emit_shader(ring, s[FS].v);
530 }
531
532 void
533 fd4_prog_init(struct pipe_context *pctx)
534 {
535 ir3_prog_init(pctx);
536 fd_prog_init(pctx);
537 }