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freedreno/a4xx: rework vinterp/vpsrepl
[mesa.git] / src / gallium / drivers / freedreno / a4xx / fd4_program.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_inlines.h"
33 #include "util/u_format.h"
34
35 #include "freedreno_program.h"
36
37 #include "fd4_program.h"
38 #include "fd4_emit.h"
39 #include "fd4_texture.h"
40 #include "fd4_format.h"
41
42 static void
43 delete_shader_stateobj(struct fd4_shader_stateobj *so)
44 {
45 ir3_shader_destroy(so->shader);
46 free(so);
47 }
48
49 static struct fd4_shader_stateobj *
50 create_shader_stateobj(struct pipe_context *pctx, const struct pipe_shader_state *cso,
51 enum shader_t type)
52 {
53 struct fd4_shader_stateobj *so = CALLOC_STRUCT(fd4_shader_stateobj);
54 so->shader = ir3_shader_create(pctx, cso, type);
55 return so;
56 }
57
58 static void *
59 fd4_fp_state_create(struct pipe_context *pctx,
60 const struct pipe_shader_state *cso)
61 {
62 return create_shader_stateobj(pctx, cso, SHADER_FRAGMENT);
63 }
64
65 static void
66 fd4_fp_state_delete(struct pipe_context *pctx, void *hwcso)
67 {
68 struct fd4_shader_stateobj *so = hwcso;
69 delete_shader_stateobj(so);
70 }
71
72 static void *
73 fd4_vp_state_create(struct pipe_context *pctx,
74 const struct pipe_shader_state *cso)
75 {
76 return create_shader_stateobj(pctx, cso, SHADER_VERTEX);
77 }
78
79 static void
80 fd4_vp_state_delete(struct pipe_context *pctx, void *hwcso)
81 {
82 struct fd4_shader_stateobj *so = hwcso;
83 delete_shader_stateobj(so);
84 }
85
86 static void
87 emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
88 {
89 const struct ir3_info *si = &so->info;
90 enum adreno_state_block sb;
91 enum adreno_state_src src;
92 uint32_t i, sz, *bin;
93
94 if (so->type == SHADER_VERTEX) {
95 sb = SB_VERT_SHADER;
96 } else {
97 sb = SB_FRAG_SHADER;
98 }
99
100 if (fd_mesa_debug & FD_DBG_DIRECT) {
101 sz = si->sizedwords;
102 src = SS_DIRECT;
103 bin = fd_bo_map(so->bo);
104 } else {
105 sz = 0;
106 src = 2; // enums different on a4xx..
107 bin = NULL;
108 }
109
110 OUT_PKT3(ring, CP_LOAD_STATE, 2 + sz);
111 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
112 CP_LOAD_STATE_0_STATE_SRC(src) |
113 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
114 CP_LOAD_STATE_0_NUM_UNIT(so->instrlen));
115 if (bin) {
116 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
117 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER));
118 } else {
119 OUT_RELOC(ring, so->bo, 0,
120 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER), 0);
121 }
122 for (i = 0; i < sz; i++) {
123 OUT_RING(ring, bin[i]);
124 }
125 }
126
127 struct stage {
128 const struct ir3_shader_variant *v;
129 const struct ir3_info *i;
130 /* const sizes are in units of 4 * vec4 */
131 uint8_t constoff;
132 uint8_t constlen;
133 /* instr sizes are in units of 16 instructions */
134 uint8_t instroff;
135 uint8_t instrlen;
136 };
137
138 enum {
139 VS = 0,
140 FS = 1,
141 HS = 2,
142 DS = 3,
143 GS = 4,
144 MAX_STAGES
145 };
146
147 static void
148 setup_stages(struct fd4_emit *emit, struct stage *s)
149 {
150 unsigned i;
151
152 s[VS].v = fd4_emit_get_vp(emit);
153
154 if (emit->key.binning_pass) {
155 /* use dummy stateobj to simplify binning vs non-binning: */
156 static const struct ir3_shader_variant binning_fp = {};
157 s[FS].v = &binning_fp;
158 } else {
159 s[FS].v = fd4_emit_get_fp(emit);
160 }
161
162 s[HS].v = s[DS].v = s[GS].v = NULL; /* for now */
163
164 for (i = 0; i < MAX_STAGES; i++) {
165 if (s[i].v) {
166 s[i].i = &s[i].v->info;
167 /* constlen is in units of 4 * vec4: */
168 s[i].constlen = align(s[i].v->constlen, 4) / 4;
169 /* instrlen is already in units of 16 instr.. although
170 * probably we should ditch that and not make the compiler
171 * care about instruction group size of a3xx vs a4xx
172 */
173 s[i].instrlen = s[i].v->instrlen;
174 } else {
175 s[i].i = NULL;
176 s[i].constlen = 0;
177 s[i].instrlen = 0;
178 }
179 }
180
181 /* NOTE: at least for gles2, blob partitions VS at bottom of const
182 * space and FS taking entire remaining space. We probably don't
183 * need to do that the same way, but for now mimic what the blob
184 * does to make it easier to diff against register values from blob
185 *
186 * NOTE: if VS.instrlen + FS.instrlen > 64, then one or both shaders
187 * is run from external memory.
188 */
189 if ((s[VS].instrlen + s[FS].instrlen) > 64) {
190 /* prioritize FS for internal memory: */
191 if (s[FS].instrlen < 64) {
192 /* if FS can fit, kick VS out to external memory: */
193 s[VS].instrlen = 0;
194 } else if (s[VS].instrlen < 64) {
195 /* otherwise if VS can fit, kick out FS: */
196 s[FS].instrlen = 0;
197 } else {
198 /* neither can fit, run both from external memory: */
199 s[VS].instrlen = 0;
200 s[FS].instrlen = 0;
201 }
202 }
203 s[VS].constlen = 66;
204 s[FS].constlen = 128 - s[VS].constlen;
205 s[VS].instroff = 0;
206 s[VS].constoff = 0;
207 s[FS].instroff = 64 - s[FS].instrlen;
208 s[FS].constoff = s[VS].constlen;
209 s[HS].instroff = s[DS].instroff = s[GS].instroff = s[FS].instroff;
210 s[HS].constoff = s[DS].constoff = s[GS].constoff = s[FS].constoff;
211 }
212
213 void
214 fd4_program_emit(struct fd_ringbuffer *ring, struct fd4_emit *emit,
215 int nr, struct pipe_surface **bufs)
216 {
217 struct stage s[MAX_STAGES];
218 uint32_t pos_regid, posz_regid, psize_regid, color_regid[8];
219 uint32_t face_regid, coord_regid, zwcoord_regid;
220 int constmode;
221 int i, j, k;
222
223 debug_assert(nr <= ARRAY_SIZE(color_regid));
224
225 setup_stages(emit, s);
226
227 /* blob seems to always use constmode currently: */
228 constmode = 1;
229
230 pos_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_POS);
231 posz_regid = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DEPTH);
232 psize_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_PSIZ);
233 if (s[FS].v->color0_mrt) {
234 color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
235 color_regid[4] = color_regid[5] = color_regid[6] = color_regid[7] =
236 ir3_find_output_regid(s[FS].v, FRAG_RESULT_COLOR);
237 } else {
238 color_regid[0] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA0);
239 color_regid[1] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA1);
240 color_regid[2] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA2);
241 color_regid[3] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA3);
242 color_regid[4] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA4);
243 color_regid[5] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA5);
244 color_regid[6] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA6);
245 color_regid[7] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA7);
246 }
247
248 /* TODO get these dynamically: */
249 face_regid = s[FS].v->frag_face ? regid(0,0) : regid(63,0);
250 coord_regid = s[FS].v->frag_coord ? regid(0,0) : regid(63,0);
251 zwcoord_regid = s[FS].v->frag_coord ? regid(0,2) : regid(63,0);
252
253 /* we could probably divide this up into things that need to be
254 * emitted if frag-prog is dirty vs if vert-prog is dirty..
255 */
256
257 OUT_PKT0(ring, REG_A4XX_HLSQ_UPDATE_CONTROL, 1);
258 OUT_RING(ring, 0x00000003);
259
260 OUT_PKT0(ring, REG_A4XX_HLSQ_CONTROL_0_REG, 5);
261 OUT_RING(ring, A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS) |
262 A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(constmode) |
263 A4XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE |
264 /* NOTE: I guess SHADERRESTART and CONSTFULLUPDATE maybe
265 * flush some caches? I think we only need to set those
266 * bits if we have updated const or shader..
267 */
268 A4XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART |
269 A4XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE);
270 OUT_RING(ring, A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
271 A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE |
272 A4XX_HLSQ_CONTROL_1_REG_COORDREGID(coord_regid) |
273 A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID(zwcoord_regid));
274 OUT_RING(ring, A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(63) |
275 0x3f3f000 | /* XXX */
276 A4XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid));
277 OUT_RING(ring, A4XX_HLSQ_CONTROL_3_REG_REGID(s[FS].v->pos_regid) |
278 0xfcfcfc00);
279 OUT_RING(ring, 0x00fcfcfc); /* XXX HLSQ_CONTROL_4 */
280
281 OUT_PKT0(ring, REG_A4XX_HLSQ_VS_CONTROL_REG, 5);
282 OUT_RING(ring, A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(s[VS].constlen) |
283 A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(s[VS].constoff) |
284 A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(s[VS].instrlen) |
285 A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(s[VS].instroff));
286 OUT_RING(ring, A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(s[FS].constlen) |
287 A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(s[FS].constoff) |
288 A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(s[FS].instrlen) |
289 A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(s[FS].instroff));
290 OUT_RING(ring, A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(s[HS].constlen) |
291 A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(s[HS].constoff) |
292 A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(s[HS].instrlen) |
293 A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(s[HS].instroff));
294 OUT_RING(ring, A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(s[DS].constlen) |
295 A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(s[DS].constoff) |
296 A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(s[DS].instrlen) |
297 A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(s[DS].instroff));
298 OUT_RING(ring, A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(s[GS].constlen) |
299 A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(s[GS].constoff) |
300 A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(s[GS].instrlen) |
301 A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(s[GS].instroff));
302
303 OUT_PKT0(ring, REG_A4XX_SP_SP_CTRL_REG, 1);
304 OUT_RING(ring, 0x140010 | /* XXX */
305 COND(emit->key.binning_pass, A4XX_SP_SP_CTRL_REG_BINNING_PASS));
306
307 OUT_PKT0(ring, REG_A4XX_SP_INSTR_CACHE_CTRL, 1);
308 OUT_RING(ring, 0x7f | /* XXX */
309 COND(s[VS].instrlen, A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER) |
310 COND(s[FS].instrlen, A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER) |
311 COND(s[VS].instrlen && s[FS].instrlen,
312 A4XX_SP_INSTR_CACHE_CTRL_INSTR_BUFFER));
313
314 OUT_PKT0(ring, REG_A4XX_SP_VS_LENGTH_REG, 1);
315 OUT_RING(ring, s[VS].v->instrlen); /* SP_VS_LENGTH_REG */
316
317 OUT_PKT0(ring, REG_A4XX_SP_VS_CTRL_REG0, 3);
318 OUT_RING(ring, A4XX_SP_VS_CTRL_REG0_THREADMODE(MULTI) |
319 A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(s[VS].i->max_half_reg + 1) |
320 A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(s[VS].i->max_reg + 1) |
321 A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(0) |
322 A4XX_SP_VS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
323 A4XX_SP_VS_CTRL_REG0_SUPERTHREADMODE |
324 COND(s[VS].v->has_samp, A4XX_SP_VS_CTRL_REG0_PIXLODENABLE));
325 OUT_RING(ring, A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(s[VS].constlen) |
326 A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(s[VS].v->total_in));
327 OUT_RING(ring, A4XX_SP_VS_PARAM_REG_POSREGID(pos_regid) |
328 A4XX_SP_VS_PARAM_REG_PSIZEREGID(psize_regid) |
329 A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(align(s[FS].v->total_in, 4) / 4));
330
331 for (i = 0, j = -1; (i < 16) && (j < (int)s[FS].v->inputs_count); i++) {
332 uint32_t reg = 0;
333
334 OUT_PKT0(ring, REG_A4XX_SP_VS_OUT_REG(i), 1);
335
336 j = ir3_next_varying(s[FS].v, j);
337 if (j < s[FS].v->inputs_count) {
338 k = ir3_find_output(s[VS].v, s[FS].v->inputs[j].slot);
339 reg |= A4XX_SP_VS_OUT_REG_A_REGID(s[VS].v->outputs[k].regid);
340 reg |= A4XX_SP_VS_OUT_REG_A_COMPMASK(s[FS].v->inputs[j].compmask);
341 }
342
343 j = ir3_next_varying(s[FS].v, j);
344 if (j < s[FS].v->inputs_count) {
345 k = ir3_find_output(s[VS].v, s[FS].v->inputs[j].slot);
346 reg |= A4XX_SP_VS_OUT_REG_B_REGID(s[VS].v->outputs[k].regid);
347 reg |= A4XX_SP_VS_OUT_REG_B_COMPMASK(s[FS].v->inputs[j].compmask);
348 }
349
350 OUT_RING(ring, reg);
351 }
352
353 for (i = 0, j = -1; (i < 8) && (j < (int)s[FS].v->inputs_count); i++) {
354 uint32_t reg = 0;
355
356 OUT_PKT0(ring, REG_A4XX_SP_VS_VPC_DST_REG(i), 1);
357
358 j = ir3_next_varying(s[FS].v, j);
359 if (j < s[FS].v->inputs_count)
360 reg |= A4XX_SP_VS_VPC_DST_REG_OUTLOC0(s[FS].v->inputs[j].inloc);
361 j = ir3_next_varying(s[FS].v, j);
362 if (j < s[FS].v->inputs_count)
363 reg |= A4XX_SP_VS_VPC_DST_REG_OUTLOC1(s[FS].v->inputs[j].inloc);
364 j = ir3_next_varying(s[FS].v, j);
365 if (j < s[FS].v->inputs_count)
366 reg |= A4XX_SP_VS_VPC_DST_REG_OUTLOC2(s[FS].v->inputs[j].inloc);
367 j = ir3_next_varying(s[FS].v, j);
368 if (j < s[FS].v->inputs_count)
369 reg |= A4XX_SP_VS_VPC_DST_REG_OUTLOC3(s[FS].v->inputs[j].inloc);
370
371 OUT_RING(ring, reg);
372 }
373
374 OUT_PKT0(ring, REG_A4XX_SP_VS_OBJ_OFFSET_REG, 2);
375 OUT_RING(ring, A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[VS].constoff) |
376 A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[VS].instroff));
377 OUT_RELOC(ring, s[VS].v->bo, 0, 0, 0); /* SP_VS_OBJ_START_REG */
378
379 OUT_PKT0(ring, REG_A4XX_SP_FS_LENGTH_REG, 1);
380 OUT_RING(ring, s[FS].v->instrlen); /* SP_FS_LENGTH_REG */
381
382 OUT_PKT0(ring, REG_A4XX_SP_FS_CTRL_REG0, 2);
383 OUT_RING(ring, A4XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
384 COND(s[FS].v->total_in > 0, A4XX_SP_FS_CTRL_REG0_VARYING) |
385 A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(s[FS].i->max_half_reg + 1) |
386 A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s[FS].i->max_reg + 1) |
387 A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(1) |
388 A4XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
389 A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE |
390 COND(s[FS].v->has_samp, A4XX_SP_FS_CTRL_REG0_PIXLODENABLE));
391 OUT_RING(ring, A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(s[FS].constlen) |
392 0x80000000 | /* XXX */
393 COND(s[FS].v->frag_face, A4XX_SP_FS_CTRL_REG1_FACENESS) |
394 COND(s[FS].v->total_in > 0, A4XX_SP_FS_CTRL_REG1_VARYING) |
395 COND(s[FS].v->frag_coord, A4XX_SP_FS_CTRL_REG1_FRAGCOORD));
396
397 OUT_PKT0(ring, REG_A4XX_SP_FS_OBJ_OFFSET_REG, 2);
398 OUT_RING(ring, A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[FS].constoff) |
399 A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[FS].instroff));
400 if (emit->key.binning_pass)
401 OUT_RING(ring, 0x00000000);
402 else
403 OUT_RELOC(ring, s[FS].v->bo, 0, 0, 0); /* SP_FS_OBJ_START_REG */
404
405 OUT_PKT0(ring, REG_A4XX_SP_HS_OBJ_OFFSET_REG, 1);
406 OUT_RING(ring, A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[HS].constoff) |
407 A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[HS].instroff));
408
409 OUT_PKT0(ring, REG_A4XX_SP_DS_OBJ_OFFSET_REG, 1);
410 OUT_RING(ring, A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[DS].constoff) |
411 A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[DS].instroff));
412
413 OUT_PKT0(ring, REG_A4XX_SP_GS_OBJ_OFFSET_REG, 1);
414 OUT_RING(ring, A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[GS].constoff) |
415 A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[GS].instroff));
416
417 OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL2, 1);
418 OUT_RING(ring, A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(0) |
419 COND(s[FS].v->total_in > 0, A4XX_RB_RENDER_CONTROL2_VARYING) |
420 COND(s[FS].v->frag_face, A4XX_RB_RENDER_CONTROL2_FACENESS) |
421 COND(s[FS].v->frag_coord, A4XX_RB_RENDER_CONTROL2_XCOORD |
422 A4XX_RB_RENDER_CONTROL2_YCOORD |
423 // TODO enabling gl_FragCoord.z is causing lockups on 0ad (but seems
424 // to work everywhere else).
425 // A4XX_RB_RENDER_CONTROL2_ZCOORD |
426 A4XX_RB_RENDER_CONTROL2_WCOORD));
427
428 OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT_REG, 1);
429 OUT_RING(ring, A4XX_RB_FS_OUTPUT_REG_MRT(MAX2(1, nr)) |
430 COND(s[FS].v->writes_pos, A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z));
431
432 OUT_PKT0(ring, REG_A4XX_SP_FS_OUTPUT_REG, 1);
433 OUT_RING(ring, A4XX_SP_FS_OUTPUT_REG_MRT(MAX2(1, nr)) |
434 COND(s[FS].v->writes_pos, A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE) |
435 A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(posz_regid));
436
437 OUT_PKT0(ring, REG_A4XX_SP_FS_MRT_REG(0), 8);
438 for (i = 0; i < 8; i++) {
439 enum a4xx_color_fmt format = 0;
440 bool srgb = false;
441 if (i < nr) {
442 format = fd4_emit_format(bufs[i]);
443 if (bufs[i] && !emit->no_decode_srgb)
444 srgb = util_format_is_srgb(bufs[i]->format);
445 }
446 OUT_RING(ring, A4XX_SP_FS_MRT_REG_REGID(color_regid[i]) |
447 A4XX_SP_FS_MRT_REG_MRTFORMAT(format) |
448 COND(srgb, A4XX_SP_FS_MRT_REG_COLOR_SRGB) |
449 COND(emit->key.half_precision,
450 A4XX_SP_FS_MRT_REG_HALF_PRECISION));
451 }
452
453 if (emit->key.binning_pass) {
454 OUT_PKT0(ring, REG_A4XX_VPC_ATTR, 2);
455 OUT_RING(ring, A4XX_VPC_ATTR_THRDASSIGN(1) |
456 0x40000000 | /* XXX */
457 COND(s[VS].v->writes_psize, A4XX_VPC_ATTR_PSIZE));
458 OUT_RING(ring, 0x00000000);
459 } else {
460 uint32_t vinterp[8], vpsrepl[8];
461
462 memset(vinterp, 0, sizeof(vinterp));
463 memset(vpsrepl, 0, sizeof(vpsrepl));
464
465 /* looks like we need to do int varyings in the frag
466 * shader on a4xx (no flatshad reg? or a420.0 bug?):
467 *
468 * (sy)(ss)nop
469 * (sy)ldlv.u32 r0.x,l[r0.x], 1
470 * ldlv.u32 r0.y,l[r0.x+1], 1
471 * (ss)bary.f (ei)r63.x, 0, r0.x
472 * (ss)(rpt1)cov.s32f16 hr0.x, (r)r0.x
473 * (rpt5)nop
474 * sam (f16)(xyzw)hr0.x, hr0.x, s#0, t#0
475 *
476 * Possibly on later a4xx variants we'll be able to use
477 * something like the code below instead of workaround
478 * in the shader:
479 */
480 /* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
481 for (j = -1; (j = ir3_next_varying(s[FS].v, j)) < (int)s[FS].v->inputs_count; ) {
482 /* NOTE: varyings are packed, so if compmask is 0xb
483 * then first, third, and fourth component occupy
484 * three consecutive varying slots:
485 */
486 unsigned compmask = s[FS].v->inputs[j].compmask;
487
488 /* TODO might be cleaner to just +8 in SP_VS_VPC_DST_REG
489 * instead.. rather than -8 everywhere else..
490 */
491 uint32_t inloc = s[FS].v->inputs[j].inloc - 8;
492
493 if ((s[FS].v->inputs[j].interpolate == INTERP_QUALIFIER_FLAT) ||
494 (s[FS].v->inputs[j].rasterflat && emit->rasterflat)) {
495 uint32_t loc = inloc;
496
497 for (i = 0; i < 4; i++) {
498 if (compmask & (1 << i)) {
499 vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
500 //flatshade[loc / 32] |= 1 << (loc % 32);
501 loc++;
502 }
503 }
504 }
505
506 gl_varying_slot slot = s[FS].v->inputs[j].slot;
507
508 /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
509 if (slot >= VARYING_SLOT_VAR0) {
510 unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
511 /* Replace the .xy coordinates with S/T from the point sprite. Set
512 * interpolation bits for .zw such that they become .01
513 */
514 if (emit->sprite_coord_enable & texmask) {
515 /* mask is two 2-bit fields, where:
516 * '01' -> S
517 * '10' -> T
518 * '11' -> 1 - T (flip mode)
519 */
520 unsigned mask = emit->sprite_coord_mode ? 0b1101 : 0b1001;
521 uint32_t loc = inloc;
522 if (compmask & 0x1) {
523 vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
524 loc++;
525 }
526 if (compmask & 0x2) {
527 vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
528 loc++;
529 }
530 if (compmask & 0x4) {
531 /* .z <- 0.0f */
532 vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
533 loc++;
534 }
535 if (compmask & 0x8) {
536 /* .w <- 1.0f */
537 vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
538 loc++;
539 }
540 }
541 }
542 }
543
544 OUT_PKT0(ring, REG_A4XX_VPC_ATTR, 2);
545 OUT_RING(ring, A4XX_VPC_ATTR_TOTALATTR(s[FS].v->total_in) |
546 A4XX_VPC_ATTR_THRDASSIGN(1) |
547 COND(s[FS].v->total_in > 0, A4XX_VPC_ATTR_ENABLE) |
548 0x40000000 | /* XXX */
549 COND(s[VS].v->writes_psize, A4XX_VPC_ATTR_PSIZE));
550 OUT_RING(ring, A4XX_VPC_PACK_NUMFPNONPOSVAR(s[FS].v->total_in) |
551 A4XX_VPC_PACK_NUMNONPOSVSVAR(s[FS].v->total_in));
552
553 OUT_PKT0(ring, REG_A4XX_VPC_VARYING_INTERP_MODE(0), 8);
554 for (i = 0; i < 8; i++)
555 OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
556
557 OUT_PKT0(ring, REG_A4XX_VPC_VARYING_PS_REPL_MODE(0), 8);
558 for (i = 0; i < 8; i++)
559 OUT_RING(ring, vpsrepl[i]); /* VPC_VARYING_PS_REPL[i] */
560 }
561
562 if (s[VS].instrlen)
563 emit_shader(ring, s[VS].v);
564
565 if (!emit->key.binning_pass)
566 if (s[FS].instrlen)
567 emit_shader(ring, s[FS].v);
568 }
569
570 void
571 fd4_prog_init(struct pipe_context *pctx)
572 {
573 pctx->create_fs_state = fd4_fp_state_create;
574 pctx->delete_fs_state = fd4_fp_state_delete;
575
576 pctx->create_vs_state = fd4_vp_state_create;
577 pctx->delete_vs_state = fd4_vp_state_delete;
578
579 fd_prog_init(pctx);
580 }