1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_inlines.h"
33 #include "util/u_format.h"
34 #include "tgsi/tgsi_dump.h"
35 #include "tgsi/tgsi_parse.h"
37 #include "freedreno_program.h"
39 #include "fd4_program.h"
41 #include "fd4_texture.h"
45 delete_shader_stateobj(struct fd4_shader_stateobj
*so
)
47 ir3_shader_destroy(so
->shader
);
51 static struct fd4_shader_stateobj
*
52 create_shader_stateobj(struct pipe_context
*pctx
, const struct pipe_shader_state
*cso
,
55 struct fd4_shader_stateobj
*so
= CALLOC_STRUCT(fd4_shader_stateobj
);
56 so
->shader
= ir3_shader_create(pctx
, cso
->tokens
, type
);
61 fd4_fp_state_create(struct pipe_context
*pctx
,
62 const struct pipe_shader_state
*cso
)
64 return create_shader_stateobj(pctx
, cso
, SHADER_FRAGMENT
);
68 fd4_fp_state_delete(struct pipe_context
*pctx
, void *hwcso
)
70 struct fd4_shader_stateobj
*so
= hwcso
;
71 delete_shader_stateobj(so
);
75 fd4_vp_state_create(struct pipe_context
*pctx
,
76 const struct pipe_shader_state
*cso
)
78 return create_shader_stateobj(pctx
, cso
, SHADER_VERTEX
);
82 fd4_vp_state_delete(struct pipe_context
*pctx
, void *hwcso
)
84 struct fd4_shader_stateobj
*so
= hwcso
;
85 delete_shader_stateobj(so
);
89 emit_shader(struct fd_ringbuffer
*ring
, const struct ir3_shader_variant
*so
)
91 const struct ir3_info
*si
= &so
->info
;
92 enum adreno_state_block sb
;
93 enum adreno_state_src src
;
96 if (so
->type
== SHADER_VERTEX
) {
102 if (fd_mesa_debug
& FD_DBG_DIRECT
) {
105 bin
= fd_bo_map(so
->bo
);
108 src
= 2; // enums different on a4xx..
112 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + sz
);
113 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(0) |
114 CP_LOAD_STATE_0_STATE_SRC(src
) |
115 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
116 CP_LOAD_STATE_0_NUM_UNIT(so
->instrlen
));
118 OUT_RING(ring
, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
119 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
));
121 OUT_RELOC(ring
, so
->bo
, 0,
122 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
), 0);
124 for (i
= 0; i
< sz
; i
++) {
125 OUT_RING(ring
, bin
[i
]);
130 const struct ir3_shader_variant
*v
;
131 const struct ir3_info
*i
;
132 /* const sizes are in units of 4 * vec4 */
135 /* instr sizes are in units of 16 instructions */
150 setup_stages(struct fd4_emit
*emit
, struct stage
*s
)
154 s
[VS
].v
= fd4_emit_get_vp(emit
);
156 if (emit
->key
.binning_pass
) {
157 /* use dummy stateobj to simplify binning vs non-binning: */
158 static const struct ir3_shader_variant binning_fp
= {};
159 s
[FS
].v
= &binning_fp
;
161 s
[FS
].v
= fd4_emit_get_fp(emit
);
164 s
[HS
].v
= s
[DS
].v
= s
[GS
].v
= NULL
; /* for now */
166 for (i
= 0; i
< MAX_STAGES
; i
++) {
168 s
[i
].i
= &s
[i
].v
->info
;
169 /* constlen is in units of 4 * vec4: */
170 s
[i
].constlen
= align(s
[i
].v
->constlen
, 4) / 4;
171 /* instrlen is already in units of 16 instr.. although
172 * probably we should ditch that and not make the compiler
173 * care about instruction group size of a3xx vs a4xx
175 s
[i
].instrlen
= s
[i
].v
->instrlen
;
183 /* NOTE: at least for gles2, blob partitions VS at bottom of const
184 * space and FS taking entire remaining space. We probably don't
185 * need to do that the same way, but for now mimic what the blob
186 * does to make it easier to diff against register values from blob
189 s
[FS
].constlen
= 128 - s
[VS
].constlen
;
192 s
[FS
].instroff
= 64 - s
[FS
].instrlen
;
193 s
[FS
].constoff
= s
[VS
].constlen
;
194 s
[HS
].instroff
= s
[DS
].instroff
= s
[GS
].instroff
= s
[FS
].instroff
;
195 s
[HS
].constoff
= s
[DS
].constoff
= s
[GS
].constoff
= s
[FS
].constoff
;
199 fd4_program_emit(struct fd_ringbuffer
*ring
, struct fd4_emit
*emit
)
201 struct stage s
[MAX_STAGES
];
202 uint32_t pos_regid
, posz_regid
, psize_regid
, color_regid
;
206 setup_stages(emit
, s
);
208 /* blob seems to always use constmode currently: */
211 pos_regid
= ir3_find_output_regid(s
[VS
].v
,
212 ir3_semantic_name(TGSI_SEMANTIC_POSITION
, 0));
213 posz_regid
= ir3_find_output_regid(s
[FS
].v
,
214 ir3_semantic_name(TGSI_SEMANTIC_POSITION
, 0));
215 psize_regid
= ir3_find_output_regid(s
[VS
].v
,
216 ir3_semantic_name(TGSI_SEMANTIC_PSIZE
, 0));
217 color_regid
= ir3_find_output_regid(s
[FS
].v
,
218 ir3_semantic_name(TGSI_SEMANTIC_COLOR
, 0));
220 /* we could probably divide this up into things that need to be
221 * emitted if frag-prog is dirty vs if vert-prog is dirty..
224 OUT_PKT0(ring
, REG_A4XX_HLSQ_UPDATE_CONTROL
, 1);
225 OUT_RING(ring
, 0x00000003);
227 OUT_PKT0(ring
, REG_A4XX_HLSQ_CONTROL_0_REG
, 4);
228 OUT_RING(ring
, A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS
) |
229 A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(constmode
) |
230 A4XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE
|
231 /* NOTE: I guess SHADERRESTART and CONSTFULLUPDATE maybe
232 * flush some caches? I think we only need to set those
233 * bits if we have updated const or shader..
235 A4XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART
|
236 A4XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE
);
237 OUT_RING(ring
, A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS
) |
238 0xfcfc0000 | /* XXX */
239 A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE
|
240 COND(s
[FS
].v
->frag_coord
, A4XX_HLSQ_CONTROL_1_REG_ZWCOORD
));
241 OUT_RING(ring
, A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(31));
242 OUT_RING(ring
, A4XX_HLSQ_CONTROL_3_REG_REGID(s
[FS
].v
->pos_regid
));
244 OUT_PKT0(ring
, REG_A4XX_HLSQ_VS_CONTROL_REG
, 5);
245 OUT_RING(ring
, A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(s
[VS
].constlen
) |
246 A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(s
[VS
].constoff
) |
247 A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(s
[VS
].instrlen
) |
248 A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(s
[VS
].instroff
));
249 OUT_RING(ring
, A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(s
[FS
].constlen
) |
250 A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(s
[FS
].constoff
) |
251 A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(s
[FS
].instrlen
) |
252 A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(s
[FS
].instroff
));
253 OUT_RING(ring
, A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(s
[HS
].constlen
) |
254 A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(s
[HS
].constoff
) |
255 A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(s
[HS
].instrlen
) |
256 A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(s
[HS
].instroff
));
257 OUT_RING(ring
, A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(s
[DS
].constlen
) |
258 A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(s
[DS
].constoff
) |
259 A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(s
[DS
].instrlen
) |
260 A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(s
[DS
].instroff
));
261 OUT_RING(ring
, A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(s
[GS
].constlen
) |
262 A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(s
[GS
].constoff
) |
263 A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(s
[GS
].instrlen
) |
264 A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(s
[GS
].instroff
));
266 OUT_PKT0(ring
, REG_A4XX_SP_SP_CTRL_REG
, 1);
267 OUT_RING(ring
, 0x140010 | /* XXX */
268 COND(emit
->key
.binning_pass
, A4XX_SP_SP_CTRL_REG_BINNING_PASS
));
270 OUT_PKT0(ring
, REG_A4XX_SP_INSTR_CACHE_CTRL
, 1);
271 OUT_RING(ring
, 0x1c3); /* XXX SP_INSTR_CACHE_CTRL */
273 OUT_PKT0(ring
, REG_A4XX_SP_VS_LENGTH_REG
, 1);
274 OUT_RING(ring
, s
[VS
].v
->instrlen
); /* SP_VS_LENGTH_REG */
276 OUT_PKT0(ring
, REG_A4XX_SP_VS_CTRL_REG0
, 3);
277 OUT_RING(ring
, A4XX_SP_VS_CTRL_REG0_THREADMODE(MULTI
) |
278 A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(s
[VS
].i
->max_half_reg
+ 1) |
279 A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(s
[VS
].i
->max_reg
+ 1) |
280 A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(0) |
281 A4XX_SP_VS_CTRL_REG0_THREADSIZE(TWO_QUADS
) |
282 A4XX_SP_VS_CTRL_REG0_SUPERTHREADMODE
|
283 COND(s
[VS
].v
->has_samp
, A4XX_SP_VS_CTRL_REG0_PIXLODENABLE
));
284 OUT_RING(ring
, A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(s
[VS
].constlen
) |
285 A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(s
[VS
].v
->total_in
));
286 OUT_RING(ring
, A4XX_SP_VS_PARAM_REG_POSREGID(pos_regid
) |
287 A4XX_SP_VS_PARAM_REG_PSIZEREGID(psize_regid
) |
288 A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(align(s
[FS
].v
->total_in
, 4) / 4));
290 for (i
= 0, j
= -1; (i
< 16) && (j
< (int)s
[FS
].v
->inputs_count
); i
++) {
293 OUT_PKT0(ring
, REG_A4XX_SP_VS_OUT_REG(i
), 1);
295 j
= ir3_next_varying(s
[FS
].v
, j
);
296 if (j
< s
[FS
].v
->inputs_count
) {
297 k
= ir3_find_output(s
[VS
].v
, s
[FS
].v
->inputs
[j
].semantic
);
298 reg
|= A4XX_SP_VS_OUT_REG_A_REGID(s
[VS
].v
->outputs
[k
].regid
);
299 reg
|= A4XX_SP_VS_OUT_REG_A_COMPMASK(s
[FS
].v
->inputs
[j
].compmask
);
302 j
= ir3_next_varying(s
[FS
].v
, j
);
303 if (j
< s
[FS
].v
->inputs_count
) {
304 k
= ir3_find_output(s
[VS
].v
, s
[FS
].v
->inputs
[j
].semantic
);
305 reg
|= A4XX_SP_VS_OUT_REG_B_REGID(s
[VS
].v
->outputs
[k
].regid
);
306 reg
|= A4XX_SP_VS_OUT_REG_B_COMPMASK(s
[FS
].v
->inputs
[j
].compmask
);
312 for (i
= 0, j
= -1; (i
< 8) && (j
< (int)s
[FS
].v
->inputs_count
); i
++) {
315 OUT_PKT0(ring
, REG_A4XX_SP_VS_VPC_DST_REG(i
), 1);
317 j
= ir3_next_varying(s
[FS
].v
, j
);
318 if (j
< s
[FS
].v
->inputs_count
)
319 reg
|= A4XX_SP_VS_VPC_DST_REG_OUTLOC0(s
[FS
].v
->inputs
[j
].inloc
);
320 j
= ir3_next_varying(s
[FS
].v
, j
);
321 if (j
< s
[FS
].v
->inputs_count
)
322 reg
|= A4XX_SP_VS_VPC_DST_REG_OUTLOC1(s
[FS
].v
->inputs
[j
].inloc
);
323 j
= ir3_next_varying(s
[FS
].v
, j
);
324 if (j
< s
[FS
].v
->inputs_count
)
325 reg
|= A4XX_SP_VS_VPC_DST_REG_OUTLOC2(s
[FS
].v
->inputs
[j
].inloc
);
326 j
= ir3_next_varying(s
[FS
].v
, j
);
327 if (j
< s
[FS
].v
->inputs_count
)
328 reg
|= A4XX_SP_VS_VPC_DST_REG_OUTLOC3(s
[FS
].v
->inputs
[j
].inloc
);
333 OUT_PKT0(ring
, REG_A4XX_SP_VS_OBJ_OFFSET_REG
, 2);
334 OUT_RING(ring
, A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s
[VS
].constoff
) |
335 A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s
[VS
].instroff
));
336 OUT_RELOC(ring
, s
[VS
].v
->bo
, 0, 0, 0); /* SP_VS_OBJ_START_REG */
338 OUT_PKT0(ring
, REG_A4XX_SP_FS_LENGTH_REG
, 1);
339 OUT_RING(ring
, s
[FS
].v
->instrlen
); /* SP_FS_LENGTH_REG */
341 OUT_PKT0(ring
, REG_A4XX_SP_FS_CTRL_REG0
, 2);
342 OUT_RING(ring
, A4XX_SP_FS_CTRL_REG0_THREADMODE(MULTI
) |
343 COND(s
[FS
].v
->total_in
> 0, A4XX_SP_FS_CTRL_REG0_VARYING
) |
344 A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(s
[FS
].i
->max_half_reg
+ 1) |
345 A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s
[FS
].i
->max_reg
+ 1) |
346 A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(1) |
347 A4XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS
) |
348 A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE
|
349 COND(s
[FS
].v
->has_samp
, A4XX_SP_FS_CTRL_REG0_PIXLODENABLE
));
350 OUT_RING(ring
, A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(s
[FS
].constlen
) |
351 0x80000000 | /* XXX */
352 COND(s
[FS
].v
->total_in
> 0, A4XX_SP_FS_CTRL_REG1_VARYING
));
354 OUT_PKT0(ring
, REG_A4XX_SP_FS_OBJ_OFFSET_REG
, 2);
355 OUT_RING(ring
, A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s
[FS
].constoff
) |
356 A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s
[FS
].instroff
));
357 if (emit
->key
.binning_pass
)
358 OUT_RING(ring
, 0x00000000);
360 OUT_RELOC(ring
, s
[FS
].v
->bo
, 0, 0, 0); /* SP_FS_OBJ_START_REG */
362 OUT_PKT0(ring
, REG_A4XX_SP_HS_OBJ_OFFSET_REG
, 1);
363 OUT_RING(ring
, A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s
[HS
].constoff
) |
364 A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s
[HS
].instroff
));
366 OUT_PKT0(ring
, REG_A4XX_SP_DS_OBJ_OFFSET_REG
, 1);
367 OUT_RING(ring
, A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s
[DS
].constoff
) |
368 A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s
[DS
].instroff
));
370 OUT_PKT0(ring
, REG_A4XX_SP_GS_OBJ_OFFSET_REG
, 1);
371 OUT_RING(ring
, A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s
[GS
].constoff
) |
372 A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s
[GS
].instroff
));
374 OUT_PKT0(ring
, REG_A4XX_RB_MSAA_CONTROL2
, 1);
375 OUT_RING(ring
, A4XX_RB_MSAA_CONTROL2_MSAA_SAMPLES(0) |
376 COND(s
[FS
].v
->total_in
> 0, A4XX_RB_MSAA_CONTROL2_VARYING
));
378 OUT_PKT0(ring
, REG_A4XX_SP_FS_OUTPUT_REG
, 1);
379 if (s
[FS
].v
->writes_pos
) {
380 OUT_RING(ring
, A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE
|
381 A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(posz_regid
));
383 OUT_RING(ring
, 0x00000001);
386 if (emit
->key
.binning_pass
) {
387 OUT_PKT0(ring
, REG_A4XX_VPC_ATTR
, 2);
388 OUT_RING(ring
, A4XX_VPC_ATTR_THRDASSIGN(1) |
389 0x40000000 | /* XXX */
390 COND(s
[VS
].v
->writes_psize
, A4XX_VPC_ATTR_PSIZE
));
391 OUT_RING(ring
, 0x00000000);
393 uint32_t vinterp
[8] = {0}, flatshade
[2] = {0};
395 /* figure out VARYING_INTERP / FLAT_SHAD register values: */
396 for (j
= -1; (j
= ir3_next_varying(s
[FS
].v
, j
)) < (int)s
[FS
].v
->inputs_count
; ) {
397 uint32_t interp
= s
[FS
].v
->inputs
[j
].interpolate
;
398 if ((interp
== TGSI_INTERPOLATE_CONSTANT
) ||
399 ((interp
== TGSI_INTERPOLATE_COLOR
) && emit
->rasterflat
)) {
400 /* TODO might be cleaner to just +8 in SP_VS_VPC_DST_REG
401 * instead.. rather than -8 everywhere else..
403 uint32_t loc
= s
[FS
].v
->inputs
[j
].inloc
- 8;
405 /* currently assuming varyings aligned to 4 (not
408 debug_assert((loc
% 4) == 0);
410 for (i
= 0; i
< 4; i
++, loc
++) {
411 vinterp
[loc
/ 16] |= 1 << ((loc
% 16) * 2);
412 flatshade
[loc
/ 32] |= 1 << (loc
% 32);
417 OUT_PKT0(ring
, REG_A4XX_VPC_ATTR
, 2);
418 OUT_RING(ring
, A4XX_VPC_ATTR_TOTALATTR(s
[FS
].v
->total_in
) |
419 A4XX_VPC_ATTR_THRDASSIGN(1) |
420 COND(s
[FS
].v
->total_in
> 0, A4XX_VPC_ATTR_ENABLE
) |
421 0x40000000 | /* XXX */
422 COND(s
[VS
].v
->writes_psize
, A4XX_VPC_ATTR_PSIZE
));
423 OUT_RING(ring
, A4XX_VPC_PACK_NUMFPNONPOSVAR(s
[FS
].v
->total_in
) |
424 A4XX_VPC_PACK_NUMNONPOSVSVAR(s
[FS
].v
->total_in
));
426 OUT_PKT0(ring
, REG_A4XX_VPC_VARYING_INTERP_MODE(0), 8);
427 for (i
= 0; i
< 8; i
++)
428 OUT_RING(ring
, vinterp
[i
]); /* VPC_VARYING_INTERP[i].MODE */
430 OUT_PKT0(ring
, REG_A4XX_VPC_VARYING_PS_REPL_MODE(0), 8);
431 for (i
= 0; i
< 8; i
++)
432 OUT_RING(ring
, s
[FS
].v
->shader
->vpsrepl
[i
]); /* VPC_VARYING_PS_REPL[i] */
435 emit_shader(ring
, s
[VS
].v
);
437 if (!emit
->key
.binning_pass
)
438 emit_shader(ring
, s
[FS
].v
);
441 /* hack.. until we figure out how to deal w/ vpsrepl properly.. */
443 fix_blit_fp(struct pipe_context
*pctx
)
445 struct fd_context
*ctx
= fd_context(pctx
);
446 struct fd4_shader_stateobj
*so
= ctx
->blit_prog
.fp
;
448 so
->shader
->vpsrepl
[0] = 0x99999999;
449 so
->shader
->vpsrepl
[1] = 0x99999999;
450 so
->shader
->vpsrepl
[2] = 0x99999999;
451 so
->shader
->vpsrepl
[3] = 0x99999999;
455 fd4_prog_init(struct pipe_context
*pctx
)
457 pctx
->create_fs_state
= fd4_fp_state_create
;
458 pctx
->delete_fs_state
= fd4_fp_state_delete
;
460 pctx
->create_vs_state
= fd4_vp_state_create
;
461 pctx
->delete_vs_state
= fd4_vp_state_delete
;