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freedreno/a4xx: fix vpsrepl for blit shaders
[mesa.git] / src / gallium / drivers / freedreno / a4xx / fd4_program.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_inlines.h"
33 #include "util/u_format.h"
34
35 #include "freedreno_program.h"
36
37 #include "fd4_program.h"
38 #include "fd4_emit.h"
39 #include "fd4_texture.h"
40 #include "fd4_format.h"
41
42 static void
43 delete_shader_stateobj(struct fd4_shader_stateobj *so)
44 {
45 ir3_shader_destroy(so->shader);
46 free(so);
47 }
48
49 static struct fd4_shader_stateobj *
50 create_shader_stateobj(struct pipe_context *pctx, const struct pipe_shader_state *cso,
51 enum shader_t type)
52 {
53 struct fd4_shader_stateobj *so = CALLOC_STRUCT(fd4_shader_stateobj);
54 so->shader = ir3_shader_create(pctx, cso, type);
55 return so;
56 }
57
58 static void *
59 fd4_fp_state_create(struct pipe_context *pctx,
60 const struct pipe_shader_state *cso)
61 {
62 return create_shader_stateobj(pctx, cso, SHADER_FRAGMENT);
63 }
64
65 static void
66 fd4_fp_state_delete(struct pipe_context *pctx, void *hwcso)
67 {
68 struct fd4_shader_stateobj *so = hwcso;
69 delete_shader_stateobj(so);
70 }
71
72 static void *
73 fd4_vp_state_create(struct pipe_context *pctx,
74 const struct pipe_shader_state *cso)
75 {
76 return create_shader_stateobj(pctx, cso, SHADER_VERTEX);
77 }
78
79 static void
80 fd4_vp_state_delete(struct pipe_context *pctx, void *hwcso)
81 {
82 struct fd4_shader_stateobj *so = hwcso;
83 delete_shader_stateobj(so);
84 }
85
86 static void
87 emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
88 {
89 const struct ir3_info *si = &so->info;
90 enum adreno_state_block sb;
91 enum adreno_state_src src;
92 uint32_t i, sz, *bin;
93
94 if (so->type == SHADER_VERTEX) {
95 sb = SB_VERT_SHADER;
96 } else {
97 sb = SB_FRAG_SHADER;
98 }
99
100 if (fd_mesa_debug & FD_DBG_DIRECT) {
101 sz = si->sizedwords;
102 src = SS_DIRECT;
103 bin = fd_bo_map(so->bo);
104 } else {
105 sz = 0;
106 src = 2; // enums different on a4xx..
107 bin = NULL;
108 }
109
110 OUT_PKT3(ring, CP_LOAD_STATE, 2 + sz);
111 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
112 CP_LOAD_STATE_0_STATE_SRC(src) |
113 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
114 CP_LOAD_STATE_0_NUM_UNIT(so->instrlen));
115 if (bin) {
116 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
117 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER));
118 } else {
119 OUT_RELOC(ring, so->bo, 0,
120 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER), 0);
121 }
122 for (i = 0; i < sz; i++) {
123 OUT_RING(ring, bin[i]);
124 }
125 }
126
127 struct stage {
128 const struct ir3_shader_variant *v;
129 const struct ir3_info *i;
130 /* const sizes are in units of 4 * vec4 */
131 uint8_t constoff;
132 uint8_t constlen;
133 /* instr sizes are in units of 16 instructions */
134 uint8_t instroff;
135 uint8_t instrlen;
136 };
137
138 enum {
139 VS = 0,
140 FS = 1,
141 HS = 2,
142 DS = 3,
143 GS = 4,
144 MAX_STAGES
145 };
146
147 static void
148 setup_stages(struct fd4_emit *emit, struct stage *s)
149 {
150 unsigned i;
151
152 s[VS].v = fd4_emit_get_vp(emit);
153
154 if (emit->key.binning_pass) {
155 /* use dummy stateobj to simplify binning vs non-binning: */
156 static const struct ir3_shader_variant binning_fp = {};
157 s[FS].v = &binning_fp;
158 } else {
159 s[FS].v = fd4_emit_get_fp(emit);
160 }
161
162 s[HS].v = s[DS].v = s[GS].v = NULL; /* for now */
163
164 for (i = 0; i < MAX_STAGES; i++) {
165 if (s[i].v) {
166 s[i].i = &s[i].v->info;
167 /* constlen is in units of 4 * vec4: */
168 s[i].constlen = align(s[i].v->constlen, 4) / 4;
169 /* instrlen is already in units of 16 instr.. although
170 * probably we should ditch that and not make the compiler
171 * care about instruction group size of a3xx vs a4xx
172 */
173 s[i].instrlen = s[i].v->instrlen;
174 } else {
175 s[i].i = NULL;
176 s[i].constlen = 0;
177 s[i].instrlen = 0;
178 }
179 }
180
181 /* NOTE: at least for gles2, blob partitions VS at bottom of const
182 * space and FS taking entire remaining space. We probably don't
183 * need to do that the same way, but for now mimic what the blob
184 * does to make it easier to diff against register values from blob
185 *
186 * NOTE: if VS.instrlen + FS.instrlen > 64, then one or both shaders
187 * is run from external memory.
188 */
189 if ((s[VS].instrlen + s[FS].instrlen) > 64) {
190 /* prioritize FS for internal memory: */
191 if (s[FS].instrlen < 64) {
192 /* if FS can fit, kick VS out to external memory: */
193 s[VS].instrlen = 0;
194 } else if (s[VS].instrlen < 64) {
195 /* otherwise if VS can fit, kick out FS: */
196 s[FS].instrlen = 0;
197 } else {
198 /* neither can fit, run both from external memory: */
199 s[VS].instrlen = 0;
200 s[FS].instrlen = 0;
201 }
202 }
203 s[VS].constlen = 66;
204 s[FS].constlen = 128 - s[VS].constlen;
205 s[VS].instroff = 0;
206 s[VS].constoff = 0;
207 s[FS].instroff = 64 - s[FS].instrlen;
208 s[FS].constoff = s[VS].constlen;
209 s[HS].instroff = s[DS].instroff = s[GS].instroff = s[FS].instroff;
210 s[HS].constoff = s[DS].constoff = s[GS].constoff = s[FS].constoff;
211 }
212
213 void
214 fd4_program_emit(struct fd_ringbuffer *ring, struct fd4_emit *emit,
215 int nr, struct pipe_surface **bufs)
216 {
217 struct stage s[MAX_STAGES];
218 uint32_t pos_regid, posz_regid, psize_regid, color_regid[8];
219 uint32_t face_regid, coord_regid, zwcoord_regid;
220 int constmode;
221 int i, j, k;
222
223 debug_assert(nr <= ARRAY_SIZE(color_regid));
224
225 setup_stages(emit, s);
226
227 /* blob seems to always use constmode currently: */
228 constmode = 1;
229
230 pos_regid = ir3_find_output_regid(s[VS].v,
231 ir3_semantic_name(TGSI_SEMANTIC_POSITION, 0));
232 posz_regid = ir3_find_output_regid(s[FS].v,
233 ir3_semantic_name(TGSI_SEMANTIC_POSITION, 0));
234 psize_regid = ir3_find_output_regid(s[VS].v,
235 ir3_semantic_name(TGSI_SEMANTIC_PSIZE, 0));
236 if (s[FS].v->color0_mrt) {
237 color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
238 color_regid[4] = color_regid[5] = color_regid[6] = color_regid[7] =
239 ir3_find_output_regid(s[FS].v, ir3_semantic_name(TGSI_SEMANTIC_COLOR, 0));
240 } else {
241 const struct ir3_shader_variant *fp = s[FS].v;
242 memset(color_regid, 0, sizeof(color_regid));
243 for (i = 0; i < fp->outputs_count; i++) {
244 ir3_semantic sem = fp->outputs[i].semantic;
245 unsigned idx = sem2idx(sem);
246 if (sem2name(sem) != TGSI_SEMANTIC_COLOR)
247 continue;
248 debug_assert(idx < ARRAY_SIZE(color_regid));
249 color_regid[idx] = fp->outputs[i].regid;
250 }
251 }
252
253 /* adjust regids for alpha output formats. there is no alpha render
254 * format, so it's just treated like red
255 */
256 for (i = 0; i < nr; i++)
257 if (util_format_is_alpha(pipe_surface_format(bufs[i])))
258 color_regid[i] += 3;
259
260
261 /* TODO get these dynamically: */
262 face_regid = s[FS].v->frag_face ? regid(0,0) : regid(63,0);
263 coord_regid = s[FS].v->frag_coord ? regid(0,0) : regid(63,0);
264 zwcoord_regid = s[FS].v->frag_coord ? regid(0,2) : regid(63,0);
265
266 /* we could probably divide this up into things that need to be
267 * emitted if frag-prog is dirty vs if vert-prog is dirty..
268 */
269
270 OUT_PKT0(ring, REG_A4XX_HLSQ_UPDATE_CONTROL, 1);
271 OUT_RING(ring, 0x00000003);
272
273 OUT_PKT0(ring, REG_A4XX_HLSQ_CONTROL_0_REG, 5);
274 OUT_RING(ring, A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS) |
275 A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(constmode) |
276 A4XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE |
277 /* NOTE: I guess SHADERRESTART and CONSTFULLUPDATE maybe
278 * flush some caches? I think we only need to set those
279 * bits if we have updated const or shader..
280 */
281 A4XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART |
282 A4XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE);
283 OUT_RING(ring, A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
284 A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE |
285 A4XX_HLSQ_CONTROL_1_REG_COORDREGID(coord_regid) |
286 A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID(zwcoord_regid));
287 OUT_RING(ring, A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(63) |
288 0x3f3f000 | /* XXX */
289 A4XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid));
290 OUT_RING(ring, A4XX_HLSQ_CONTROL_3_REG_REGID(s[FS].v->pos_regid) |
291 0xfcfcfc00);
292 OUT_RING(ring, 0x00fcfcfc); /* XXX HLSQ_CONTROL_4 */
293
294 OUT_PKT0(ring, REG_A4XX_HLSQ_VS_CONTROL_REG, 5);
295 OUT_RING(ring, A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(s[VS].constlen) |
296 A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(s[VS].constoff) |
297 A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(s[VS].instrlen) |
298 A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(s[VS].instroff));
299 OUT_RING(ring, A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(s[FS].constlen) |
300 A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(s[FS].constoff) |
301 A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(s[FS].instrlen) |
302 A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(s[FS].instroff));
303 OUT_RING(ring, A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(s[HS].constlen) |
304 A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(s[HS].constoff) |
305 A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(s[HS].instrlen) |
306 A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(s[HS].instroff));
307 OUT_RING(ring, A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(s[DS].constlen) |
308 A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(s[DS].constoff) |
309 A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(s[DS].instrlen) |
310 A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(s[DS].instroff));
311 OUT_RING(ring, A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(s[GS].constlen) |
312 A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(s[GS].constoff) |
313 A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(s[GS].instrlen) |
314 A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(s[GS].instroff));
315
316 OUT_PKT0(ring, REG_A4XX_SP_SP_CTRL_REG, 1);
317 OUT_RING(ring, 0x140010 | /* XXX */
318 COND(emit->key.binning_pass, A4XX_SP_SP_CTRL_REG_BINNING_PASS));
319
320 OUT_PKT0(ring, REG_A4XX_SP_INSTR_CACHE_CTRL, 1);
321 OUT_RING(ring, 0x7f | /* XXX */
322 COND(s[VS].instrlen, A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER) |
323 COND(s[FS].instrlen, A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER) |
324 COND(s[VS].instrlen && s[FS].instrlen,
325 A4XX_SP_INSTR_CACHE_CTRL_INSTR_BUFFER));
326
327 OUT_PKT0(ring, REG_A4XX_SP_VS_LENGTH_REG, 1);
328 OUT_RING(ring, s[VS].v->instrlen); /* SP_VS_LENGTH_REG */
329
330 OUT_PKT0(ring, REG_A4XX_SP_VS_CTRL_REG0, 3);
331 OUT_RING(ring, A4XX_SP_VS_CTRL_REG0_THREADMODE(MULTI) |
332 A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(s[VS].i->max_half_reg + 1) |
333 A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(s[VS].i->max_reg + 1) |
334 A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(0) |
335 A4XX_SP_VS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
336 A4XX_SP_VS_CTRL_REG0_SUPERTHREADMODE |
337 COND(s[VS].v->has_samp, A4XX_SP_VS_CTRL_REG0_PIXLODENABLE));
338 OUT_RING(ring, A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(s[VS].constlen) |
339 A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(s[VS].v->total_in));
340 OUT_RING(ring, A4XX_SP_VS_PARAM_REG_POSREGID(pos_regid) |
341 A4XX_SP_VS_PARAM_REG_PSIZEREGID(psize_regid) |
342 A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(align(s[FS].v->total_in, 4) / 4));
343
344 for (i = 0, j = -1; (i < 16) && (j < (int)s[FS].v->inputs_count); i++) {
345 uint32_t reg = 0;
346
347 OUT_PKT0(ring, REG_A4XX_SP_VS_OUT_REG(i), 1);
348
349 j = ir3_next_varying(s[FS].v, j);
350 if (j < s[FS].v->inputs_count) {
351 k = ir3_find_output(s[VS].v, s[FS].v->inputs[j].semantic);
352 reg |= A4XX_SP_VS_OUT_REG_A_REGID(s[VS].v->outputs[k].regid);
353 reg |= A4XX_SP_VS_OUT_REG_A_COMPMASK(s[FS].v->inputs[j].compmask);
354 }
355
356 j = ir3_next_varying(s[FS].v, j);
357 if (j < s[FS].v->inputs_count) {
358 k = ir3_find_output(s[VS].v, s[FS].v->inputs[j].semantic);
359 reg |= A4XX_SP_VS_OUT_REG_B_REGID(s[VS].v->outputs[k].regid);
360 reg |= A4XX_SP_VS_OUT_REG_B_COMPMASK(s[FS].v->inputs[j].compmask);
361 }
362
363 OUT_RING(ring, reg);
364 }
365
366 for (i = 0, j = -1; (i < 8) && (j < (int)s[FS].v->inputs_count); i++) {
367 uint32_t reg = 0;
368
369 OUT_PKT0(ring, REG_A4XX_SP_VS_VPC_DST_REG(i), 1);
370
371 j = ir3_next_varying(s[FS].v, j);
372 if (j < s[FS].v->inputs_count)
373 reg |= A4XX_SP_VS_VPC_DST_REG_OUTLOC0(s[FS].v->inputs[j].inloc);
374 j = ir3_next_varying(s[FS].v, j);
375 if (j < s[FS].v->inputs_count)
376 reg |= A4XX_SP_VS_VPC_DST_REG_OUTLOC1(s[FS].v->inputs[j].inloc);
377 j = ir3_next_varying(s[FS].v, j);
378 if (j < s[FS].v->inputs_count)
379 reg |= A4XX_SP_VS_VPC_DST_REG_OUTLOC2(s[FS].v->inputs[j].inloc);
380 j = ir3_next_varying(s[FS].v, j);
381 if (j < s[FS].v->inputs_count)
382 reg |= A4XX_SP_VS_VPC_DST_REG_OUTLOC3(s[FS].v->inputs[j].inloc);
383
384 OUT_RING(ring, reg);
385 }
386
387 OUT_PKT0(ring, REG_A4XX_SP_VS_OBJ_OFFSET_REG, 2);
388 OUT_RING(ring, A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[VS].constoff) |
389 A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[VS].instroff));
390 OUT_RELOC(ring, s[VS].v->bo, 0, 0, 0); /* SP_VS_OBJ_START_REG */
391
392 OUT_PKT0(ring, REG_A4XX_SP_FS_LENGTH_REG, 1);
393 OUT_RING(ring, s[FS].v->instrlen); /* SP_FS_LENGTH_REG */
394
395 OUT_PKT0(ring, REG_A4XX_SP_FS_CTRL_REG0, 2);
396 OUT_RING(ring, A4XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
397 COND(s[FS].v->total_in > 0, A4XX_SP_FS_CTRL_REG0_VARYING) |
398 A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(s[FS].i->max_half_reg + 1) |
399 A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s[FS].i->max_reg + 1) |
400 A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(1) |
401 A4XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
402 A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE |
403 COND(s[FS].v->has_samp, A4XX_SP_FS_CTRL_REG0_PIXLODENABLE));
404 OUT_RING(ring, A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(s[FS].constlen) |
405 0x80000000 | /* XXX */
406 COND(s[FS].v->frag_face, A4XX_SP_FS_CTRL_REG1_FACENESS) |
407 COND(s[FS].v->total_in > 0, A4XX_SP_FS_CTRL_REG1_VARYING) |
408 COND(s[FS].v->frag_coord, A4XX_SP_FS_CTRL_REG1_FRAGCOORD));
409
410 OUT_PKT0(ring, REG_A4XX_SP_FS_OBJ_OFFSET_REG, 2);
411 OUT_RING(ring, A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[FS].constoff) |
412 A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[FS].instroff));
413 if (emit->key.binning_pass)
414 OUT_RING(ring, 0x00000000);
415 else
416 OUT_RELOC(ring, s[FS].v->bo, 0, 0, 0); /* SP_FS_OBJ_START_REG */
417
418 OUT_PKT0(ring, REG_A4XX_SP_HS_OBJ_OFFSET_REG, 1);
419 OUT_RING(ring, A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[HS].constoff) |
420 A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[HS].instroff));
421
422 OUT_PKT0(ring, REG_A4XX_SP_DS_OBJ_OFFSET_REG, 1);
423 OUT_RING(ring, A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[DS].constoff) |
424 A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[DS].instroff));
425
426 OUT_PKT0(ring, REG_A4XX_SP_GS_OBJ_OFFSET_REG, 1);
427 OUT_RING(ring, A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[GS].constoff) |
428 A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[GS].instroff));
429
430 OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL2, 1);
431 OUT_RING(ring, A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(0) |
432 COND(s[FS].v->total_in > 0, A4XX_RB_RENDER_CONTROL2_VARYING) |
433 COND(s[FS].v->frag_face, A4XX_RB_RENDER_CONTROL2_FACENESS) |
434 COND(s[FS].v->frag_coord, A4XX_RB_RENDER_CONTROL2_XCOORD |
435 A4XX_RB_RENDER_CONTROL2_YCOORD |
436 // TODO enabling gl_FragCoord.z is causing lockups on 0ad (but seems
437 // to work everywhere else).
438 // A4XX_RB_RENDER_CONTROL2_ZCOORD |
439 A4XX_RB_RENDER_CONTROL2_WCOORD));
440
441 OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT_REG, 1);
442 OUT_RING(ring, A4XX_RB_FS_OUTPUT_REG_MRT(MAX2(1, nr)) |
443 COND(s[FS].v->writes_pos, A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z));
444
445 OUT_PKT0(ring, REG_A4XX_SP_FS_OUTPUT_REG, 1);
446 OUT_RING(ring, A4XX_SP_FS_OUTPUT_REG_MRT(MAX2(1, nr)) |
447 COND(s[FS].v->writes_pos, A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE) |
448 A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(posz_regid));
449
450 OUT_PKT0(ring, REG_A4XX_SP_FS_MRT_REG(0), 8);
451 for (i = 0; i < 8; i++) {
452 enum a4xx_color_fmt format = 0;
453 if (i < nr)
454 format = fd4_emit_format(bufs[i]);
455 OUT_RING(ring, A4XX_SP_FS_MRT_REG_REGID(color_regid[i]) |
456 A4XX_SP_FS_MRT_REG_MRTFORMAT(format) |
457 COND(emit->key.half_precision,
458 A4XX_SP_FS_MRT_REG_HALF_PRECISION));
459 }
460
461 if (emit->key.binning_pass) {
462 OUT_PKT0(ring, REG_A4XX_VPC_ATTR, 2);
463 OUT_RING(ring, A4XX_VPC_ATTR_THRDASSIGN(1) |
464 0x40000000 | /* XXX */
465 COND(s[VS].v->writes_psize, A4XX_VPC_ATTR_PSIZE));
466 OUT_RING(ring, 0x00000000);
467 } else {
468 uint32_t vinterp[8], flatshade[2];
469
470 memset(vinterp, 0, sizeof(vinterp));
471 memset(flatshade, 0, sizeof(flatshade));
472
473 /* looks like we need to do int varyings in the frag
474 * shader on a4xx (no flatshad reg? or a420.0 bug?):
475 *
476 * (sy)(ss)nop
477 * (sy)ldlv.u32 r0.x,l[r0.x], 1
478 * ldlv.u32 r0.y,l[r0.x+1], 1
479 * (ss)bary.f (ei)r63.x, 0, r0.x
480 * (ss)(rpt1)cov.s32f16 hr0.x, (r)r0.x
481 * (rpt5)nop
482 * sam (f16)(xyzw)hr0.x, hr0.x, s#0, t#0
483 *
484 * Possibly on later a4xx variants we'll be able to use
485 * something like the code below instead of workaround
486 * in the shader:
487 */
488 #if 0
489 /* figure out VARYING_INTERP / FLAT_SHAD register values: */
490 for (j = -1; (j = ir3_next_varying(s[FS].v, j)) < (int)s[FS].v->inputs_count; ) {
491 uint32_t interp = s[FS].v->inputs[j].interpolate;
492 if ((interp == TGSI_INTERPOLATE_CONSTANT) ||
493 ((interp == TGSI_INTERPOLATE_COLOR) && emit->rasterflat)) {
494 /* TODO might be cleaner to just +8 in SP_VS_VPC_DST_REG
495 * instead.. rather than -8 everywhere else..
496 */
497 uint32_t loc = s[FS].v->inputs[j].inloc - 8;
498
499 /* currently assuming varyings aligned to 4 (not
500 * packed):
501 */
502 debug_assert((loc % 4) == 0);
503
504 for (i = 0; i < 4; i++, loc++) {
505 vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
506 flatshade[loc / 32] |= 1 << (loc % 32);
507 }
508 }
509 }
510 #endif
511
512 OUT_PKT0(ring, REG_A4XX_VPC_ATTR, 2);
513 OUT_RING(ring, A4XX_VPC_ATTR_TOTALATTR(s[FS].v->total_in) |
514 A4XX_VPC_ATTR_THRDASSIGN(1) |
515 COND(s[FS].v->total_in > 0, A4XX_VPC_ATTR_ENABLE) |
516 0x40000000 | /* XXX */
517 COND(s[VS].v->writes_psize, A4XX_VPC_ATTR_PSIZE));
518 OUT_RING(ring, A4XX_VPC_PACK_NUMFPNONPOSVAR(s[FS].v->total_in) |
519 A4XX_VPC_PACK_NUMNONPOSVSVAR(s[FS].v->total_in));
520
521 OUT_PKT0(ring, REG_A4XX_VPC_VARYING_INTERP_MODE(0), 8);
522 for (i = 0; i < 8; i++)
523 OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
524
525 OUT_PKT0(ring, REG_A4XX_VPC_VARYING_PS_REPL_MODE(0), 8);
526 for (i = 0; i < 8; i++)
527 OUT_RING(ring, s[FS].v->shader->vpsrepl[i]); /* VPC_VARYING_PS_REPL[i] */
528 }
529
530 if (s[VS].instrlen)
531 emit_shader(ring, s[VS].v);
532
533 if (!emit->key.binning_pass)
534 if (s[FS].instrlen)
535 emit_shader(ring, s[FS].v);
536 }
537
538 /* hack.. until we figure out how to deal w/ vpsrepl properly.. */
539 static void
540 fix_blit_fp(struct fd4_shader_stateobj *so)
541 {
542 so->shader->vpsrepl[0] = 0x99999999;
543 so->shader->vpsrepl[1] = 0x99999999;
544 so->shader->vpsrepl[2] = 0x99999999;
545 so->shader->vpsrepl[3] = 0x99999999;
546 }
547 static void
548 fix_blit_fps(struct pipe_context *pctx)
549 {
550 struct fd_context *ctx = fd_context(pctx);
551 int i;
552
553 for (i = 0; i < ctx->screen->max_rts; i++)
554 fix_blit_fp(ctx->blit_prog[i].fp);
555
556 fix_blit_fp(ctx->blit_z.fp);
557 fix_blit_fp(ctx->blit_zs.fp);
558 }
559
560 void
561 fd4_prog_init(struct pipe_context *pctx)
562 {
563 pctx->create_fs_state = fd4_fp_state_create;
564 pctx->delete_fs_state = fd4_fp_state_delete;
565
566 pctx->create_vs_state = fd4_vp_state_create;
567 pctx->delete_vs_state = fd4_vp_state_delete;
568
569 fd_prog_init(pctx);
570
571 fix_blit_fps(pctx);
572 }