1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_inlines.h"
33 #include "util/u_format.h"
35 #include "freedreno_program.h"
37 #include "fd4_program.h"
39 #include "fd4_texture.h"
40 #include "fd4_format.h"
43 delete_shader_stateobj(struct fd4_shader_stateobj
*so
)
45 ir3_shader_destroy(so
->shader
);
49 static struct fd4_shader_stateobj
*
50 create_shader_stateobj(struct pipe_context
*pctx
, const struct pipe_shader_state
*cso
,
53 struct fd4_shader_stateobj
*so
= CALLOC_STRUCT(fd4_shader_stateobj
);
54 so
->shader
= ir3_shader_create(pctx
, cso
, type
);
59 fd4_fp_state_create(struct pipe_context
*pctx
,
60 const struct pipe_shader_state
*cso
)
62 return create_shader_stateobj(pctx
, cso
, SHADER_FRAGMENT
);
66 fd4_fp_state_delete(struct pipe_context
*pctx
, void *hwcso
)
68 struct fd4_shader_stateobj
*so
= hwcso
;
69 delete_shader_stateobj(so
);
73 fd4_vp_state_create(struct pipe_context
*pctx
,
74 const struct pipe_shader_state
*cso
)
76 return create_shader_stateobj(pctx
, cso
, SHADER_VERTEX
);
80 fd4_vp_state_delete(struct pipe_context
*pctx
, void *hwcso
)
82 struct fd4_shader_stateobj
*so
= hwcso
;
83 delete_shader_stateobj(so
);
87 emit_shader(struct fd_ringbuffer
*ring
, const struct ir3_shader_variant
*so
)
89 const struct ir3_info
*si
= &so
->info
;
90 enum adreno_state_block sb
;
91 enum adreno_state_src src
;
94 if (so
->type
== SHADER_VERTEX
) {
100 if (fd_mesa_debug
& FD_DBG_DIRECT
) {
103 bin
= fd_bo_map(so
->bo
);
106 src
= 2; // enums different on a4xx..
110 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + sz
);
111 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(0) |
112 CP_LOAD_STATE_0_STATE_SRC(src
) |
113 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
114 CP_LOAD_STATE_0_NUM_UNIT(so
->instrlen
));
116 OUT_RING(ring
, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
117 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
));
119 OUT_RELOC(ring
, so
->bo
, 0,
120 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
), 0);
122 for (i
= 0; i
< sz
; i
++) {
123 OUT_RING(ring
, bin
[i
]);
128 const struct ir3_shader_variant
*v
;
129 const struct ir3_info
*i
;
130 /* const sizes are in units of 4 * vec4 */
133 /* instr sizes are in units of 16 instructions */
148 setup_stages(struct fd4_emit
*emit
, struct stage
*s
)
152 s
[VS
].v
= fd4_emit_get_vp(emit
);
154 if (emit
->key
.binning_pass
) {
155 /* use dummy stateobj to simplify binning vs non-binning: */
156 static const struct ir3_shader_variant binning_fp
= {};
157 s
[FS
].v
= &binning_fp
;
159 s
[FS
].v
= fd4_emit_get_fp(emit
);
162 s
[HS
].v
= s
[DS
].v
= s
[GS
].v
= NULL
; /* for now */
164 for (i
= 0; i
< MAX_STAGES
; i
++) {
166 s
[i
].i
= &s
[i
].v
->info
;
167 /* constlen is in units of 4 * vec4: */
168 s
[i
].constlen
= align(s
[i
].v
->constlen
, 4) / 4;
169 /* instrlen is already in units of 16 instr.. although
170 * probably we should ditch that and not make the compiler
171 * care about instruction group size of a3xx vs a4xx
173 s
[i
].instrlen
= s
[i
].v
->instrlen
;
181 /* NOTE: at least for gles2, blob partitions VS at bottom of const
182 * space and FS taking entire remaining space. We probably don't
183 * need to do that the same way, but for now mimic what the blob
184 * does to make it easier to diff against register values from blob
186 * NOTE: if VS.instrlen + FS.instrlen > 64, then one or both shaders
187 * is run from external memory.
189 if ((s
[VS
].instrlen
+ s
[FS
].instrlen
) > 64) {
190 /* prioritize FS for internal memory: */
191 if (s
[FS
].instrlen
< 64) {
192 /* if FS can fit, kick VS out to external memory: */
194 } else if (s
[VS
].instrlen
< 64) {
195 /* otherwise if VS can fit, kick out FS: */
198 /* neither can fit, run both from external memory: */
204 s
[FS
].constlen
= 128 - s
[VS
].constlen
;
207 s
[FS
].instroff
= 64 - s
[FS
].instrlen
;
208 s
[FS
].constoff
= s
[VS
].constlen
;
209 s
[HS
].instroff
= s
[DS
].instroff
= s
[GS
].instroff
= s
[FS
].instroff
;
210 s
[HS
].constoff
= s
[DS
].constoff
= s
[GS
].constoff
= s
[FS
].constoff
;
214 fd4_program_emit(struct fd_ringbuffer
*ring
, struct fd4_emit
*emit
,
215 int nr
, struct pipe_surface
**bufs
)
217 struct stage s
[MAX_STAGES
];
218 uint32_t pos_regid
, posz_regid
, psize_regid
, color_regid
[8];
219 uint32_t face_regid
, coord_regid
, zwcoord_regid
;
223 debug_assert(nr
<= ARRAY_SIZE(color_regid
));
225 setup_stages(emit
, s
);
227 /* blob seems to always use constmode currently: */
230 pos_regid
= ir3_find_output_regid(s
[VS
].v
, VARYING_SLOT_POS
);
231 posz_regid
= ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DEPTH
);
232 psize_regid
= ir3_find_output_regid(s
[VS
].v
, VARYING_SLOT_PSIZ
);
233 if (s
[FS
].v
->color0_mrt
) {
234 color_regid
[0] = color_regid
[1] = color_regid
[2] = color_regid
[3] =
235 color_regid
[4] = color_regid
[5] = color_regid
[6] = color_regid
[7] =
236 ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_COLOR
);
238 color_regid
[0] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA0
);
239 color_regid
[1] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA1
);
240 color_regid
[2] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA2
);
241 color_regid
[3] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA3
);
242 color_regid
[4] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA4
);
243 color_regid
[5] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA5
);
244 color_regid
[6] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA6
);
245 color_regid
[7] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA7
);
248 /* TODO get these dynamically: */
249 face_regid
= s
[FS
].v
->frag_face
? regid(0,0) : regid(63,0);
250 coord_regid
= s
[FS
].v
->frag_coord
? regid(0,0) : regid(63,0);
251 zwcoord_regid
= s
[FS
].v
->frag_coord
? regid(0,2) : regid(63,0);
253 /* we could probably divide this up into things that need to be
254 * emitted if frag-prog is dirty vs if vert-prog is dirty..
257 OUT_PKT0(ring
, REG_A4XX_HLSQ_UPDATE_CONTROL
, 1);
258 OUT_RING(ring
, 0x00000003);
260 OUT_PKT0(ring
, REG_A4XX_HLSQ_CONTROL_0_REG
, 5);
261 OUT_RING(ring
, A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS
) |
262 A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(constmode
) |
263 A4XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE
|
264 /* NOTE: I guess SHADERRESTART and CONSTFULLUPDATE maybe
265 * flush some caches? I think we only need to set those
266 * bits if we have updated const or shader..
268 A4XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART
|
269 A4XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE
);
270 OUT_RING(ring
, A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS
) |
271 A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE
|
272 A4XX_HLSQ_CONTROL_1_REG_COORDREGID(coord_regid
) |
273 A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID(zwcoord_regid
));
274 OUT_RING(ring
, A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(63) |
275 0x3f3f000 | /* XXX */
276 A4XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid
));
277 OUT_RING(ring
, A4XX_HLSQ_CONTROL_3_REG_REGID(s
[FS
].v
->pos_regid
) |
279 OUT_RING(ring
, 0x00fcfcfc); /* XXX HLSQ_CONTROL_4 */
281 OUT_PKT0(ring
, REG_A4XX_HLSQ_VS_CONTROL_REG
, 5);
282 OUT_RING(ring
, A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(s
[VS
].constlen
) |
283 A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(s
[VS
].constoff
) |
284 A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(s
[VS
].instrlen
) |
285 A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(s
[VS
].instroff
));
286 OUT_RING(ring
, A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(s
[FS
].constlen
) |
287 A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(s
[FS
].constoff
) |
288 A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(s
[FS
].instrlen
) |
289 A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(s
[FS
].instroff
));
290 OUT_RING(ring
, A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(s
[HS
].constlen
) |
291 A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(s
[HS
].constoff
) |
292 A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(s
[HS
].instrlen
) |
293 A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(s
[HS
].instroff
));
294 OUT_RING(ring
, A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(s
[DS
].constlen
) |
295 A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(s
[DS
].constoff
) |
296 A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(s
[DS
].instrlen
) |
297 A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(s
[DS
].instroff
));
298 OUT_RING(ring
, A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(s
[GS
].constlen
) |
299 A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(s
[GS
].constoff
) |
300 A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(s
[GS
].instrlen
) |
301 A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(s
[GS
].instroff
));
303 OUT_PKT0(ring
, REG_A4XX_SP_SP_CTRL_REG
, 1);
304 OUT_RING(ring
, 0x140010 | /* XXX */
305 COND(emit
->key
.binning_pass
, A4XX_SP_SP_CTRL_REG_BINNING_PASS
));
307 OUT_PKT0(ring
, REG_A4XX_SP_INSTR_CACHE_CTRL
, 1);
308 OUT_RING(ring
, 0x7f | /* XXX */
309 COND(s
[VS
].instrlen
, A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER
) |
310 COND(s
[FS
].instrlen
, A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER
) |
311 COND(s
[VS
].instrlen
&& s
[FS
].instrlen
,
312 A4XX_SP_INSTR_CACHE_CTRL_INSTR_BUFFER
));
314 OUT_PKT0(ring
, REG_A4XX_SP_VS_LENGTH_REG
, 1);
315 OUT_RING(ring
, s
[VS
].v
->instrlen
); /* SP_VS_LENGTH_REG */
317 OUT_PKT0(ring
, REG_A4XX_SP_VS_CTRL_REG0
, 3);
318 OUT_RING(ring
, A4XX_SP_VS_CTRL_REG0_THREADMODE(MULTI
) |
319 A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(s
[VS
].i
->max_half_reg
+ 1) |
320 A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(s
[VS
].i
->max_reg
+ 1) |
321 A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(0) |
322 A4XX_SP_VS_CTRL_REG0_THREADSIZE(TWO_QUADS
) |
323 A4XX_SP_VS_CTRL_REG0_SUPERTHREADMODE
|
324 COND(s
[VS
].v
->has_samp
, A4XX_SP_VS_CTRL_REG0_PIXLODENABLE
));
325 OUT_RING(ring
, A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(s
[VS
].constlen
) |
326 A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(s
[VS
].v
->total_in
));
327 OUT_RING(ring
, A4XX_SP_VS_PARAM_REG_POSREGID(pos_regid
) |
328 A4XX_SP_VS_PARAM_REG_PSIZEREGID(psize_regid
) |
329 A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(align(s
[FS
].v
->total_in
, 4) / 4));
331 for (i
= 0, j
= -1; (i
< 16) && (j
< (int)s
[FS
].v
->inputs_count
); i
++) {
334 OUT_PKT0(ring
, REG_A4XX_SP_VS_OUT_REG(i
), 1);
336 j
= ir3_next_varying(s
[FS
].v
, j
);
337 if (j
< s
[FS
].v
->inputs_count
) {
338 k
= ir3_find_output(s
[VS
].v
, s
[FS
].v
->inputs
[j
].slot
);
339 reg
|= A4XX_SP_VS_OUT_REG_A_REGID(s
[VS
].v
->outputs
[k
].regid
);
340 reg
|= A4XX_SP_VS_OUT_REG_A_COMPMASK(s
[FS
].v
->inputs
[j
].compmask
);
343 j
= ir3_next_varying(s
[FS
].v
, j
);
344 if (j
< s
[FS
].v
->inputs_count
) {
345 k
= ir3_find_output(s
[VS
].v
, s
[FS
].v
->inputs
[j
].slot
);
346 reg
|= A4XX_SP_VS_OUT_REG_B_REGID(s
[VS
].v
->outputs
[k
].regid
);
347 reg
|= A4XX_SP_VS_OUT_REG_B_COMPMASK(s
[FS
].v
->inputs
[j
].compmask
);
353 for (i
= 0, j
= -1; (i
< 8) && (j
< (int)s
[FS
].v
->inputs_count
); i
++) {
356 OUT_PKT0(ring
, REG_A4XX_SP_VS_VPC_DST_REG(i
), 1);
358 j
= ir3_next_varying(s
[FS
].v
, j
);
359 if (j
< s
[FS
].v
->inputs_count
)
360 reg
|= A4XX_SP_VS_VPC_DST_REG_OUTLOC0(s
[FS
].v
->inputs
[j
].inloc
);
361 j
= ir3_next_varying(s
[FS
].v
, j
);
362 if (j
< s
[FS
].v
->inputs_count
)
363 reg
|= A4XX_SP_VS_VPC_DST_REG_OUTLOC1(s
[FS
].v
->inputs
[j
].inloc
);
364 j
= ir3_next_varying(s
[FS
].v
, j
);
365 if (j
< s
[FS
].v
->inputs_count
)
366 reg
|= A4XX_SP_VS_VPC_DST_REG_OUTLOC2(s
[FS
].v
->inputs
[j
].inloc
);
367 j
= ir3_next_varying(s
[FS
].v
, j
);
368 if (j
< s
[FS
].v
->inputs_count
)
369 reg
|= A4XX_SP_VS_VPC_DST_REG_OUTLOC3(s
[FS
].v
->inputs
[j
].inloc
);
374 OUT_PKT0(ring
, REG_A4XX_SP_VS_OBJ_OFFSET_REG
, 2);
375 OUT_RING(ring
, A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s
[VS
].constoff
) |
376 A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s
[VS
].instroff
));
377 OUT_RELOC(ring
, s
[VS
].v
->bo
, 0, 0, 0); /* SP_VS_OBJ_START_REG */
379 OUT_PKT0(ring
, REG_A4XX_SP_FS_LENGTH_REG
, 1);
380 OUT_RING(ring
, s
[FS
].v
->instrlen
); /* SP_FS_LENGTH_REG */
382 OUT_PKT0(ring
, REG_A4XX_SP_FS_CTRL_REG0
, 2);
383 OUT_RING(ring
, A4XX_SP_FS_CTRL_REG0_THREADMODE(MULTI
) |
384 COND(s
[FS
].v
->total_in
> 0, A4XX_SP_FS_CTRL_REG0_VARYING
) |
385 A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(s
[FS
].i
->max_half_reg
+ 1) |
386 A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s
[FS
].i
->max_reg
+ 1) |
387 A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(1) |
388 A4XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS
) |
389 A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE
|
390 COND(s
[FS
].v
->has_samp
, A4XX_SP_FS_CTRL_REG0_PIXLODENABLE
));
391 OUT_RING(ring
, A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(s
[FS
].constlen
) |
392 0x80000000 | /* XXX */
393 COND(s
[FS
].v
->frag_face
, A4XX_SP_FS_CTRL_REG1_FACENESS
) |
394 COND(s
[FS
].v
->total_in
> 0, A4XX_SP_FS_CTRL_REG1_VARYING
) |
395 COND(s
[FS
].v
->frag_coord
, A4XX_SP_FS_CTRL_REG1_FRAGCOORD
));
397 OUT_PKT0(ring
, REG_A4XX_SP_FS_OBJ_OFFSET_REG
, 2);
398 OUT_RING(ring
, A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s
[FS
].constoff
) |
399 A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s
[FS
].instroff
));
400 if (emit
->key
.binning_pass
)
401 OUT_RING(ring
, 0x00000000);
403 OUT_RELOC(ring
, s
[FS
].v
->bo
, 0, 0, 0); /* SP_FS_OBJ_START_REG */
405 OUT_PKT0(ring
, REG_A4XX_SP_HS_OBJ_OFFSET_REG
, 1);
406 OUT_RING(ring
, A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s
[HS
].constoff
) |
407 A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s
[HS
].instroff
));
409 OUT_PKT0(ring
, REG_A4XX_SP_DS_OBJ_OFFSET_REG
, 1);
410 OUT_RING(ring
, A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s
[DS
].constoff
) |
411 A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s
[DS
].instroff
));
413 OUT_PKT0(ring
, REG_A4XX_SP_GS_OBJ_OFFSET_REG
, 1);
414 OUT_RING(ring
, A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s
[GS
].constoff
) |
415 A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s
[GS
].instroff
));
417 OUT_PKT0(ring
, REG_A4XX_RB_RENDER_CONTROL2
, 1);
418 OUT_RING(ring
, A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(0) |
419 COND(s
[FS
].v
->total_in
> 0, A4XX_RB_RENDER_CONTROL2_VARYING
) |
420 COND(s
[FS
].v
->frag_face
, A4XX_RB_RENDER_CONTROL2_FACENESS
) |
421 COND(s
[FS
].v
->frag_coord
, A4XX_RB_RENDER_CONTROL2_XCOORD
|
422 A4XX_RB_RENDER_CONTROL2_YCOORD
|
423 // TODO enabling gl_FragCoord.z is causing lockups on 0ad (but seems
424 // to work everywhere else).
425 // A4XX_RB_RENDER_CONTROL2_ZCOORD |
426 A4XX_RB_RENDER_CONTROL2_WCOORD
));
428 OUT_PKT0(ring
, REG_A4XX_RB_FS_OUTPUT_REG
, 1);
429 OUT_RING(ring
, A4XX_RB_FS_OUTPUT_REG_MRT(MAX2(1, nr
)) |
430 COND(s
[FS
].v
->writes_pos
, A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z
));
432 OUT_PKT0(ring
, REG_A4XX_SP_FS_OUTPUT_REG
, 1);
433 OUT_RING(ring
, A4XX_SP_FS_OUTPUT_REG_MRT(MAX2(1, nr
)) |
434 COND(s
[FS
].v
->writes_pos
, A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE
) |
435 A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(posz_regid
));
437 OUT_PKT0(ring
, REG_A4XX_SP_FS_MRT_REG(0), 8);
438 for (i
= 0; i
< 8; i
++) {
439 enum a4xx_color_fmt format
= 0;
442 format
= fd4_emit_format(bufs
[i
]);
443 if (bufs
[i
] && !emit
->no_decode_srgb
)
444 srgb
= util_format_is_srgb(bufs
[i
]->format
);
446 OUT_RING(ring
, A4XX_SP_FS_MRT_REG_REGID(color_regid
[i
]) |
447 A4XX_SP_FS_MRT_REG_MRTFORMAT(format
) |
448 COND(srgb
, A4XX_SP_FS_MRT_REG_COLOR_SRGB
) |
449 COND(emit
->key
.half_precision
,
450 A4XX_SP_FS_MRT_REG_HALF_PRECISION
));
453 if (emit
->key
.binning_pass
) {
454 OUT_PKT0(ring
, REG_A4XX_VPC_ATTR
, 2);
455 OUT_RING(ring
, A4XX_VPC_ATTR_THRDASSIGN(1) |
456 0x40000000 | /* XXX */
457 COND(s
[VS
].v
->writes_psize
, A4XX_VPC_ATTR_PSIZE
));
458 OUT_RING(ring
, 0x00000000);
460 uint32_t vinterp
[8], vpsrepl
[8];
462 memset(vinterp
, 0, sizeof(vinterp
));
463 memset(vpsrepl
, 0, sizeof(vpsrepl
));
465 /* looks like we need to do int varyings in the frag
466 * shader on a4xx (no flatshad reg? or a420.0 bug?):
469 * (sy)ldlv.u32 r0.x,l[r0.x], 1
470 * ldlv.u32 r0.y,l[r0.x+1], 1
471 * (ss)bary.f (ei)r63.x, 0, r0.x
472 * (ss)(rpt1)cov.s32f16 hr0.x, (r)r0.x
474 * sam (f16)(xyzw)hr0.x, hr0.x, s#0, t#0
476 * Possibly on later a4xx variants we'll be able to use
477 * something like the code below instead of workaround
480 /* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
481 for (j
= -1; (j
= ir3_next_varying(s
[FS
].v
, j
)) < (int)s
[FS
].v
->inputs_count
; ) {
483 /* TODO might be cleaner to just +8 in SP_VS_VPC_DST_REG
484 * instead.. rather than -8 everywhere else..
486 uint32_t inloc
= s
[FS
].v
->inputs
[j
].inloc
- 8;
488 /* currently assuming varyings aligned to 4 (not
491 debug_assert((inloc
% 4) == 0);
493 if ((s
[FS
].v
->inputs
[j
].interpolate
== INTERP_QUALIFIER_FLAT
) ||
494 (s
[FS
].v
->inputs
[j
].rasterflat
&& emit
->rasterflat
)) {
495 uint32_t loc
= inloc
;
497 for (i
= 0; i
< 4; i
++, loc
++) {
498 vinterp
[loc
/ 16] |= 1 << ((loc
% 16) * 2);
499 //flatshade[loc / 32] |= 1 << (loc % 32);
503 gl_varying_slot slot
= s
[FS
].v
->inputs
[j
].slot
;
505 /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
506 if (slot
>= VARYING_SLOT_VAR0
) {
507 unsigned texmask
= 1 << (slot
- VARYING_SLOT_VAR0
);
508 /* Replace the .xy coordinates with S/T from the point sprite. Set
509 * interpolation bits for .zw such that they become .01
511 if (emit
->sprite_coord_enable
& texmask
) {
512 vpsrepl
[inloc
/ 16] |= (emit
->sprite_coord_mode
? 0x0d : 0x09)
513 << ((inloc
% 16) * 2);
514 vinterp
[(inloc
+ 2) / 16] |= 2 << (((inloc
+ 2) % 16) * 2);
515 vinterp
[(inloc
+ 3) / 16] |= 3 << (((inloc
+ 3) % 16) * 2);
520 OUT_PKT0(ring
, REG_A4XX_VPC_ATTR
, 2);
521 OUT_RING(ring
, A4XX_VPC_ATTR_TOTALATTR(s
[FS
].v
->total_in
) |
522 A4XX_VPC_ATTR_THRDASSIGN(1) |
523 COND(s
[FS
].v
->total_in
> 0, A4XX_VPC_ATTR_ENABLE
) |
524 0x40000000 | /* XXX */
525 COND(s
[VS
].v
->writes_psize
, A4XX_VPC_ATTR_PSIZE
));
526 OUT_RING(ring
, A4XX_VPC_PACK_NUMFPNONPOSVAR(s
[FS
].v
->total_in
) |
527 A4XX_VPC_PACK_NUMNONPOSVSVAR(s
[FS
].v
->total_in
));
529 OUT_PKT0(ring
, REG_A4XX_VPC_VARYING_INTERP_MODE(0), 8);
530 for (i
= 0; i
< 8; i
++)
531 OUT_RING(ring
, vinterp
[i
]); /* VPC_VARYING_INTERP[i].MODE */
533 OUT_PKT0(ring
, REG_A4XX_VPC_VARYING_PS_REPL_MODE(0), 8);
534 for (i
= 0; i
< 8; i
++)
535 OUT_RING(ring
, vpsrepl
[i
]); /* VPC_VARYING_PS_REPL[i] */
539 emit_shader(ring
, s
[VS
].v
);
541 if (!emit
->key
.binning_pass
)
543 emit_shader(ring
, s
[FS
].v
);
547 fd4_prog_init(struct pipe_context
*pctx
)
549 pctx
->create_fs_state
= fd4_fp_state_create
;
550 pctx
->delete_fs_state
= fd4_fp_state_delete
;
552 pctx
->create_vs_state
= fd4_vp_state_create
;
553 pctx
->delete_vs_state
= fd4_vp_state_delete
;