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freedreno/a6xx: Split clear and blit texture into different functions
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_blitter.c
1 /*
2 * Copyright (C) 2017 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include "util/u_dump.h"
29 #include "util/half_float.h"
30
31 #include "freedreno_blitter.h"
32 #include "freedreno_fence.h"
33 #include "freedreno_log.h"
34 #include "freedreno_resource.h"
35
36 #include "fd6_blitter.h"
37 #include "fd6_format.h"
38 #include "fd6_emit.h"
39 #include "fd6_resource.h"
40 #include "fd6_pack.h"
41
42 static inline enum a6xx_2d_ifmt
43 fd6_ifmt(enum a6xx_format fmt)
44 {
45 switch (fmt) {
46 case FMT6_A8_UNORM:
47 case FMT6_8_UNORM:
48 case FMT6_8_SNORM:
49 case FMT6_8_8_UNORM:
50 case FMT6_8_8_SNORM:
51 case FMT6_8_8_8_8_UNORM:
52 case FMT6_8_8_8_X8_UNORM:
53 case FMT6_8_8_8_8_SNORM:
54 case FMT6_4_4_4_4_UNORM:
55 case FMT6_5_5_5_1_UNORM:
56 case FMT6_5_6_5_UNORM:
57 return R2D_UNORM8;
58
59 case FMT6_32_UINT:
60 case FMT6_32_SINT:
61 case FMT6_32_32_UINT:
62 case FMT6_32_32_SINT:
63 case FMT6_32_32_32_32_UINT:
64 case FMT6_32_32_32_32_SINT:
65 return R2D_INT32;
66
67 case FMT6_16_UINT:
68 case FMT6_16_SINT:
69 case FMT6_16_16_UINT:
70 case FMT6_16_16_SINT:
71 case FMT6_16_16_16_16_UINT:
72 case FMT6_16_16_16_16_SINT:
73 case FMT6_10_10_10_2_UINT:
74 return R2D_INT16;
75
76 case FMT6_8_UINT:
77 case FMT6_8_SINT:
78 case FMT6_8_8_UINT:
79 case FMT6_8_8_SINT:
80 case FMT6_8_8_8_8_UINT:
81 case FMT6_8_8_8_8_SINT:
82 case FMT6_Z24_UNORM_S8_UINT:
83 case FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8:
84 return R2D_INT8;
85
86 case FMT6_16_UNORM:
87 case FMT6_16_SNORM:
88 case FMT6_16_16_UNORM:
89 case FMT6_16_16_SNORM:
90 case FMT6_16_16_16_16_UNORM:
91 case FMT6_16_16_16_16_SNORM:
92 case FMT6_32_FLOAT:
93 case FMT6_32_32_FLOAT:
94 case FMT6_32_32_32_32_FLOAT:
95 return R2D_FLOAT32;
96
97 case FMT6_16_FLOAT:
98 case FMT6_16_16_FLOAT:
99 case FMT6_16_16_16_16_FLOAT:
100 case FMT6_11_11_10_FLOAT:
101 case FMT6_10_10_10_2_UNORM_DEST:
102 return R2D_FLOAT16;
103
104 default:
105 unreachable("bad format");
106 return 0;
107 }
108 }
109
110 /* Make sure none of the requested dimensions extend beyond the size of the
111 * resource. Not entirely sure why this happens, but sometimes it does, and
112 * w/ 2d blt doesn't have wrap modes like a sampler, so force those cases
113 * back to u_blitter
114 */
115 static bool
116 ok_dims(const struct pipe_resource *r, const struct pipe_box *b, int lvl)
117 {
118 int last_layer =
119 r->target == PIPE_TEXTURE_3D ? u_minify(r->depth0, lvl)
120 : r->array_size;
121
122 return (b->x >= 0) && (b->x + b->width <= u_minify(r->width0, lvl)) &&
123 (b->y >= 0) && (b->y + b->height <= u_minify(r->height0, lvl)) &&
124 (b->z >= 0) && (b->z + b->depth <= last_layer);
125 }
126
127 static bool
128 ok_format(enum pipe_format pfmt)
129 {
130 enum a6xx_format fmt = fd6_pipe2color(pfmt);
131
132 if (util_format_is_compressed(pfmt))
133 return true;
134
135 switch (pfmt) {
136 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
137 case PIPE_FORMAT_Z24X8_UNORM:
138 case PIPE_FORMAT_Z16_UNORM:
139 case PIPE_FORMAT_Z32_UNORM:
140 case PIPE_FORMAT_Z32_FLOAT:
141 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
142 case PIPE_FORMAT_S8_UINT:
143 return true;
144 default:
145 break;
146 }
147
148 if (fmt == FMT6_NONE)
149 return false;
150
151 return true;
152 }
153
154 #define DEBUG_BLIT 0
155 #define DEBUG_BLIT_FALLBACK 0
156
157 #define fail_if(cond) \
158 do { \
159 if (cond) { \
160 if (DEBUG_BLIT_FALLBACK) { \
161 fprintf(stderr, "falling back: %s for blit:\n", #cond); \
162 util_dump_blit_info(stderr, info); \
163 fprintf(stderr, "\nsrc: "); \
164 util_dump_resource(stderr, info->src.resource); \
165 fprintf(stderr, "\ndst: "); \
166 util_dump_resource(stderr, info->dst.resource); \
167 fprintf(stderr, "\n"); \
168 } \
169 return false; \
170 } \
171 } while (0)
172
173 static bool
174 can_do_blit(const struct pipe_blit_info *info)
175 {
176 /* I think we can do scaling, but not in z dimension since that would
177 * require blending..
178 */
179 fail_if(info->dst.box.depth != info->src.box.depth);
180
181 /* Fail if unsupported format: */
182 fail_if(!ok_format(info->src.format));
183 fail_if(!ok_format(info->dst.format));
184
185 debug_assert(!util_format_is_compressed(info->src.format));
186 debug_assert(!util_format_is_compressed(info->dst.format));
187
188 fail_if(!ok_dims(info->src.resource, &info->src.box, info->src.level));
189
190 fail_if(!ok_dims(info->dst.resource, &info->dst.box, info->dst.level));
191
192 debug_assert(info->dst.box.width >= 0);
193 debug_assert(info->dst.box.height >= 0);
194 debug_assert(info->dst.box.depth >= 0);
195
196 fail_if(info->dst.resource->nr_samples > 1);
197
198 fail_if(info->window_rectangle_include);
199
200 const struct util_format_description *src_desc =
201 util_format_description(info->src.format);
202 const struct util_format_description *dst_desc =
203 util_format_description(info->dst.format);
204 const int common_channels = MIN2(src_desc->nr_channels, dst_desc->nr_channels);
205
206 if (info->mask & PIPE_MASK_RGBA) {
207 for (int i = 0; i < common_channels; i++) {
208 fail_if(memcmp(&src_desc->channel[i],
209 &dst_desc->channel[i],
210 sizeof(src_desc->channel[0])));
211 }
212 }
213
214 fail_if(info->alpha_blend);
215
216 return true;
217 }
218
219 static void
220 emit_setup(struct fd_batch *batch)
221 {
222 struct fd_ringbuffer *ring = batch->draw;
223
224 fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
225 fd6_event_write(batch, ring, PC_CCU_FLUSH_DEPTH_TS, true);
226 fd6_event_write(batch, ring, PC_CCU_INVALIDATE_COLOR, false);
227 fd6_event_write(batch, ring, PC_CCU_INVALIDATE_DEPTH, false);
228
229 /* normal BLIT_OP_SCALE operation needs bypass RB_CCU_CNTL */
230 OUT_WFI5(ring);
231 OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
232 OUT_RING(ring, fd6_context(batch->ctx)->magic.RB_CCU_CNTL_bypass);
233 }
234
235 static void
236 emit_blit_setup(struct fd_ringbuffer *ring,
237 enum pipe_format pfmt, bool scissor_enable, union pipe_color_union *color)
238 {
239 enum a6xx_format fmt = fd6_pipe2color(pfmt);
240 bool is_srgb = util_format_is_srgb(pfmt);
241 enum a6xx_2d_ifmt ifmt = fd6_ifmt(fmt);
242
243 OUT_PKT7(ring, CP_SET_MARKER, 1);
244 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE));
245
246 if (is_srgb) {
247 assert(ifmt == R2D_UNORM8);
248 ifmt = R2D_UNORM8_SRGB;
249 }
250
251 uint32_t blit_cntl = A6XX_RB_2D_BLIT_CNTL_MASK(0xf) |
252 A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(fmt) |
253 A6XX_RB_2D_BLIT_CNTL_IFMT(ifmt) |
254 COND(color, A6XX_RB_2D_BLIT_CNTL_SOLID_COLOR) |
255 COND(scissor_enable, A6XX_RB_2D_BLIT_CNTL_SCISSOR);
256
257 OUT_PKT4(ring, REG_A6XX_RB_2D_BLIT_CNTL, 1);
258 OUT_RING(ring, blit_cntl);
259
260 OUT_PKT4(ring, REG_A6XX_GRAS_2D_BLIT_CNTL, 1);
261 OUT_RING(ring, blit_cntl);
262
263 if (fmt == FMT6_10_10_10_2_UNORM_DEST)
264 fmt = FMT6_16_16_16_16_FLOAT;
265
266 /* This register is probably badly named... it seems that it's
267 * controlling the internal/accumulator format or something like
268 * that. It's certainly not tied to only the src format.
269 */
270 OUT_PKT4(ring, REG_A6XX_SP_2D_SRC_FORMAT, 1);
271 OUT_RING(ring, A6XX_SP_2D_SRC_FORMAT_COLOR_FORMAT(fmt) |
272 COND(util_format_is_pure_sint(pfmt),
273 A6XX_SP_2D_SRC_FORMAT_SINT) |
274 COND(util_format_is_pure_uint(pfmt),
275 A6XX_SP_2D_SRC_FORMAT_UINT) |
276 COND(util_format_is_snorm(pfmt),
277 A6XX_SP_2D_SRC_FORMAT_SINT |
278 A6XX_SP_2D_SRC_FORMAT_NORM) |
279 COND(util_format_is_unorm(pfmt),
280 // TODO sometimes blob uses UINT+NORM but dEQP seems unhappy about that
281 // A6XX_SP_2D_SRC_FORMAT_UINT |
282 A6XX_SP_2D_SRC_FORMAT_NORM) |
283 COND(is_srgb, A6XX_SP_2D_SRC_FORMAT_SRGB) |
284 A6XX_SP_2D_SRC_FORMAT_MASK(0xf));
285
286 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8C01, 1);
287 OUT_RING(ring, 0);
288 }
289
290 /* buffers need to be handled specially since x/width can exceed the bounds
291 * supported by hw.. if necessary decompose into (potentially) two 2D blits
292 */
293 static void
294 emit_blit_buffer(struct fd_context *ctx, struct fd_ringbuffer *ring,
295 const struct pipe_blit_info *info)
296 {
297 const struct pipe_box *sbox = &info->src.box;
298 const struct pipe_box *dbox = &info->dst.box;
299 struct fd_resource *src, *dst;
300 unsigned sshift, dshift;
301
302 if (DEBUG_BLIT) {
303 fprintf(stderr, "buffer blit: ");
304 util_dump_blit_info(stderr, info);
305 fprintf(stderr, "\ndst resource: ");
306 util_dump_resource(stderr, info->dst.resource);
307 fprintf(stderr, "\nsrc resource: ");
308 util_dump_resource(stderr, info->src.resource);
309 fprintf(stderr, "\n");
310 }
311
312 src = fd_resource(info->src.resource);
313 dst = fd_resource(info->dst.resource);
314
315 debug_assert(src->layout.cpp == 1);
316 debug_assert(dst->layout.cpp == 1);
317 debug_assert(info->src.resource->format == info->dst.resource->format);
318 debug_assert((sbox->y == 0) && (sbox->height == 1));
319 debug_assert((dbox->y == 0) && (dbox->height == 1));
320 debug_assert((sbox->z == 0) && (sbox->depth == 1));
321 debug_assert((dbox->z == 0) && (dbox->depth == 1));
322 debug_assert(sbox->width == dbox->width);
323 debug_assert(info->src.level == 0);
324 debug_assert(info->dst.level == 0);
325
326 /*
327 * Buffers can have dimensions bigger than max width, remap into
328 * multiple 1d blits to fit within max dimension
329 *
330 * Note that blob uses .ARRAY_PITCH=128 for blitting buffers, which
331 * seems to prevent overfetch related faults. Not quite sure what
332 * the deal is there.
333 *
334 * Low 6 bits of SRC/DST addresses need to be zero (ie. address
335 * aligned to 64) so we need to shift src/dst x1/x2 to make up the
336 * difference. On top of already splitting up the blit so width
337 * isn't > 16k.
338 *
339 * We perhaps could do a bit better, if src and dst are aligned but
340 * in the worst case this means we have to split the copy up into
341 * 16k (0x4000) minus 64 (0x40).
342 */
343
344 sshift = sbox->x & 0x3f;
345 dshift = dbox->x & 0x3f;
346
347 emit_blit_setup(ring, PIPE_FORMAT_R8_UNORM, false, NULL);
348
349 for (unsigned off = 0; off < sbox->width; off += (0x4000 - 0x40)) {
350 unsigned soff, doff, w, p;
351
352 soff = (sbox->x + off) & ~0x3f;
353 doff = (dbox->x + off) & ~0x3f;
354
355 w = MIN2(sbox->width - off, (0x4000 - 0x40));
356 p = align(w, 64);
357
358 debug_assert((soff + w) <= fd_bo_size(src->bo));
359 debug_assert((doff + w) <= fd_bo_size(dst->bo));
360
361 /*
362 * Emit source:
363 */
364 OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_INFO, 10);
365 OUT_RING(ring, A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(FMT6_8_UNORM) |
366 A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(TILE6_LINEAR) |
367 A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(WZYX) |
368 0x500000);
369 OUT_RING(ring, A6XX_SP_PS_2D_SRC_SIZE_WIDTH(sshift + w) |
370 A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(1)); /* SP_PS_2D_SRC_SIZE */
371 OUT_RELOC(ring, src->bo, soff, 0, 0); /* SP_PS_2D_SRC_LO/HI */
372 OUT_RING(ring, A6XX_SP_PS_2D_SRC_PITCH_PITCH(p));
373
374 OUT_RING(ring, 0x00000000);
375 OUT_RING(ring, 0x00000000);
376 OUT_RING(ring, 0x00000000);
377 OUT_RING(ring, 0x00000000);
378 OUT_RING(ring, 0x00000000);
379
380 /*
381 * Emit destination:
382 */
383 OUT_PKT4(ring, REG_A6XX_RB_2D_DST_INFO, 9);
384 OUT_RING(ring, A6XX_RB_2D_DST_INFO_COLOR_FORMAT(FMT6_8_UNORM) |
385 A6XX_RB_2D_DST_INFO_TILE_MODE(TILE6_LINEAR) |
386 A6XX_RB_2D_DST_INFO_COLOR_SWAP(WZYX));
387 OUT_RELOC(ring, dst->bo, doff, 0, 0); /* RB_2D_DST_LO/HI */
388 OUT_RING(ring, A6XX_RB_2D_DST_SIZE_PITCH(p));
389 OUT_RING(ring, 0x00000000);
390 OUT_RING(ring, 0x00000000);
391 OUT_RING(ring, 0x00000000);
392 OUT_RING(ring, 0x00000000);
393 OUT_RING(ring, 0x00000000);
394
395 /*
396 * Blit command:
397 */
398 OUT_PKT4(ring, REG_A6XX_GRAS_2D_SRC_TL_X, 4);
399 OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_X_X(sshift));
400 OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_X_X(sshift + w - 1));
401 OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_Y_Y(0));
402 OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_Y_Y(0));
403
404 OUT_PKT4(ring, REG_A6XX_GRAS_2D_DST_TL, 2);
405 OUT_RING(ring, A6XX_GRAS_2D_DST_TL_X(dshift) | A6XX_GRAS_2D_DST_TL_Y(0));
406 OUT_RING(ring, A6XX_GRAS_2D_DST_BR_X(dshift + w - 1) | A6XX_GRAS_2D_DST_BR_Y(0));
407
408 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
409 OUT_RING(ring, 0x3f);
410 OUT_WFI5(ring);
411
412 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
413 OUT_RING(ring, fd6_context(ctx)->magic.RB_UNKNOWN_8E04_blit);
414
415 OUT_PKT7(ring, CP_BLIT, 1);
416 OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
417
418 OUT_WFI5(ring);
419
420 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
421 OUT_RING(ring, 0); /* RB_UNKNOWN_8E04 */
422 }
423 }
424
425 static void
426 emit_blit_dst(struct fd_ringbuffer *ring, struct pipe_resource *prsc, enum pipe_format pfmt, unsigned level, unsigned layer)
427 {
428 struct fd_resource *dst = fd_resource(prsc);
429 enum a6xx_format fmt = fd6_pipe2color(pfmt);
430 enum a6xx_tile_mode tile = fd_resource_tile_mode(prsc, level);
431 enum a3xx_color_swap swap = fd6_resource_swap(dst, pfmt);
432 uint32_t pitch = fd_resource_pitch(dst, level);
433 bool ubwc_enabled = fd_resource_ubwc_enabled(dst, level);
434 unsigned off = fd_resource_offset(dst, level, layer);
435
436 if (fmt == FMT6_Z24_UNORM_S8_UINT)
437 fmt = FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8;
438
439 OUT_PKT4(ring, REG_A6XX_RB_2D_DST_INFO, 9);
440 OUT_RING(ring, A6XX_RB_2D_DST_INFO_COLOR_FORMAT(fmt) |
441 A6XX_RB_2D_DST_INFO_TILE_MODE(tile) |
442 A6XX_RB_2D_DST_INFO_COLOR_SWAP(swap) |
443 COND(util_format_is_srgb(pfmt), A6XX_RB_2D_DST_INFO_SRGB) |
444 COND(ubwc_enabled, A6XX_RB_2D_DST_INFO_FLAGS));
445 OUT_RELOC(ring, dst->bo, off, 0, 0); /* RB_2D_DST_LO/HI */
446 OUT_RING(ring, A6XX_RB_2D_DST_SIZE_PITCH(pitch));
447 OUT_RING(ring, 0x00000000);
448 OUT_RING(ring, 0x00000000);
449 OUT_RING(ring, 0x00000000);
450 OUT_RING(ring, 0x00000000);
451 OUT_RING(ring, 0x00000000);
452
453 if (ubwc_enabled) {
454 OUT_PKT4(ring, REG_A6XX_RB_2D_DST_FLAGS_LO, 6);
455 fd6_emit_flag_reference(ring, dst, level, layer);
456 OUT_RING(ring, 0x00000000);
457 OUT_RING(ring, 0x00000000);
458 OUT_RING(ring, 0x00000000);
459 }
460 }
461
462 static void
463 emit_blit_src(struct fd_ringbuffer *ring, const struct pipe_blit_info *info, unsigned layer, unsigned nr_samples)
464 {
465 struct fd_resource *src = fd_resource(info->src.resource);
466 enum a6xx_format sfmt = fd6_pipe2color(info->src.format);
467 enum a6xx_tile_mode stile = fd_resource_tile_mode(info->src.resource, info->src.level);
468 enum a3xx_color_swap sswap = fd6_resource_swap(src, info->src.format);
469 uint32_t pitch = fd_resource_pitch(src, info->src.level);
470 bool subwc_enabled = fd_resource_ubwc_enabled(src, info->src.level);
471 unsigned soff = fd_resource_offset(src, info->src.level, layer);
472 uint32_t width = u_minify(src->base.width0, info->src.level) * nr_samples;
473 uint32_t height = u_minify(src->base.height0, info->src.level);
474 uint32_t filter = 0;
475
476 if (info->filter == PIPE_TEX_FILTER_LINEAR)
477 filter = A6XX_SP_PS_2D_SRC_INFO_FILTER;
478
479 enum a3xx_msaa_samples samples = fd_msaa_samples(src->base.nr_samples);
480
481 if (sfmt == FMT6_10_10_10_2_UNORM_DEST)
482 sfmt = FMT6_10_10_10_2_UNORM;
483
484 OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_INFO, 10);
485 OUT_RING(ring, A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(sfmt) |
486 A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(stile) |
487 A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(sswap) |
488 A6XX_SP_PS_2D_SRC_INFO_SAMPLES(samples) |
489 COND(samples > MSAA_ONE && (info->mask & PIPE_MASK_RGBA),
490 A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE) |
491 COND(subwc_enabled, A6XX_SP_PS_2D_SRC_INFO_FLAGS) |
492 COND(util_format_is_srgb(info->src.format), A6XX_SP_PS_2D_SRC_INFO_SRGB) |
493 0x500000 | filter);
494 OUT_RING(ring, A6XX_SP_PS_2D_SRC_SIZE_WIDTH(width) |
495 A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(height)); /* SP_PS_2D_SRC_SIZE */
496 OUT_RELOC(ring, src->bo, soff, 0, 0); /* SP_PS_2D_SRC_LO/HI */
497 OUT_RING(ring, A6XX_SP_PS_2D_SRC_PITCH_PITCH(pitch));
498
499 OUT_RING(ring, 0x00000000);
500 OUT_RING(ring, 0x00000000);
501 OUT_RING(ring, 0x00000000);
502 OUT_RING(ring, 0x00000000);
503 OUT_RING(ring, 0x00000000);
504
505 if (subwc_enabled) {
506 OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_FLAGS_LO, 6);
507 fd6_emit_flag_reference(ring, src, info->src.level, layer);
508 OUT_RING(ring, 0x00000000);
509 OUT_RING(ring, 0x00000000);
510 OUT_RING(ring, 0x00000000);
511 }
512 }
513
514 static void
515 emit_blit_texture(struct fd_context *ctx,
516 struct fd_ringbuffer *ring, const struct pipe_blit_info *info)
517 {
518 const struct pipe_box *sbox = &info->src.box;
519 const struct pipe_box *dbox = &info->dst.box;
520 struct fd_resource *dst;
521 int sx1, sy1, sx2, sy2;
522 int dx1, dy1, dx2, dy2;
523
524 if (DEBUG_BLIT) {
525 fprintf(stderr, "texture blit: ");
526 util_dump_blit_info(stderr, info);
527 fprintf(stderr, "\ndst resource: ");
528 util_dump_resource(stderr, info->dst.resource);
529 fprintf(stderr, "\nsrc resource: ");
530 util_dump_resource(stderr, info->src.resource);
531 fprintf(stderr, "\n");
532 }
533
534 dst = fd_resource(info->dst.resource);
535
536 uint32_t nr_samples = fd_resource_nr_samples(&dst->base);
537
538 sx1 = sbox->x * nr_samples;
539 sy1 = sbox->y;
540 sx2 = (sbox->x + sbox->width) * nr_samples - 1;
541 sy2 = sbox->y + sbox->height - 1;
542
543 OUT_PKT4(ring, REG_A6XX_GRAS_2D_SRC_TL_X, 4);
544 OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_X_X(sx1));
545 OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_X_X(sx2));
546 OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_Y_Y(sy1));
547 OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_Y_Y(sy2));
548
549 dx1 = dbox->x * nr_samples;
550 dy1 = dbox->y;
551 dx2 = (dbox->x + dbox->width) * nr_samples - 1;
552 dy2 = dbox->y + dbox->height - 1;
553
554 OUT_PKT4(ring, REG_A6XX_GRAS_2D_DST_TL, 2);
555 OUT_RING(ring, A6XX_GRAS_2D_DST_TL_X(dx1) | A6XX_GRAS_2D_DST_TL_Y(dy1));
556 OUT_RING(ring, A6XX_GRAS_2D_DST_BR_X(dx2) | A6XX_GRAS_2D_DST_BR_Y(dy2));
557
558 if (info->scissor_enable) {
559 OUT_PKT4(ring, REG_A6XX_GRAS_RESOLVE_CNTL_1, 2);
560 OUT_RING(ring, A6XX_GRAS_RESOLVE_CNTL_1_X(info->scissor.minx) |
561 A6XX_GRAS_RESOLVE_CNTL_1_Y(info->scissor.miny));
562 OUT_RING(ring, A6XX_GRAS_RESOLVE_CNTL_1_X(info->scissor.maxx - 1) |
563 A6XX_GRAS_RESOLVE_CNTL_1_Y(info->scissor.maxy - 1));
564 }
565
566 emit_blit_setup(ring, info->dst.format, info->scissor_enable, NULL);
567
568 for (unsigned i = 0; i < info->dst.box.depth; i++) {
569
570 emit_blit_src(ring, info, sbox->z + i, nr_samples);
571 emit_blit_dst(ring, info->dst.resource, info->dst.format, info->dst.level, dbox->z + i);
572
573 /*
574 * Blit command:
575 */
576 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
577 OUT_RING(ring, 0x3f);
578 OUT_WFI5(ring);
579
580 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
581 OUT_RING(ring, fd6_context(ctx)->magic.RB_UNKNOWN_8E04_blit);
582
583 OUT_PKT7(ring, CP_BLIT, 1);
584 OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
585
586 OUT_WFI5(ring);
587
588 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
589 OUT_RING(ring, 0); /* RB_UNKNOWN_8E04 */
590 }
591 }
592
593 static void
594 emit_clear_color(struct fd_ringbuffer *ring,
595 enum pipe_format pfmt, union pipe_color_union *color)
596 {
597 switch (pfmt) {
598 case PIPE_FORMAT_Z24X8_UNORM:
599 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
600 case PIPE_FORMAT_X24S8_UINT: {
601 uint32_t depth_unorm24 = color->f[0] * ((1u << 24) - 1);
602 uint8_t stencil = color->ui[1];
603 color->ui[0] = depth_unorm24 & 0xff;
604 color->ui[1] = (depth_unorm24 >> 8) & 0xff;
605 color->ui[2] = (depth_unorm24 >> 16) & 0xff;
606 color->ui[3] = stencil;
607 break;
608 }
609 default:
610 break;
611 }
612
613 OUT_PKT4(ring, REG_A6XX_RB_2D_SRC_SOLID_C0, 4);
614 switch (fd6_ifmt(fd6_pipe2color(pfmt))) {
615 case R2D_UNORM8:
616 case R2D_UNORM8_SRGB:
617 OUT_RING(ring, float_to_ubyte(color->f[0]));
618 OUT_RING(ring, float_to_ubyte(color->f[1]));
619 OUT_RING(ring, float_to_ubyte(color->f[2]));
620 OUT_RING(ring, float_to_ubyte(color->f[3]));
621 break;
622 case R2D_FLOAT16:
623 OUT_RING(ring, _mesa_float_to_half(color->f[0]));
624 OUT_RING(ring, _mesa_float_to_half(color->f[1]));
625 OUT_RING(ring, _mesa_float_to_half(color->f[2]));
626 OUT_RING(ring, _mesa_float_to_half(color->f[3]));
627 break;
628 case R2D_FLOAT32:
629 case R2D_INT32:
630 case R2D_INT16:
631 case R2D_INT8:
632 default:
633 OUT_RING(ring, color->ui[0]);
634 OUT_RING(ring, color->ui[1]);
635 OUT_RING(ring, color->ui[2]);
636 OUT_RING(ring, color->ui[3]);
637 break;
638 }
639 }
640
641 void
642 fd6_clear_surface(struct fd_context *ctx,
643 struct fd_ringbuffer *ring, struct pipe_surface *psurf,
644 uint32_t width, uint32_t height, union pipe_color_union *color)
645 {
646 if (DEBUG_BLIT) {
647 fprintf(stderr, "surface clear:\ndst resource: ");
648 util_dump_resource(stderr, psurf->texture);
649 fprintf(stderr, "\n");
650 }
651
652 uint32_t nr_samples = fd_resource_nr_samples(psurf->texture);
653 OUT_PKT4(ring, REG_A6XX_GRAS_2D_DST_TL, 2);
654 OUT_RING(ring, A6XX_GRAS_2D_DST_TL_X(0) | A6XX_GRAS_2D_DST_TL_Y(0));
655 OUT_RING(ring, A6XX_GRAS_2D_DST_BR_X(width * nr_samples - 1) |
656 A6XX_GRAS_2D_DST_BR_Y(height - 1));
657
658 emit_clear_color(ring, psurf->format, color);
659 emit_blit_setup(ring, psurf->format, false, color);
660
661 for (unsigned i = psurf->u.tex.first_layer; i <= psurf->u.tex.last_layer; i++) {
662 emit_blit_dst(ring, psurf->texture, psurf->format, psurf->u.tex.level, i);
663
664 /*
665 * Blit command:
666 */
667 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
668 OUT_RING(ring, 0x3f);
669 OUT_WFI5(ring);
670
671 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
672 OUT_RING(ring, fd6_context(ctx)->magic.RB_UNKNOWN_8E04_blit);
673
674 OUT_PKT7(ring, CP_BLIT, 1);
675 OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
676
677 OUT_WFI5(ring);
678
679 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
680 OUT_RING(ring, 0); /* RB_UNKNOWN_8E04 */
681 }
682 }
683
684 static bool
685 handle_rgba_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
686 {
687 struct fd_batch *batch;
688
689 debug_assert(!(info->mask & PIPE_MASK_ZS));
690
691 if (!can_do_blit(info))
692 return false;
693
694 batch = fd_bc_alloc_batch(&ctx->screen->batch_cache, ctx, true);
695
696 fd6_emit_restore(batch, batch->draw);
697 fd6_emit_lrz_flush(batch->draw);
698
699 fd_screen_lock(ctx->screen);
700
701 fd_batch_resource_read(batch, fd_resource(info->src.resource));
702 fd_batch_resource_write(batch, fd_resource(info->dst.resource));
703
704 fd_screen_unlock(ctx->screen);
705
706 /* Clearing last_fence must come after the batch dependency tracking
707 * (resource_read()/resource_write()), as that can trigger a flush,
708 * re-populating last_fence
709 */
710 fd_fence_ref(&ctx->last_fence, NULL);
711
712 fd_batch_set_stage(batch, FD_STAGE_BLIT);
713
714 fd_log_stream(batch, stream, util_dump_blit_info(stream, info));
715
716 emit_setup(batch);
717
718 if ((info->src.resource->target == PIPE_BUFFER) &&
719 (info->dst.resource->target == PIPE_BUFFER)) {
720 assert(fd_resource(info->src.resource)->layout.tile_mode == TILE6_LINEAR);
721 assert(fd_resource(info->dst.resource)->layout.tile_mode == TILE6_LINEAR);
722 fd_log(batch, "START BLIT (BUFFER)");
723 emit_blit_buffer(ctx, batch->draw, info);
724 fd_log(batch, "END BLIT (BUFFER)");
725 } else {
726 /* I don't *think* we need to handle blits between buffer <-> !buffer */
727 debug_assert(info->src.resource->target != PIPE_BUFFER);
728 debug_assert(info->dst.resource->target != PIPE_BUFFER);
729 fd_log(batch, "START BLIT (TEXTURE)");
730 emit_blit_texture(ctx, batch->draw, info);
731 fd_log(batch, "END BLIT (TEXTURE)");
732 }
733
734 fd6_event_write(batch, batch->draw, PC_CCU_FLUSH_COLOR_TS, true);
735 fd6_event_write(batch, batch->draw, PC_CCU_FLUSH_DEPTH_TS, true);
736 fd6_event_write(batch, batch->draw, CACHE_FLUSH_TS, true);
737 fd6_cache_inv(batch, batch->draw);
738
739 fd_resource(info->dst.resource)->valid = true;
740 batch->needs_flush = true;
741
742 fd_batch_flush(batch);
743 fd_batch_reference(&batch, NULL);
744
745 return true;
746 }
747
748 /**
749 * Re-written z/s blits can still fail for various reasons (for example MSAA).
750 * But we want to do the fallback blit with the re-written pipe_blit_info,
751 * in particular as u_blitter cannot blit stencil. So handle the fallback
752 * ourself and never "fail".
753 */
754 static bool
755 do_rewritten_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
756 {
757 bool success = handle_rgba_blit(ctx, info);
758 if (!success)
759 success = fd_blitter_blit(ctx, info);
760 debug_assert(success); /* fallback should never fail! */
761 return success;
762 }
763
764 /**
765 * Handle depth/stencil blits either via u_blitter and/or re-writing the
766 * blit into an equivilant format that we can handle
767 */
768 static bool
769 handle_zs_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
770 {
771 struct pipe_blit_info blit = *info;
772
773 if (DEBUG_BLIT) {
774 fprintf(stderr, "---- handle_zs_blit: ");
775 util_dump_blit_info(stderr, info);
776 fprintf(stderr, "\ndst resource: ");
777 util_dump_resource(stderr, info->dst.resource);
778 fprintf(stderr, "\nsrc resource: ");
779 util_dump_resource(stderr, info->src.resource);
780 fprintf(stderr, "\n");
781 }
782
783 switch (info->dst.format) {
784 case PIPE_FORMAT_S8_UINT:
785 debug_assert(info->mask == PIPE_MASK_S);
786 blit.mask = PIPE_MASK_R;
787 blit.src.format = PIPE_FORMAT_R8_UINT;
788 blit.dst.format = PIPE_FORMAT_R8_UINT;
789 return do_rewritten_blit(ctx, &blit);
790
791 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
792 if (info->mask & PIPE_MASK_Z) {
793 blit.mask = PIPE_MASK_R;
794 blit.src.format = PIPE_FORMAT_R32_FLOAT;
795 blit.dst.format = PIPE_FORMAT_R32_FLOAT;
796 do_rewritten_blit(ctx, &blit);
797 }
798
799 if (info->mask & PIPE_MASK_S) {
800 blit.mask = PIPE_MASK_R;
801 blit.src.format = PIPE_FORMAT_R8_UINT;
802 blit.dst.format = PIPE_FORMAT_R8_UINT;
803 blit.src.resource = &fd_resource(info->src.resource)->stencil->base;
804 blit.dst.resource = &fd_resource(info->dst.resource)->stencil->base;
805 do_rewritten_blit(ctx, &blit);
806 }
807
808 return true;
809
810 case PIPE_FORMAT_Z16_UNORM:
811 blit.mask = PIPE_MASK_R;
812 blit.src.format = PIPE_FORMAT_R16_UNORM;
813 blit.dst.format = PIPE_FORMAT_R16_UNORM;
814 return do_rewritten_blit(ctx, &blit);
815
816 case PIPE_FORMAT_Z32_UNORM:
817 case PIPE_FORMAT_Z32_FLOAT:
818 debug_assert(info->mask == PIPE_MASK_Z);
819 blit.mask = PIPE_MASK_R;
820 blit.src.format = PIPE_FORMAT_R32_UINT;
821 blit.dst.format = PIPE_FORMAT_R32_UINT;
822 return do_rewritten_blit(ctx, &blit);
823
824 case PIPE_FORMAT_Z24X8_UNORM:
825 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
826 blit.mask = 0;
827 if (info->mask & PIPE_MASK_Z)
828 blit.mask |= PIPE_MASK_R | PIPE_MASK_G | PIPE_MASK_B;
829 if (info->mask & PIPE_MASK_S)
830 blit.mask |= PIPE_MASK_A;
831 blit.src.format = PIPE_FORMAT_Z24_UNORM_S8_UINT_AS_R8G8B8A8;
832 blit.dst.format = PIPE_FORMAT_Z24_UNORM_S8_UINT_AS_R8G8B8A8;
833 return fd_blitter_blit(ctx, &blit);
834
835 default:
836 return false;
837 }
838 }
839
840 static bool
841 handle_compressed_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
842 {
843 struct pipe_blit_info blit = *info;
844
845 if (DEBUG_BLIT) {
846 fprintf(stderr, "---- handle_compressed_blit: ");
847 util_dump_blit_info(stderr, info);
848 fprintf(stderr, "\ndst resource: ");
849 util_dump_resource(stderr, info->dst.resource);
850 fprintf(stderr, "\nsrc resource: ");
851 util_dump_resource(stderr, info->src.resource);
852 fprintf(stderr, "\n");
853 }
854
855 if (info->src.format != info->dst.format)
856 return fd_blitter_blit(ctx, info);
857
858 if (util_format_get_blocksize(info->src.format) == 8) {
859 blit.src.format = blit.dst.format = PIPE_FORMAT_R16G16B16A16_UINT;
860 } else {
861 debug_assert(util_format_get_blocksize(info->src.format) == 16);
862 blit.src.format = blit.dst.format = PIPE_FORMAT_R32G32B32A32_UINT;
863 }
864
865 int bw = util_format_get_blockwidth(info->src.format);
866 int bh = util_format_get_blockheight(info->src.format);
867
868 /* NOTE: x/y *must* be aligned to block boundary (ie. in
869 * glCompressedTexSubImage2D()) but width/height may not
870 * be:
871 */
872
873 debug_assert((blit.src.box.x % bw) == 0);
874 debug_assert((blit.src.box.y % bh) == 0);
875
876 blit.src.box.x /= bw;
877 blit.src.box.y /= bh;
878 blit.src.box.width = DIV_ROUND_UP(blit.src.box.width, bw);
879 blit.src.box.height = DIV_ROUND_UP(blit.src.box.height, bh);
880
881 debug_assert((blit.dst.box.x % bw) == 0);
882 debug_assert((blit.dst.box.y % bh) == 0);
883
884 blit.dst.box.x /= bw;
885 blit.dst.box.y /= bh;
886 blit.dst.box.width = DIV_ROUND_UP(blit.dst.box.width, bw);
887 blit.dst.box.height = DIV_ROUND_UP(blit.dst.box.height, bh);
888
889 return do_rewritten_blit(ctx, &blit);
890 }
891
892 static bool
893 fd6_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
894 {
895 if (info->mask & PIPE_MASK_ZS)
896 return handle_zs_blit(ctx, info);
897 if (util_format_is_compressed(info->src.format) ||
898 util_format_is_compressed(info->dst.format))
899 return handle_compressed_blit(ctx, info);
900
901 return handle_rgba_blit(ctx, info);
902 }
903
904 void
905 fd6_blitter_init(struct pipe_context *pctx)
906 {
907 if (fd_mesa_debug & FD_DBG_NOBLIT)
908 return;
909
910 fd_context(pctx)->blit = fd6_blit;
911 }
912
913 unsigned
914 fd6_tile_mode(const struct pipe_resource *tmpl)
915 {
916 /* if the mipmap level 0 is still too small to be tiled, then don't
917 * bother pretending:
918 */
919 if (fd_resource_level_linear(tmpl, 0))
920 return TILE6_LINEAR;
921
922 /* basically just has to be a format we can blit, so uploads/downloads
923 * via linear staging buffer works:
924 */
925 if (ok_format(tmpl->format))
926 return TILE6_3;
927
928 return TILE6_LINEAR;
929 }