1 /**************************************************************************
3 * Copyright 2008 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include "draw/draw_context.h"
30 #include "os/os_misc.h"
31 #include "util/u_format.h"
32 #include "util/u_format_s3tc.h"
33 #include "util/u_inlines.h"
34 #include "util/u_memory.h"
35 #include "util/u_string.h"
38 #include "i915_debug.h"
39 #include "i915_context.h"
40 #include "i915_screen.h"
41 #include "i915_resource.h"
42 #include "i915_winsys.h"
43 #include "i915_public.h"
52 i915_get_vendor(struct pipe_screen
*screen
)
54 return "Mesa Project";
58 i915_get_device_vendor(struct pipe_screen
*screen
)
64 i915_get_name(struct pipe_screen
*screen
)
66 static char buffer
[128];
69 switch (i915_screen(screen
)->iws
->pci_id
) {
73 case PCI_CHIP_I915_GM
:
79 case PCI_CHIP_I945_GM
:
82 case PCI_CHIP_I945_GME
:
94 case PCI_CHIP_PINEVIEW_G
:
95 chipset
= "Pineview G";
97 case PCI_CHIP_PINEVIEW_M
:
98 chipset
= "Pineview M";
105 util_snprintf(buffer
, sizeof(buffer
), "i915 (chipset: %s)", chipset
);
110 i915_get_shader_param(struct pipe_screen
*screen
,
111 enum pipe_shader_type shader
,
112 enum pipe_shader_cap cap
)
115 case PIPE_SHADER_VERTEX
:
117 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
118 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
119 if (debug_get_bool_option("DRAW_USE_LLVM", TRUE
))
120 return PIPE_MAX_SAMPLERS
;
124 return draw_get_shader_param(shader
, cap
);
126 case PIPE_SHADER_FRAGMENT
:
127 /* XXX: some of these are just shader model 2.0 values, fix this! */
129 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
130 return I915_MAX_ALU_INSN
+ I915_MAX_TEX_INSN
;
131 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
132 return I915_MAX_ALU_INSN
;
133 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
134 return I915_MAX_TEX_INSN
;
135 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
137 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
139 case PIPE_SHADER_CAP_MAX_INPUTS
:
141 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
143 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
144 return 32 * sizeof(float[4]);
145 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
147 case PIPE_SHADER_CAP_MAX_TEMPS
:
148 return 12; /* XXX: 12 -> 32 ? */
149 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
150 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
152 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
153 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
154 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
155 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
157 case PIPE_SHADER_CAP_SUBROUTINES
:
159 case PIPE_SHADER_CAP_INTEGERS
:
161 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
162 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
163 return I915_TEX_UNITS
;
164 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
165 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
166 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
167 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
169 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
172 debug_printf("%s: Unknown cap %u.\n", __FUNCTION__
, cap
);
183 i915_get_param(struct pipe_screen
*screen
, enum pipe_cap cap
)
185 struct i915_screen
*is
= i915_screen(screen
);
188 /* Supported features (boolean caps). */
189 case PIPE_CAP_ANISOTROPIC_FILTER
:
190 case PIPE_CAP_NPOT_TEXTURES
:
191 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
192 case PIPE_CAP_POINT_SPRITE
:
193 case PIPE_CAP_PRIMITIVE_RESTART
: /* draw module */
194 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
195 case PIPE_CAP_TWO_SIDED_STENCIL
:
196 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
197 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
198 case PIPE_CAP_TGSI_INSTANCEID
:
199 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
200 case PIPE_CAP_USER_VERTEX_BUFFERS
:
201 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
202 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
205 /* Unsupported features (boolean caps). */
206 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
207 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
208 case PIPE_CAP_INDEP_BLEND_ENABLE
:
209 case PIPE_CAP_INDEP_BLEND_FUNC
:
210 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
211 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
212 case PIPE_CAP_TEXTURE_SWIZZLE
:
213 case PIPE_CAP_QUERY_TIME_ELAPSED
:
215 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
216 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
217 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
218 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
219 case PIPE_CAP_CONDITIONAL_RENDER
:
220 case PIPE_CAP_TEXTURE_BARRIER
:
221 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
222 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
223 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
224 case PIPE_CAP_START_INSTANCE
:
225 case PIPE_CAP_QUERY_TIMESTAMP
:
226 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
227 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
228 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
229 case PIPE_CAP_CUBE_MAP_ARRAY
:
230 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
231 case PIPE_CAP_TGSI_TEXCOORD
:
232 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
233 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
234 case PIPE_CAP_TEXTURE_GATHER_SM5
:
235 case PIPE_CAP_FAKE_SW_MSAA
:
236 case PIPE_CAP_TEXTURE_QUERY_LOD
:
237 case PIPE_CAP_SAMPLE_SHADING
:
238 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
239 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
240 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
241 case PIPE_CAP_CLIP_HALFZ
:
242 case PIPE_CAP_VERTEXID_NOBASE
:
243 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
244 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
245 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
246 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
247 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
248 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
249 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
250 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
251 case PIPE_CAP_TGSI_TXQS
:
252 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
253 case PIPE_CAP_SHAREABLE_SHADERS
:
254 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
255 case PIPE_CAP_CLEAR_TEXTURE
:
256 case PIPE_CAP_DRAW_PARAMETERS
:
257 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
258 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
259 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
260 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
261 case PIPE_CAP_INVALIDATE_BUFFER
:
262 case PIPE_CAP_GENERATE_MIPMAP
:
263 case PIPE_CAP_STRING_MARKER
:
264 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
:
265 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
266 case PIPE_CAP_QUERY_MEMORY_INFO
:
267 case PIPE_CAP_PCI_GROUP
:
268 case PIPE_CAP_PCI_BUS
:
269 case PIPE_CAP_PCI_DEVICE
:
270 case PIPE_CAP_PCI_FUNCTION
:
271 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
272 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
273 case PIPE_CAP_CULL_DISTANCE
:
274 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES
:
275 case PIPE_CAP_TGSI_VOTE
:
276 case PIPE_CAP_MAX_WINDOW_RECTANGLES
:
277 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED
:
278 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
281 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
282 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
283 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
284 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
285 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
286 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
287 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
288 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
289 case PIPE_CAP_DRAW_INDIRECT
:
290 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
291 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
292 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
293 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
294 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS
:
295 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS
:
296 case PIPE_CAP_NATIVE_FENCE_FD
:
297 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
298 case PIPE_CAP_TGSI_FS_FBFETCH
:
299 case PIPE_CAP_TGSI_MUL_ZERO_WINS
:
300 case PIPE_CAP_DOUBLES
:
302 case PIPE_CAP_INT64_DIVMOD
:
303 case PIPE_CAP_TGSI_TEX_TXF_LZ
:
304 case PIPE_CAP_TGSI_CLOCK
:
307 case PIPE_CAP_MAX_VIEWPORTS
:
310 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
313 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
316 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
319 /* Features we can lie about (boolean caps). */
320 case PIPE_CAP_OCCLUSION_QUERY
:
321 return is
->debug
.lie
? 1 : 0;
324 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
325 return I915_MAX_TEXTURE_2D_LEVELS
;
326 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
327 return I915_MAX_TEXTURE_3D_LEVELS
;
328 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
329 return I915_MAX_TEXTURE_2D_LEVELS
;
330 case PIPE_CAP_MIN_TEXEL_OFFSET
:
331 case PIPE_CAP_MAX_TEXEL_OFFSET
:
332 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
333 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
334 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
335 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
336 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
339 /* Render targets. */
340 case PIPE_CAP_MAX_RENDER_TARGETS
:
343 /* Geometry shader output, unsupported. */
344 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
345 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
346 case PIPE_CAP_MAX_VERTEX_STREAMS
:
349 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
352 /* Fragment coordinate conventions. */
353 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
354 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
356 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
357 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
359 case PIPE_CAP_ENDIANNESS
:
360 return PIPE_ENDIAN_LITTLE
;
362 case PIPE_CAP_VENDOR_ID
:
364 case PIPE_CAP_DEVICE_ID
:
365 return is
->iws
->pci_id
;
366 case PIPE_CAP_ACCELERATED
:
368 case PIPE_CAP_VIDEO_MEMORY
: {
369 /* Once a batch uses more than 75% of the maximum mappable size, we
370 * assume that there's some fragmentation, and we start doing extra
371 * flushing, etc. That's the big cliff apps will care about.
373 const int gpu_mappable_megabytes
= is
->iws
->aperture_size(is
->iws
) * 3 / 4;
374 uint64_t system_memory
;
376 if (!os_get_total_physical_memory(&system_memory
))
379 return MIN2(gpu_mappable_megabytes
, (int)(system_memory
>> 20));
385 debug_printf("%s: Unknown cap %u.\n", __FUNCTION__
, cap
);
391 i915_get_paramf(struct pipe_screen
*screen
, enum pipe_capf cap
)
394 case PIPE_CAPF_MAX_LINE_WIDTH
:
396 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
399 case PIPE_CAPF_MAX_POINT_WIDTH
:
401 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
404 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
407 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
411 debug_printf("%s: Unknown cap %u.\n", __FUNCTION__
, cap
);
417 i915_is_format_supported(struct pipe_screen
*screen
,
418 enum pipe_format format
,
419 enum pipe_texture_target target
,
420 unsigned sample_count
,
423 static const enum pipe_format tex_supported
[] = {
424 PIPE_FORMAT_B8G8R8A8_UNORM
,
425 PIPE_FORMAT_B8G8R8A8_SRGB
,
426 PIPE_FORMAT_B8G8R8X8_UNORM
,
427 PIPE_FORMAT_R8G8B8A8_UNORM
,
428 PIPE_FORMAT_R8G8B8X8_UNORM
,
429 PIPE_FORMAT_B4G4R4A4_UNORM
,
430 PIPE_FORMAT_B5G6R5_UNORM
,
431 PIPE_FORMAT_B5G5R5A1_UNORM
,
432 PIPE_FORMAT_B10G10R10A2_UNORM
,
433 PIPE_FORMAT_L8_UNORM
,
434 PIPE_FORMAT_A8_UNORM
,
435 PIPE_FORMAT_I8_UNORM
,
436 PIPE_FORMAT_L8A8_UNORM
,
440 PIPE_FORMAT_Z16_UNORM, */
441 PIPE_FORMAT_DXT1_RGB
,
442 PIPE_FORMAT_DXT1_RGBA
,
443 PIPE_FORMAT_DXT3_RGBA
,
444 PIPE_FORMAT_DXT5_RGBA
,
445 PIPE_FORMAT_Z24X8_UNORM
,
446 PIPE_FORMAT_Z24_UNORM_S8_UINT
,
447 PIPE_FORMAT_NONE
/* list terminator */
449 static const enum pipe_format render_supported
[] = {
450 PIPE_FORMAT_B8G8R8A8_UNORM
,
451 PIPE_FORMAT_B8G8R8X8_UNORM
,
452 PIPE_FORMAT_R8G8B8A8_UNORM
,
453 PIPE_FORMAT_R8G8B8X8_UNORM
,
454 PIPE_FORMAT_B5G6R5_UNORM
,
455 PIPE_FORMAT_B5G5R5A1_UNORM
,
456 PIPE_FORMAT_B4G4R4A4_UNORM
,
457 PIPE_FORMAT_B10G10R10A2_UNORM
,
458 PIPE_FORMAT_L8_UNORM
,
459 PIPE_FORMAT_A8_UNORM
,
460 PIPE_FORMAT_I8_UNORM
,
461 PIPE_FORMAT_NONE
/* list terminator */
463 static const enum pipe_format depth_supported
[] = {
465 PIPE_FORMAT_Z16_UNORM, */
466 PIPE_FORMAT_Z24X8_UNORM
,
467 PIPE_FORMAT_Z24_UNORM_S8_UINT
,
468 PIPE_FORMAT_NONE
/* list terminator */
470 const enum pipe_format
*list
;
473 if (!util_format_is_supported(format
, tex_usage
))
476 if (sample_count
> 1)
479 if(tex_usage
& PIPE_BIND_DEPTH_STENCIL
)
480 list
= depth_supported
;
481 else if (tex_usage
& PIPE_BIND_RENDER_TARGET
)
482 list
= render_supported
;
483 else if (tex_usage
& PIPE_BIND_SAMPLER_VIEW
)
484 list
= tex_supported
;
486 return TRUE
; /* PIPE_BIND_{VERTEX,INDEX}_BUFFER */
488 for (i
= 0; list
[i
] != PIPE_FORMAT_NONE
; i
++) {
489 if (list
[i
] == format
)
503 i915_fence_reference(struct pipe_screen
*screen
,
504 struct pipe_fence_handle
**ptr
,
505 struct pipe_fence_handle
*fence
)
507 struct i915_screen
*is
= i915_screen(screen
);
509 is
->iws
->fence_reference(is
->iws
, ptr
, fence
);
513 i915_fence_finish(struct pipe_screen
*screen
,
514 struct pipe_context
*ctx
,
515 struct pipe_fence_handle
*fence
,
518 struct i915_screen
*is
= i915_screen(screen
);
521 return is
->iws
->fence_signalled(is
->iws
, fence
) == 1;
523 return is
->iws
->fence_finish(is
->iws
, fence
) == 1;
533 i915_flush_frontbuffer(struct pipe_screen
*screen
,
534 struct pipe_resource
*resource
,
535 unsigned level
, unsigned layer
,
536 void *winsys_drawable_handle
,
537 struct pipe_box
*sub_box
)
539 /* XXX: Dummy right now. */
544 (void)winsys_drawable_handle
;
549 i915_destroy_screen(struct pipe_screen
*screen
)
551 struct i915_screen
*is
= i915_screen(screen
);
554 is
->iws
->destroy(is
->iws
);
560 * Create a new i915_screen object
563 i915_screen_create(struct i915_winsys
*iws
)
565 struct i915_screen
*is
= CALLOC_STRUCT(i915_screen
);
570 switch (iws
->pci_id
) {
571 case PCI_CHIP_I915_G
:
572 case PCI_CHIP_I915_GM
:
576 case PCI_CHIP_I945_G
:
577 case PCI_CHIP_I945_GM
:
578 case PCI_CHIP_I945_GME
:
582 case PCI_CHIP_PINEVIEW_G
:
583 case PCI_CHIP_PINEVIEW_M
:
588 debug_printf("%s: unknown pci id 0x%x, cannot create screen\n",
589 __FUNCTION__
, iws
->pci_id
);
596 is
->base
.destroy
= i915_destroy_screen
;
597 is
->base
.flush_frontbuffer
= i915_flush_frontbuffer
;
599 is
->base
.get_name
= i915_get_name
;
600 is
->base
.get_vendor
= i915_get_vendor
;
601 is
->base
.get_device_vendor
= i915_get_device_vendor
;
602 is
->base
.get_param
= i915_get_param
;
603 is
->base
.get_shader_param
= i915_get_shader_param
;
604 is
->base
.get_paramf
= i915_get_paramf
;
605 is
->base
.is_format_supported
= i915_is_format_supported
;
607 is
->base
.context_create
= i915_create_context
;
609 is
->base
.fence_reference
= i915_fence_reference
;
610 is
->base
.fence_finish
= i915_fence_finish
;
612 i915_init_screen_resource_functions(is
);
616 util_format_s3tc_init();