1 /**************************************************************************
3 * Copyright 2008 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include "draw/draw_context.h"
30 #include "os/os_misc.h"
31 #include "util/u_format.h"
32 #include "util/u_format_s3tc.h"
33 #include "util/u_inlines.h"
34 #include "util/u_memory.h"
35 #include "util/u_string.h"
38 #include "i915_debug.h"
39 #include "i915_context.h"
40 #include "i915_screen.h"
41 #include "i915_resource.h"
42 #include "i915_winsys.h"
43 #include "i915_public.h"
52 i915_get_vendor(struct pipe_screen
*screen
)
54 return "Mesa Project";
58 i915_get_name(struct pipe_screen
*screen
)
60 static char buffer
[128];
63 switch (i915_screen(screen
)->iws
->pci_id
) {
67 case PCI_CHIP_I915_GM
:
73 case PCI_CHIP_I945_GM
:
76 case PCI_CHIP_I945_GME
:
88 case PCI_CHIP_PINEVIEW_G
:
89 chipset
= "Pineview G";
91 case PCI_CHIP_PINEVIEW_M
:
92 chipset
= "Pineview M";
99 util_snprintf(buffer
, sizeof(buffer
), "i915 (chipset: %s)", chipset
);
104 i915_get_shader_param(struct pipe_screen
*screen
, unsigned shader
, enum pipe_shader_cap cap
)
107 case PIPE_SHADER_VERTEX
:
109 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
110 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
111 if (debug_get_bool_option("DRAW_USE_LLVM", TRUE
))
112 return PIPE_MAX_SAMPLERS
;
116 return draw_get_shader_param(shader
, cap
);
118 case PIPE_SHADER_FRAGMENT
:
119 /* XXX: some of these are just shader model 2.0 values, fix this! */
121 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
122 return I915_MAX_ALU_INSN
+ I915_MAX_TEX_INSN
;
123 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
124 return I915_MAX_ALU_INSN
;
125 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
126 return I915_MAX_TEX_INSN
;
127 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
129 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
131 case PIPE_SHADER_CAP_MAX_INPUTS
:
133 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
135 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
136 return 32 * sizeof(float[4]);
137 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
139 case PIPE_SHADER_CAP_MAX_TEMPS
:
140 return 12; /* XXX: 12 -> 32 ? */
141 case PIPE_SHADER_CAP_MAX_PREDS
:
143 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
144 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
146 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
147 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
148 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
149 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
151 case PIPE_SHADER_CAP_SUBROUTINES
:
153 case PIPE_SHADER_CAP_INTEGERS
:
155 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
156 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
157 return I915_TEX_UNITS
;
159 debug_printf("%s: Unknown cap %u.\n", __FUNCTION__
, cap
);
170 i915_get_param(struct pipe_screen
*screen
, enum pipe_cap cap
)
172 struct i915_screen
*is
= i915_screen(screen
);
175 /* Supported features (boolean caps). */
176 case PIPE_CAP_ANISOTROPIC_FILTER
:
177 case PIPE_CAP_NPOT_TEXTURES
:
178 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
179 case PIPE_CAP_POINT_SPRITE
:
180 case PIPE_CAP_PRIMITIVE_RESTART
: /* draw module */
181 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
182 case PIPE_CAP_TWO_SIDED_STENCIL
:
183 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
184 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
185 case PIPE_CAP_TGSI_INSTANCEID
:
186 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
187 case PIPE_CAP_USER_VERTEX_BUFFERS
:
188 case PIPE_CAP_USER_INDEX_BUFFERS
:
189 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
192 /* Unsupported features (boolean caps). */
193 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
194 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
195 case PIPE_CAP_INDEP_BLEND_ENABLE
:
196 case PIPE_CAP_INDEP_BLEND_FUNC
:
197 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
198 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
199 case PIPE_CAP_TEXTURE_SWIZZLE
:
200 case PIPE_CAP_QUERY_TIME_ELAPSED
:
202 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
203 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
204 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
205 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
206 case PIPE_CAP_CONDITIONAL_RENDER
:
207 case PIPE_CAP_TEXTURE_BARRIER
:
208 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
209 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
210 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
211 case PIPE_CAP_START_INSTANCE
:
212 case PIPE_CAP_QUERY_TIMESTAMP
:
213 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
214 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
215 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
216 case PIPE_CAP_CUBE_MAP_ARRAY
:
217 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
218 case PIPE_CAP_TGSI_TEXCOORD
:
219 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
220 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
221 case PIPE_CAP_TEXTURE_GATHER_SM5
:
222 case PIPE_CAP_FAKE_SW_MSAA
:
223 case PIPE_CAP_TEXTURE_QUERY_LOD
:
224 case PIPE_CAP_SAMPLE_SHADING
:
225 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
226 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
227 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
228 case PIPE_CAP_CLIP_HALFZ
:
231 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
232 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
233 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
234 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
235 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
236 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
237 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
238 case PIPE_CAP_DRAW_INDIRECT
:
239 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
240 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
243 case PIPE_CAP_MAX_VIEWPORTS
:
246 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
249 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
252 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
255 /* Features we can lie about (boolean caps). */
256 case PIPE_CAP_OCCLUSION_QUERY
:
257 return is
->debug
.lie
? 1 : 0;
260 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
261 return I915_MAX_TEXTURE_2D_LEVELS
;
262 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
263 return I915_MAX_TEXTURE_3D_LEVELS
;
264 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
265 return I915_MAX_TEXTURE_2D_LEVELS
;
266 case PIPE_CAP_MIN_TEXEL_OFFSET
:
267 case PIPE_CAP_MAX_TEXEL_OFFSET
:
268 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
269 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
270 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
271 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
272 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
275 /* Render targets. */
276 case PIPE_CAP_MAX_RENDER_TARGETS
:
279 /* Geometry shader output, unsupported. */
280 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
281 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
282 case PIPE_CAP_MAX_VERTEX_STREAMS
:
285 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
288 /* Fragment coordinate conventions. */
289 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
290 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
292 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
293 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
295 case PIPE_CAP_ENDIANNESS
:
296 return PIPE_ENDIAN_LITTLE
;
298 case PIPE_CAP_VENDOR_ID
:
300 case PIPE_CAP_DEVICE_ID
:
301 return is
->iws
->pci_id
;
302 case PIPE_CAP_ACCELERATED
:
304 case PIPE_CAP_VIDEO_MEMORY
: {
305 /* Once a batch uses more than 75% of the maximum mappable size, we
306 * assume that there's some fragmentation, and we start doing extra
307 * flushing, etc. That's the big cliff apps will care about.
309 const int gpu_mappable_megabytes
= is
->iws
->aperture_size(is
->iws
) * 3 / 4;
310 uint64_t system_memory
;
312 if (!os_get_total_physical_memory(&system_memory
))
315 return MIN2(gpu_mappable_megabytes
, (int)(system_memory
>> 20));
321 debug_printf("%s: Unknown cap %u.\n", __FUNCTION__
, cap
);
327 i915_get_paramf(struct pipe_screen
*screen
, enum pipe_capf cap
)
330 case PIPE_CAPF_MAX_LINE_WIDTH
:
332 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
335 case PIPE_CAPF_MAX_POINT_WIDTH
:
337 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
340 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
343 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
347 debug_printf("%s: Unknown cap %u.\n", __FUNCTION__
, cap
);
353 i915_is_format_supported(struct pipe_screen
*screen
,
354 enum pipe_format format
,
355 enum pipe_texture_target target
,
356 unsigned sample_count
,
359 static const enum pipe_format tex_supported
[] = {
360 PIPE_FORMAT_B8G8R8A8_UNORM
,
361 PIPE_FORMAT_B8G8R8A8_SRGB
,
362 PIPE_FORMAT_B8G8R8X8_UNORM
,
363 PIPE_FORMAT_R8G8B8A8_UNORM
,
364 PIPE_FORMAT_R8G8B8X8_UNORM
,
365 PIPE_FORMAT_B4G4R4A4_UNORM
,
366 PIPE_FORMAT_B5G6R5_UNORM
,
367 PIPE_FORMAT_B5G5R5A1_UNORM
,
368 PIPE_FORMAT_B10G10R10A2_UNORM
,
369 PIPE_FORMAT_L8_UNORM
,
370 PIPE_FORMAT_A8_UNORM
,
371 PIPE_FORMAT_I8_UNORM
,
372 PIPE_FORMAT_L8A8_UNORM
,
376 PIPE_FORMAT_Z16_UNORM, */
377 PIPE_FORMAT_DXT1_RGB
,
378 PIPE_FORMAT_DXT1_RGBA
,
379 PIPE_FORMAT_DXT3_RGBA
,
380 PIPE_FORMAT_DXT5_RGBA
,
381 PIPE_FORMAT_Z24X8_UNORM
,
382 PIPE_FORMAT_Z24_UNORM_S8_UINT
,
383 PIPE_FORMAT_NONE
/* list terminator */
385 static const enum pipe_format render_supported
[] = {
386 PIPE_FORMAT_B8G8R8A8_UNORM
,
387 PIPE_FORMAT_B8G8R8X8_UNORM
,
388 PIPE_FORMAT_R8G8B8A8_UNORM
,
389 PIPE_FORMAT_R8G8B8X8_UNORM
,
390 PIPE_FORMAT_B5G6R5_UNORM
,
391 PIPE_FORMAT_B5G5R5A1_UNORM
,
392 PIPE_FORMAT_B4G4R4A4_UNORM
,
393 PIPE_FORMAT_B10G10R10A2_UNORM
,
394 PIPE_FORMAT_L8_UNORM
,
395 PIPE_FORMAT_A8_UNORM
,
396 PIPE_FORMAT_I8_UNORM
,
397 PIPE_FORMAT_NONE
/* list terminator */
399 static const enum pipe_format depth_supported
[] = {
401 PIPE_FORMAT_Z16_UNORM, */
402 PIPE_FORMAT_Z24X8_UNORM
,
403 PIPE_FORMAT_Z24_UNORM_S8_UINT
,
404 PIPE_FORMAT_NONE
/* list terminator */
406 const enum pipe_format
*list
;
409 if (!util_format_is_supported(format
, tex_usage
))
412 if (sample_count
> 1)
415 if(tex_usage
& PIPE_BIND_DEPTH_STENCIL
)
416 list
= depth_supported
;
417 else if (tex_usage
& PIPE_BIND_RENDER_TARGET
)
418 list
= render_supported
;
419 else if (tex_usage
& PIPE_BIND_SAMPLER_VIEW
)
420 list
= tex_supported
;
422 return TRUE
; /* PIPE_BIND_{VERTEX,INDEX}_BUFFER */
424 for (i
= 0; list
[i
] != PIPE_FORMAT_NONE
; i
++) {
425 if (list
[i
] == format
)
439 i915_fence_reference(struct pipe_screen
*screen
,
440 struct pipe_fence_handle
**ptr
,
441 struct pipe_fence_handle
*fence
)
443 struct i915_screen
*is
= i915_screen(screen
);
445 is
->iws
->fence_reference(is
->iws
, ptr
, fence
);
449 i915_fence_signalled(struct pipe_screen
*screen
,
450 struct pipe_fence_handle
*fence
)
452 struct i915_screen
*is
= i915_screen(screen
);
454 return is
->iws
->fence_signalled(is
->iws
, fence
) == 1;
458 i915_fence_finish(struct pipe_screen
*screen
,
459 struct pipe_fence_handle
*fence
,
462 struct i915_screen
*is
= i915_screen(screen
);
464 return is
->iws
->fence_finish(is
->iws
, fence
) == 1;
474 i915_flush_frontbuffer(struct pipe_screen
*screen
,
475 struct pipe_resource
*resource
,
476 unsigned level
, unsigned layer
,
477 void *winsys_drawable_handle
,
478 struct pipe_box
*sub_box
)
480 /* XXX: Dummy right now. */
485 (void)winsys_drawable_handle
;
490 i915_destroy_screen(struct pipe_screen
*screen
)
492 struct i915_screen
*is
= i915_screen(screen
);
495 is
->iws
->destroy(is
->iws
);
501 * Create a new i915_screen object
504 i915_screen_create(struct i915_winsys
*iws
)
506 struct i915_screen
*is
= CALLOC_STRUCT(i915_screen
);
511 switch (iws
->pci_id
) {
512 case PCI_CHIP_I915_G
:
513 case PCI_CHIP_I915_GM
:
517 case PCI_CHIP_I945_G
:
518 case PCI_CHIP_I945_GM
:
519 case PCI_CHIP_I945_GME
:
523 case PCI_CHIP_PINEVIEW_G
:
524 case PCI_CHIP_PINEVIEW_M
:
529 debug_printf("%s: unknown pci id 0x%x, cannot create screen\n",
530 __FUNCTION__
, iws
->pci_id
);
537 is
->base
.destroy
= i915_destroy_screen
;
538 is
->base
.flush_frontbuffer
= i915_flush_frontbuffer
;
540 is
->base
.get_name
= i915_get_name
;
541 is
->base
.get_vendor
= i915_get_vendor
;
542 is
->base
.get_param
= i915_get_param
;
543 is
->base
.get_shader_param
= i915_get_shader_param
;
544 is
->base
.get_paramf
= i915_get_paramf
;
545 is
->base
.is_format_supported
= i915_is_format_supported
;
547 is
->base
.context_create
= i915_create_context
;
549 is
->base
.fence_reference
= i915_fence_reference
;
550 is
->base
.fence_signalled
= i915_fence_signalled
;
551 is
->base
.fence_finish
= i915_fence_finish
;
553 i915_init_screen_resource_functions(is
);
557 util_format_s3tc_init();