src/gallium/drivers/i915/i915_screen.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2008 VMware, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28
  29 #include "draw/draw_context.h"
  30 #include "os/os_misc.h"
  31 #include "util/u_format.h"
  32 #include "util/u_format_s3tc.h"
  33 #include "util/u_inlines.h"
  34 #include "util/u_memory.h"
  35 #include "util/u_string.h"
  36
  37 #include "i915_reg.h"
  38 #include "i915_debug.h"
  39 #include "i915_context.h"
  40 #include "i915_screen.h"
  41 #include "i915_resource.h"
  42 #include "i915_winsys.h"
  43 #include "i915_public.h"
  44
  45
  46 /*
  47  * Probe functions
  48  */
  49
  50
  51 static const char *
  52 i915_get_vendor(struct pipe_screen *screen)
  53 {
  54    return "Mesa Project";
  55 }
  56
  57 static const char *
  58 i915_get_device_vendor(struct pipe_screen *screen)
  59 {
  60    return "Intel";
  61 }
  62
  63 static const char *
  64 i915_get_name(struct pipe_screen *screen)
  65 {
  66    static char buffer[128];
  67    const char *chipset;
  68
  69    switch (i915_screen(screen)->iws->pci_id) {
  70    case PCI_CHIP_I915_G:
  71       chipset = "915G";
  72       break;
  73    case PCI_CHIP_I915_GM:
  74       chipset = "915GM";
  75       break;
  76    case PCI_CHIP_I945_G:
  77       chipset = "945G";
  78       break;
  79    case PCI_CHIP_I945_GM:
  80       chipset = "945GM";
  81       break;
  82    case PCI_CHIP_I945_GME:
  83       chipset = "945GME";
  84       break;
  85    case PCI_CHIP_G33_G:
  86       chipset = "G33";
  87       break;
  88    case PCI_CHIP_Q35_G:
  89       chipset = "Q35";
  90       break;
  91    case PCI_CHIP_Q33_G:
  92       chipset = "Q33";
  93       break;
  94    case PCI_CHIP_PINEVIEW_G:
  95       chipset = "Pineview G";
  96       break;
  97    case PCI_CHIP_PINEVIEW_M:
  98       chipset = "Pineview M";
  99       break;
 100    default:
 101       chipset = "unknown";
 102       break;
 103    }
 104
 105    util_snprintf(buffer, sizeof(buffer), "i915 (chipset: %s)", chipset);
 106    return buffer;
 107 }
 108
 109 static int
 110 i915_get_shader_param(struct pipe_screen *screen, unsigned shader, enum pipe_shader_cap cap)
 111 {
 112    switch(shader) {
 113    case PIPE_SHADER_VERTEX:
 114       switch (cap) {
 115       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 116       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 117          if (debug_get_bool_option("DRAW_USE_LLVM", TRUE))
 118             return PIPE_MAX_SAMPLERS;
 119          else
 120             return 0;
 121        default:
 122          return draw_get_shader_param(shader, cap);
 123       }
 124    case PIPE_SHADER_FRAGMENT:
 125       /* XXX: some of these are just shader model 2.0 values, fix this! */
 126       switch(cap) {
 127       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 128          return I915_MAX_ALU_INSN + I915_MAX_TEX_INSN;
 129       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 130          return I915_MAX_ALU_INSN;
 131       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 132          return I915_MAX_TEX_INSN;
 133       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 134          return 8;
 135       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 136          return 0;
 137       case PIPE_SHADER_CAP_MAX_INPUTS:
 138          return 10;
 139       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 140          return 1;
 141       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 142          return 32 * sizeof(float[4]);
 143       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 144          return 1;
 145       case PIPE_SHADER_CAP_MAX_TEMPS:
 146          return 12; /* XXX: 12 -> 32 ? */
 147       case PIPE_SHADER_CAP_MAX_PREDS:
 148          return 0;
 149       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 150       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 151          return 0;
 152       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 153       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 154       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 155       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 156          return 1;
 157       case PIPE_SHADER_CAP_SUBROUTINES:
 158          return 0;
 159       case PIPE_SHADER_CAP_INTEGERS:
 160          return 0;
 161       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 162       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 163          return I915_TEX_UNITS;
 164       case PIPE_SHADER_CAP_DOUBLES:
 165       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 166       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 167       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 168       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 169          return 0;
 170       default:
 171          debug_printf("%s: Unknown cap %u.\n", __FUNCTION__, cap);
 172          return 0;
 173       }
 174       break;
 175    default:
 176       return 0;
 177    }
 178
 179 }
 180
 181 static int
 182 i915_get_param(struct pipe_screen *screen, enum pipe_cap cap)
 183 {
 184    struct i915_screen *is = i915_screen(screen);
 185
 186    switch (cap) {
 187    /* Supported features (boolean caps). */
 188    case PIPE_CAP_ANISOTROPIC_FILTER:
 189    case PIPE_CAP_NPOT_TEXTURES:
 190    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 191    case PIPE_CAP_POINT_SPRITE:
 192    case PIPE_CAP_PRIMITIVE_RESTART: /* draw module */
 193    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 194    case PIPE_CAP_TWO_SIDED_STENCIL:
 195    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 196    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 197    case PIPE_CAP_TGSI_INSTANCEID:
 198    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 199    case PIPE_CAP_USER_VERTEX_BUFFERS:
 200    case PIPE_CAP_USER_INDEX_BUFFERS:
 201    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 202       return 1;
 203
 204    /* Unsupported features (boolean caps). */
 205    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 206    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 207    case PIPE_CAP_INDEP_BLEND_ENABLE:
 208    case PIPE_CAP_INDEP_BLEND_FUNC:
 209    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 210    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 211    case PIPE_CAP_TEXTURE_SWIZZLE:
 212    case PIPE_CAP_QUERY_TIME_ELAPSED:
 213    case PIPE_CAP_SM3:
 214    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 215    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 216    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 217    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 218    case PIPE_CAP_CONDITIONAL_RENDER:
 219    case PIPE_CAP_TEXTURE_BARRIER:
 220    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 221    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 222    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 223    case PIPE_CAP_START_INSTANCE:
 224    case PIPE_CAP_QUERY_TIMESTAMP:
 225    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 226    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 227    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 228    case PIPE_CAP_CUBE_MAP_ARRAY:
 229    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 230    case PIPE_CAP_TGSI_TEXCOORD:
 231    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 232    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 233    case PIPE_CAP_TEXTURE_GATHER_SM5:
 234    case PIPE_CAP_FAKE_SW_MSAA:
 235    case PIPE_CAP_TEXTURE_QUERY_LOD:
 236    case PIPE_CAP_SAMPLE_SHADING:
 237    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 238    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 239    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 240    case PIPE_CAP_CLIP_HALFZ:
 241    case PIPE_CAP_VERTEXID_NOBASE:
 242    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 243    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 244    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 245    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 246    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 247    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 248    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 249    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 250    case PIPE_CAP_TGSI_TXQS:
 251    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 252       return 0;
 253
 254    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 255    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 256    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 257    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 258    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 259    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 260    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 261    case PIPE_CAP_DRAW_INDIRECT:
 262    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 263    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 264       return 0;
 265
 266    case PIPE_CAP_MAX_VIEWPORTS:
 267       return 1;
 268
 269    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 270       return 64;
 271
 272    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 273       return 120;
 274
 275    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 276       return 16;
 277
 278    /* Features we can lie about (boolean caps). */
 279    case PIPE_CAP_OCCLUSION_QUERY:
 280       return is->debug.lie ? 1 : 0;
 281
 282    /* Texturing. */
 283    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 284       return I915_MAX_TEXTURE_2D_LEVELS;
 285    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 286       return I915_MAX_TEXTURE_3D_LEVELS;
 287    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 288       return I915_MAX_TEXTURE_2D_LEVELS;
 289    case PIPE_CAP_MIN_TEXEL_OFFSET:
 290    case PIPE_CAP_MAX_TEXEL_OFFSET:
 291    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 292    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 293    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 294    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 295    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 296       return 0;
 297
 298    /* Render targets. */
 299    case PIPE_CAP_MAX_RENDER_TARGETS:
 300       return 1;
 301
 302    /* Geometry shader output, unsupported. */
 303    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 304    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 305    case PIPE_CAP_MAX_VERTEX_STREAMS:
 306       return 0;
 307
 308    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 309       return 2048;
 310
 311    /* Fragment coordinate conventions. */
 312    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 313    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 314       return 1;
 315    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 316    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 317       return 0;
 318    case PIPE_CAP_ENDIANNESS:
 319       return PIPE_ENDIAN_LITTLE;
 320
 321    case PIPE_CAP_VENDOR_ID:
 322       return 0x8086;
 323    case PIPE_CAP_DEVICE_ID:
 324       return is->iws->pci_id;
 325    case PIPE_CAP_ACCELERATED:
 326       return 1;
 327    case PIPE_CAP_VIDEO_MEMORY: {
 328       /* Once a batch uses more than 75% of the maximum mappable size, we
 329        * assume that there's some fragmentation, and we start doing extra
 330        * flushing, etc.  That's the big cliff apps will care about.
 331        */
 332       const int gpu_mappable_megabytes = is->iws->aperture_size(is->iws) * 3 / 4;
 333       uint64_t system_memory;
 334
 335       if (!os_get_total_physical_memory(&system_memory))
 336          return 0;
 337
 338       return MIN2(gpu_mappable_megabytes, (int)(system_memory >> 20));
 339    }
 340    case PIPE_CAP_UMA:
 341       return 1;
 342
 343    default:
 344       debug_printf("%s: Unknown cap %u.\n", __FUNCTION__, cap);
 345       return 0;
 346    }
 347 }
 348
 349 static float
 350 i915_get_paramf(struct pipe_screen *screen, enum pipe_capf cap)
 351 {
 352    switch(cap) {
 353    case PIPE_CAPF_MAX_LINE_WIDTH:
 354       /* fall-through */
 355    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 356       return 7.5;
 357
 358    case PIPE_CAPF_MAX_POINT_WIDTH:
 359       /* fall-through */
 360    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 361       return 255.0;
 362
 363    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 364       return 4.0;
 365
 366    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 367       return 16.0;
 368
 369    default:
 370       debug_printf("%s: Unknown cap %u.\n", __FUNCTION__, cap);
 371       return 0;
 372    }
 373 }
 374
 375 boolean
 376 i915_is_format_supported(struct pipe_screen *screen,
 377                          enum pipe_format format,
 378                          enum pipe_texture_target target,
 379                          unsigned sample_count,
 380                          unsigned tex_usage)
 381 {
 382    static const enum pipe_format tex_supported[] = {
 383       PIPE_FORMAT_B8G8R8A8_UNORM,
 384       PIPE_FORMAT_B8G8R8A8_SRGB,
 385       PIPE_FORMAT_B8G8R8X8_UNORM,
 386       PIPE_FORMAT_R8G8B8A8_UNORM,
 387       PIPE_FORMAT_R8G8B8X8_UNORM,
 388       PIPE_FORMAT_B4G4R4A4_UNORM,
 389       PIPE_FORMAT_B5G6R5_UNORM,
 390       PIPE_FORMAT_B5G5R5A1_UNORM,
 391       PIPE_FORMAT_B10G10R10A2_UNORM,
 392       PIPE_FORMAT_L8_UNORM,
 393       PIPE_FORMAT_A8_UNORM,
 394       PIPE_FORMAT_I8_UNORM,
 395       PIPE_FORMAT_L8A8_UNORM,
 396       PIPE_FORMAT_UYVY,
 397       PIPE_FORMAT_YUYV,
 398       /* XXX why not?
 399       PIPE_FORMAT_Z16_UNORM, */
 400       PIPE_FORMAT_DXT1_RGB,
 401       PIPE_FORMAT_DXT1_RGBA,
 402       PIPE_FORMAT_DXT3_RGBA,
 403       PIPE_FORMAT_DXT5_RGBA,
 404       PIPE_FORMAT_Z24X8_UNORM,
 405       PIPE_FORMAT_Z24_UNORM_S8_UINT,
 406       PIPE_FORMAT_NONE  /* list terminator */
 407    };
 408    static const enum pipe_format render_supported[] = {
 409       PIPE_FORMAT_B8G8R8A8_UNORM,
 410       PIPE_FORMAT_B8G8R8X8_UNORM,
 411       PIPE_FORMAT_R8G8B8A8_UNORM,
 412       PIPE_FORMAT_R8G8B8X8_UNORM,
 413       PIPE_FORMAT_B5G6R5_UNORM,
 414       PIPE_FORMAT_B5G5R5A1_UNORM,
 415       PIPE_FORMAT_B4G4R4A4_UNORM,
 416       PIPE_FORMAT_B10G10R10A2_UNORM,
 417       PIPE_FORMAT_L8_UNORM,
 418       PIPE_FORMAT_A8_UNORM,
 419       PIPE_FORMAT_I8_UNORM,
 420       PIPE_FORMAT_NONE  /* list terminator */
 421    };
 422    static const enum pipe_format depth_supported[] = {
 423       /* XXX why not?
 424       PIPE_FORMAT_Z16_UNORM, */
 425       PIPE_FORMAT_Z24X8_UNORM,
 426       PIPE_FORMAT_Z24_UNORM_S8_UINT,
 427       PIPE_FORMAT_NONE  /* list terminator */
 428    };
 429    const enum pipe_format *list;
 430    uint i;
 431
 432    if (!util_format_is_supported(format, tex_usage))
 433       return FALSE;
 434
 435    if (sample_count > 1)
 436       return FALSE;
 437
 438    if(tex_usage & PIPE_BIND_DEPTH_STENCIL)
 439       list = depth_supported;
 440    else if (tex_usage & PIPE_BIND_RENDER_TARGET)
 441       list = render_supported;
 442    else if (tex_usage & PIPE_BIND_SAMPLER_VIEW)
 443       list = tex_supported;
 444    else
 445       return TRUE; /* PIPE_BIND_{VERTEX,INDEX}_BUFFER */
 446
 447    for (i = 0; list[i] != PIPE_FORMAT_NONE; i++) {
 448       if (list[i] == format)
 449          return TRUE;
 450    }
 451
 452    return FALSE;
 453 }
 454
 455
 456 /*
 457  * Fence functions
 458  */
 459
 460
 461 static void
 462 i915_fence_reference(struct pipe_screen *screen,
 463                      struct pipe_fence_handle **ptr,
 464                      struct pipe_fence_handle *fence)
 465 {
 466    struct i915_screen *is = i915_screen(screen);
 467
 468    is->iws->fence_reference(is->iws, ptr, fence);
 469 }
 470
 471 static boolean
 472 i915_fence_finish(struct pipe_screen *screen,
 473                   struct pipe_fence_handle *fence,
 474                   uint64_t timeout)
 475 {
 476    struct i915_screen *is = i915_screen(screen);
 477
 478    if (!timeout)
 479       return is->iws->fence_signalled(is->iws, fence) == 1;
 480
 481    return is->iws->fence_finish(is->iws, fence) == 1;
 482 }
 483
 484
 485 /*
 486  * Generic functions
 487  */
 488
 489
 490 static void
 491 i915_flush_frontbuffer(struct pipe_screen *screen,
 492                        struct pipe_resource *resource,
 493                        unsigned level, unsigned layer,
 494                        void *winsys_drawable_handle,
 495                        struct pipe_box *sub_box)
 496 {
 497    /* XXX: Dummy right now. */
 498    (void)screen;
 499    (void)resource;
 500    (void)level;
 501    (void)layer;
 502    (void)winsys_drawable_handle;
 503    (void)sub_box;
 504 }
 505
 506 static void
 507 i915_destroy_screen(struct pipe_screen *screen)
 508 {
 509    struct i915_screen *is = i915_screen(screen);
 510
 511    if (is->iws)
 512       is->iws->destroy(is->iws);
 513
 514    FREE(is);
 515 }
 516
 517 /**
 518  * Create a new i915_screen object
 519  */
 520 struct pipe_screen *
 521 i915_screen_create(struct i915_winsys *iws)
 522 {
 523    struct i915_screen *is = CALLOC_STRUCT(i915_screen);
 524
 525    if (!is)
 526       return NULL;
 527
 528    switch (iws->pci_id) {
 529    case PCI_CHIP_I915_G:
 530    case PCI_CHIP_I915_GM:
 531       is->is_i945 = FALSE;
 532       break;
 533
 534    case PCI_CHIP_I945_G:
 535    case PCI_CHIP_I945_GM:
 536    case PCI_CHIP_I945_GME:
 537    case PCI_CHIP_G33_G:
 538    case PCI_CHIP_Q33_G:
 539    case PCI_CHIP_Q35_G:
 540    case PCI_CHIP_PINEVIEW_G:
 541    case PCI_CHIP_PINEVIEW_M:
 542       is->is_i945 = TRUE;
 543       break;
 544
 545    default:
 546       debug_printf("%s: unknown pci id 0x%x, cannot create screen\n",
 547                    __FUNCTION__, iws->pci_id);
 548       FREE(is);
 549       return NULL;
 550    }
 551
 552    is->iws = iws;
 553
 554    is->base.destroy = i915_destroy_screen;
 555    is->base.flush_frontbuffer = i915_flush_frontbuffer;
 556
 557    is->base.get_name = i915_get_name;
 558    is->base.get_vendor = i915_get_vendor;
 559    is->base.get_device_vendor = i915_get_device_vendor;
 560    is->base.get_param = i915_get_param;
 561    is->base.get_shader_param = i915_get_shader_param;
 562    is->base.get_paramf = i915_get_paramf;
 563    is->base.is_format_supported = i915_is_format_supported;
 564
 565    is->base.context_create = i915_create_context;
 566
 567    is->base.fence_reference = i915_fence_reference;
 568    is->base.fence_finish = i915_fence_finish;
 569
 570    i915_init_screen_resource_functions(is);
 571
 572    i915_debug_init(is);
 573
 574    util_format_s3tc_init();
 575
 576    return &is->base;
 577 }