2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
25 #include "pipe/p_defines.h"
26 #include "pipe/p_state.h"
27 #include "pipe/p_context.h"
28 #include "pipe/p_screen.h"
29 #include "util/u_inlines.h"
30 #include "util/u_format.h"
31 #include "util/u_upload_mgr.h"
32 #include "util/ralloc.h"
33 #include "iris_context.h"
34 #include "iris_resource.h"
35 #include "iris_screen.h"
36 #include "intel/compiler/brw_compiler.h"
37 #include "util/format_srgb.h"
40 iris_is_color_fast_clear_compatible(struct iris_context
*ice
,
41 enum isl_format format
,
42 const union isl_color_value color
)
44 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
45 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
47 if (isl_format_has_int_channel(format
)) {
48 perf_debug(&ice
->dbg
, "Integer fast clear not enabled for %s",
49 isl_format_get_name(format
));
53 for (int i
= 0; i
< 4; i
++) {
54 if (!isl_format_has_color_component(format
, i
)) {
58 if (devinfo
->gen
< 9 &&
59 color
.f32
[i
] != 0.0f
&& color
.f32
[i
] != 1.0f
) {
68 can_fast_clear_color(struct iris_context
*ice
,
69 struct pipe_resource
*p_res
,
71 const struct pipe_box
*box
,
72 enum isl_format format
,
73 enum isl_format render_format
,
74 union isl_color_value color
)
76 struct iris_resource
*res
= (void *) p_res
;
78 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
79 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
81 /* XXX: Need to fix channel select for gen8 before enabling this. */
82 if (devinfo
->gen
!= 9)
85 if (res
->aux
.usage
== ISL_AUX_USAGE_NONE
)
88 /* Surface state can only record one fast clear color value. Therefore
89 * unless different levels/layers agree on the color it can be used to
90 * represent only single level/layer. Here it will be reserved for the
91 * first slice (level 0, layer 0).
93 if (level
> 0 || box
->z
> 0 || box
->depth
> 1)
96 /* Check for partial clear */
97 if (box
->x
> 0 || box
->y
> 0 ||
98 box
->width
< p_res
->width0
||
99 box
->height
< p_res
->height0
) {
103 /* We store clear colors as floats or uints as needed. If there are
104 * texture views in play, the formats will not properly be respected
105 * during resolves because the resolve operations only know about the
106 * resource and not the renderbuffer.
108 if (render_format
!= format
)
111 /* XXX: if (irb->mt->supports_fast_clear)
112 * see intel_miptree_create_for_dri_image()
115 if (!iris_is_color_fast_clear_compatible(ice
, format
, color
))
121 static union isl_color_value
122 convert_fast_clear_color(struct iris_context
*ice
,
123 struct iris_resource
*res
,
124 const union isl_color_value color
,
125 struct isl_swizzle swizzle
)
127 union isl_color_value override_color
= color
;
128 struct pipe_resource
*p_res
= (void *) res
;
130 const enum pipe_format format
= p_res
->format
;
131 const struct util_format_description
*desc
=
132 util_format_description(format
);
133 unsigned colormask
= util_format_colormask(desc
);
135 override_color
= swizzle_color_value(color
, swizzle
);
137 if (util_format_is_unorm(format
)) {
138 for (int i
= 0; i
< 4; i
++)
139 override_color
.f32
[i
] = CLAMP(override_color
.f32
[i
], 0.0f
, 1.0f
);
140 } else if (util_format_is_snorm(format
)) {
141 for (int i
= 0; i
< 4; i
++)
142 override_color
.f32
[i
] = CLAMP(override_color
.f32
[i
], -1.0f
, 1.0f
);
143 } else if (util_format_is_pure_uint(format
)) {
144 for (int i
= 0; i
< 4; i
++) {
145 unsigned bits
= util_format_get_component_bits(
146 format
, UTIL_FORMAT_COLORSPACE_RGB
, i
);
148 uint32_t max
= (1u << bits
) - 1;
149 override_color
.u32
[i
] = MIN2(override_color
.u32
[i
], max
);
152 } else if (util_format_is_pure_sint(format
)) {
153 for (int i
= 0; i
< 4; i
++) {
154 unsigned bits
= util_format_get_component_bits(
155 format
, UTIL_FORMAT_COLORSPACE_RGB
, i
);
157 int32_t max
= (1 << (bits
- 1)) - 1;
158 int32_t min
= -(1 << (bits
- 1));
159 override_color
.i32
[i
] = CLAMP(override_color
.i32
[i
], min
, max
);
162 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
||
163 format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
164 /* these packed float formats only store unsigned values */
165 for (int i
= 0; i
< 4; i
++)
166 override_color
.f32
[i
] = MAX2(override_color
.f32
[i
], 0.0f
);
169 if (!(colormask
& 1 << 3)) {
170 if (util_format_is_pure_integer(format
))
171 override_color
.u32
[3] = 1;
173 override_color
.f32
[3] = 1.0f
;
176 /* Handle linear to SRGB conversion */
177 if (util_format_is_srgb(format
)) {
178 for (int i
= 0; i
< 3; i
++) {
179 override_color
.f32
[i
] =
180 util_format_linear_to_srgb_float(override_color
.f32
[i
]);
184 return override_color
;
188 fast_clear_color(struct iris_context
*ice
,
189 struct iris_resource
*res
,
191 const struct pipe_box
*box
,
192 enum isl_format format
,
193 union isl_color_value color
,
194 struct isl_swizzle swizzle
,
195 enum blorp_batch_flags blorp_flags
)
197 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
198 struct pipe_resource
*p_res
= (void *) res
;
199 const enum isl_aux_state aux_state
=
200 iris_resource_get_aux_state(res
, level
, box
->z
);
202 color
= convert_fast_clear_color(ice
, res
, color
, swizzle
);
204 bool color_changed
= !!memcmp(&res
->aux
.clear_color
, &color
,
208 /* We decided that we are going to fast clear, and the color is
209 * changing. But if we have a predicate bit set, the predication
210 * affects whether we should clear or not, and if we shouldn't, we
211 * also shouldn't update the clear color.
213 * However, we can't simply predicate-update the clear color (the
214 * commands don't support that). And we would lose track of the
215 * color, preventing us from doing some optimizations later.
217 * Since changing the clear color when the predication bit is enabled
218 * is not something that should happen often, we stall on the CPU here
219 * to resolve the predication, and then proceed.
221 iris_resolve_conditional_render(ice
);
222 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_DONT_RENDER
)
226 iris_resource_set_clear_color(ice
, res
, color
);
228 /* If the buffer is already in ISL_AUX_STATE_CLEAR, and the color hasn't
229 * changed, the clear is redundant and can be skipped.
231 if (!color_changed
&& aux_state
== ISL_AUX_STATE_CLEAR
)
234 /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
236 * "Any transition from any value in {Clear, Render, Resolve} to a
237 * different value in {Clear, Render, Resolve} requires end of pipe
240 * In other words, fast clear ops are not properly synchronized with
241 * other drawing. We need to use a PIPE_CONTROL to ensure that the
242 * contents of the previous draw hit the render target before we resolve
243 * and again afterwards to ensure that the resolve is complete before we
244 * do any more regular drawing.
246 iris_emit_end_of_pipe_sync(batch
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
248 /* If we reach this point, we need to fast clear to change the state to
249 * ISL_AUX_STATE_CLEAR, or to update the fast clear color (or both).
251 blorp_flags
|= color_changed
? 0 : BLORP_BATCH_NO_UPDATE_CLEAR_COLOR
;
253 struct blorp_batch blorp_batch
;
254 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, blorp_flags
);
256 struct blorp_surf surf
;
257 iris_blorp_surf_for_resource(&ice
->vtbl
, &surf
, p_res
, res
->aux
.usage
,
260 blorp_fast_clear(&blorp_batch
, &surf
, format
,
261 level
, box
->z
, box
->depth
,
262 box
->x
, box
->y
, box
->x
+ box
->width
,
263 box
->y
+ box
->height
);
264 blorp_batch_finish(&blorp_batch
);
265 iris_emit_end_of_pipe_sync(batch
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
267 iris_resource_set_aux_state(ice
, res
, level
, box
->z
,
268 box
->depth
, ISL_AUX_STATE_CLEAR
);
269 ice
->state
.dirty
|= IRIS_ALL_DIRTY_BINDINGS
;
274 clear_color(struct iris_context
*ice
,
275 struct pipe_resource
*p_res
,
277 const struct pipe_box
*box
,
278 bool render_condition_enabled
,
279 enum isl_format format
,
280 struct isl_swizzle swizzle
,
281 union isl_color_value color
)
283 struct iris_resource
*res
= (void *) p_res
;
285 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
286 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
287 enum blorp_batch_flags blorp_flags
= 0;
289 if (render_condition_enabled
) {
290 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_DONT_RENDER
)
293 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
)
294 blorp_flags
|= BLORP_BATCH_PREDICATE_ENABLE
;
297 iris_batch_maybe_flush(batch
, 1500);
299 bool can_fast_clear
= can_fast_clear_color(ice
, p_res
, level
, box
,
300 res
->surf
.format
, format
, color
);
301 if (can_fast_clear
) {
302 fast_clear_color(ice
, res
, level
, box
, format
, color
,
303 swizzle
, blorp_flags
);
307 bool color_write_disable
[4] = { false, false, false, false };
308 enum isl_aux_usage aux_usage
=
309 iris_resource_render_aux_usage(ice
, res
, format
,
312 iris_resource_prepare_render(ice
, batch
, res
, level
,
313 box
->z
, box
->depth
, aux_usage
);
315 struct blorp_surf surf
;
316 iris_blorp_surf_for_resource(&ice
->vtbl
, &surf
, p_res
, aux_usage
, level
,
319 struct blorp_batch blorp_batch
;
320 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, blorp_flags
);
322 if (!isl_format_supports_rendering(devinfo
, format
) &&
323 isl_format_is_rgbx(format
))
324 format
= isl_format_rgbx_to_rgba(format
);
326 blorp_clear(&blorp_batch
, &surf
, format
, swizzle
,
327 level
, box
->z
, box
->depth
, box
->x
, box
->y
,
328 box
->x
+ box
->width
, box
->y
+ box
->height
,
329 color
, color_write_disable
);
331 blorp_batch_finish(&blorp_batch
);
332 iris_flush_and_dirty_for_history(ice
, batch
, res
);
334 iris_resource_finish_render(ice
, res
, level
,
335 box
->z
, box
->depth
, aux_usage
);
339 can_fast_clear_depth(struct iris_context
*ice
,
340 struct iris_resource
*res
,
342 const struct pipe_box
*box
,
345 struct pipe_resource
*p_res
= (void *) res
;
347 /* Check for partial clears */
348 if (box
->x
> 0 || box
->y
> 0 ||
349 box
->width
< u_minify(p_res
->width0
, level
) ||
350 box
->height
< u_minify(p_res
->height0
, level
)) {
354 if (!(res
->aux
.has_hiz
& (1 << level
)))
361 fast_clear_depth(struct iris_context
*ice
,
362 struct iris_resource
*res
,
364 const struct pipe_box
*box
,
367 struct pipe_resource
*p_res
= (void *) res
;
368 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
370 /* Quantize the clear value to what can be stored in the actual depth
371 * buffer. This makes the following check more accurate because it now
372 * checks if the actual depth bits will match. It also prevents us from
373 * getting a too-accurate depth value during depth testing or when sampling
376 const unsigned nbits
= p_res
->format
== PIPE_FORMAT_Z16_UNORM
? 16 : 24;
377 const uint32_t depth_max
= (1 << nbits
) - 1;
378 depth
= p_res
->format
== PIPE_FORMAT_Z32_FLOAT
? depth
:
379 (unsigned)(depth
* depth_max
) / (float)depth_max
;
381 bool update_clear_depth
= false;
383 /* If we're clearing to a new clear value, then we need to resolve any clear
384 * flags out of the HiZ buffer into the real depth buffer.
386 if (res
->aux
.clear_color
.f32
[0] != depth
) {
387 /* We decided that we are going to fast clear, and the color is
388 * changing. But if we have a predicate bit set, the predication
389 * affects whether we should clear or not, and if we shouldn't, we
390 * also shouldn't update the clear color.
392 * However, we can't simply predicate-update the clear color (the
393 * commands don't support that). And we would lose track of the
394 * color, preventing us from doing some optimizations later.
396 * For depth clears, things are even more complicated, because here we
397 * resolve the other levels/layers if they have a different color than
398 * the current one. That resolve can be predicated, but we also set those
399 * layers as ISL_AUX_STATE_RESOLVED, and this can't be predicated.
400 * Keeping track of the aux state when predication is involved is just
401 * even more complex, so the easiest thing to do when the fast clear
402 * depth is changing is to stall on the CPU and resolve the predication.
404 iris_resolve_conditional_render(ice
);
405 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_DONT_RENDER
)
408 for (unsigned res_level
= 0; res_level
< res
->surf
.levels
; res_level
++) {
409 if (!(res
->aux
.has_hiz
& (1 << res_level
)))
412 const unsigned level_layers
=
413 iris_get_num_logical_layers(res
, res_level
);
414 for (unsigned layer
= 0; layer
< level_layers
; layer
++) {
415 if (res_level
== level
&&
417 layer
< box
->z
+ box
->depth
) {
418 /* We're going to clear this layer anyway. Leave it alone. */
422 enum isl_aux_state aux_state
=
423 iris_resource_get_aux_state(res
, res_level
, layer
);
425 if (aux_state
!= ISL_AUX_STATE_CLEAR
&&
426 aux_state
!= ISL_AUX_STATE_COMPRESSED_CLEAR
) {
427 /* This slice doesn't have any fast-cleared bits. */
431 /* If we got here, then the level may have fast-clear bits that
432 * use the old clear value. We need to do a depth resolve to get
433 * rid of their use of the clear value before we can change it.
434 * Fortunately, few applications ever change their depth clear
435 * value so this shouldn't happen often.
437 iris_hiz_exec(ice
, batch
, res
, res_level
, layer
, 1,
438 ISL_AUX_OP_FULL_RESOLVE
, false);
439 iris_resource_set_aux_state(ice
, res
, res_level
, layer
, 1,
440 ISL_AUX_STATE_RESOLVED
);
443 const union isl_color_value clear_value
= { .f32
= {depth
, } };
444 iris_resource_set_clear_color(ice
, res
, clear_value
);
445 update_clear_depth
= true;
448 for (unsigned l
= 0; l
< box
->depth
; l
++) {
449 enum isl_aux_state aux_state
=
450 iris_resource_get_aux_state(res
, level
, box
->z
+ l
);
451 if (aux_state
!= ISL_AUX_STATE_CLEAR
) {
452 iris_hiz_exec(ice
, batch
, res
, level
,
453 box
->z
+ l
, 1, ISL_AUX_OP_FAST_CLEAR
,
458 iris_resource_set_aux_state(ice
, res
, level
, box
->z
, box
->depth
,
459 ISL_AUX_STATE_CLEAR
);
460 ice
->state
.dirty
|= IRIS_DIRTY_DEPTH_BUFFER
;
464 clear_depth_stencil(struct iris_context
*ice
,
465 struct pipe_resource
*p_res
,
467 const struct pipe_box
*box
,
468 bool render_condition_enabled
,
474 struct iris_resource
*res
= (void *) p_res
;
476 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
477 enum blorp_batch_flags blorp_flags
= 0;
479 if (render_condition_enabled
) {
480 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_DONT_RENDER
)
483 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
)
484 blorp_flags
|= BLORP_BATCH_PREDICATE_ENABLE
;
487 iris_batch_maybe_flush(batch
, 1500);
489 struct iris_resource
*z_res
;
490 struct iris_resource
*stencil_res
;
491 struct blorp_surf z_surf
;
492 struct blorp_surf stencil_surf
;
494 iris_get_depth_stencil_resources(p_res
, &z_res
, &stencil_res
);
495 if (z_res
&& clear_depth
&&
496 can_fast_clear_depth(ice
, z_res
, level
, box
, depth
)) {
497 fast_clear_depth(ice
, z_res
, level
, box
, depth
);
498 iris_flush_and_dirty_for_history(ice
, batch
, res
);
503 /* At this point, we might have fast cleared the depth buffer. So if there's
504 * no stencil clear pending, return early.
506 if (!(clear_depth
|| clear_stencil
)) {
511 iris_resource_prepare_depth(ice
, batch
, z_res
, level
, box
->z
, box
->depth
);
512 iris_blorp_surf_for_resource(&ice
->vtbl
, &z_surf
, &z_res
->base
,
513 z_res
->aux
.usage
, level
, true);
516 struct blorp_batch blorp_batch
;
517 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, blorp_flags
);
520 iris_blorp_surf_for_resource(&ice
->vtbl
, &stencil_surf
,
521 &stencil_res
->base
, stencil_res
->aux
.usage
,
525 blorp_clear_depth_stencil(&blorp_batch
, &z_surf
, &stencil_surf
,
526 level
, box
->z
, box
->depth
,
529 box
->y
+ box
->height
,
530 clear_depth
&& z_res
, depth
,
531 clear_stencil
&& stencil_res
? 0xff : 0, stencil
);
533 blorp_batch_finish(&blorp_batch
);
534 iris_flush_and_dirty_for_history(ice
, batch
, res
);
537 iris_resource_finish_depth(ice
, z_res
, level
,
538 box
->z
, box
->depth
, true);
543 * The pipe->clear() driver hook.
545 * This clears buffers attached to the current draw framebuffer.
548 iris_clear(struct pipe_context
*ctx
,
550 const union pipe_color_union
*p_color
,
554 struct iris_context
*ice
= (void *) ctx
;
555 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
557 assert(buffers
!= 0);
559 if (buffers
& PIPE_CLEAR_DEPTHSTENCIL
) {
560 struct pipe_surface
*psurf
= cso_fb
->zsbuf
;
561 struct pipe_box box
= {
562 .width
= cso_fb
->width
,
563 .height
= cso_fb
->height
,
564 .depth
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
+ 1,
565 .z
= psurf
->u
.tex
.first_layer
,
568 clear_depth_stencil(ice
, psurf
->texture
, psurf
->u
.tex
.level
, &box
, true,
569 buffers
& PIPE_CLEAR_DEPTH
,
570 buffers
& PIPE_CLEAR_STENCIL
,
574 if (buffers
& PIPE_CLEAR_COLOR
) {
575 /* pipe_color_union and isl_color_value are interchangeable */
576 union isl_color_value
*color
= (void *) p_color
;
578 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
579 if (buffers
& (PIPE_CLEAR_COLOR0
<< i
)) {
580 struct pipe_surface
*psurf
= cso_fb
->cbufs
[i
];
581 struct iris_surface
*isurf
= (void *) psurf
;
582 struct pipe_box box
= {
583 .width
= cso_fb
->width
,
584 .height
= cso_fb
->height
,
585 .depth
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
+ 1,
586 .z
= psurf
->u
.tex
.first_layer
,
589 clear_color(ice
, psurf
->texture
, psurf
->u
.tex
.level
, &box
,
590 true, isurf
->view
.format
, isurf
->view
.swizzle
,
598 * The pipe->clear_texture() driver hook.
600 * This clears the given texture resource.
603 iris_clear_texture(struct pipe_context
*ctx
,
604 struct pipe_resource
*p_res
,
606 const struct pipe_box
*box
,
609 struct iris_context
*ice
= (void *) ctx
;
610 struct iris_screen
*screen
= (void *) ctx
->screen
;
611 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
613 if (util_format_is_depth_or_stencil(p_res
->format
)) {
614 const struct util_format_description
*fmt_desc
=
615 util_format_description(p_res
->format
);
620 if (fmt_desc
->unpack_z_float
)
621 fmt_desc
->unpack_z_float(&depth
, 0, data
, 0, 1, 1);
623 if (fmt_desc
->unpack_s_8uint
)
624 fmt_desc
->unpack_s_8uint(&stencil
, 0, data
, 0, 1, 1);
626 clear_depth_stencil(ice
, p_res
, level
, box
, true, true, true,
629 union isl_color_value color
;
630 struct iris_resource
*res
= (void *) p_res
;
631 enum isl_format format
= res
->surf
.format
;
633 if (!isl_format_supports_rendering(devinfo
, format
)) {
634 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
635 // XXX: actually just get_copy_format_for_bpb from BLORP
636 // XXX: don't cut and paste this
638 case 8: format
= ISL_FORMAT_R8_UINT
; break;
639 case 16: format
= ISL_FORMAT_R8G8_UINT
; break;
640 case 24: format
= ISL_FORMAT_R8G8B8_UINT
; break;
641 case 32: format
= ISL_FORMAT_R8G8B8A8_UINT
; break;
642 case 48: format
= ISL_FORMAT_R16G16B16_UINT
; break;
643 case 64: format
= ISL_FORMAT_R16G16B16A16_UINT
; break;
644 case 96: format
= ISL_FORMAT_R32G32B32_UINT
; break;
645 case 128: format
= ISL_FORMAT_R32G32B32A32_UINT
; break;
647 unreachable("Unknown format bpb");
650 /* No aux surfaces for non-renderable surfaces */
651 assert(res
->aux
.usage
== ISL_AUX_USAGE_NONE
);
654 isl_color_value_unpack(&color
, format
, data
);
656 clear_color(ice
, p_res
, level
, box
, true, format
,
657 ISL_SWIZZLE_IDENTITY
, color
);
662 * The pipe->clear_render_target() driver hook.
664 * This clears the given render target surface.
667 iris_clear_render_target(struct pipe_context
*ctx
,
668 struct pipe_surface
*psurf
,
669 const union pipe_color_union
*p_color
,
670 unsigned dst_x
, unsigned dst_y
,
671 unsigned width
, unsigned height
,
672 bool render_condition_enabled
)
674 struct iris_context
*ice
= (void *) ctx
;
675 struct iris_surface
*isurf
= (void *) psurf
;
676 struct pipe_box box
= {
679 .z
= psurf
->u
.tex
.first_layer
,
682 .depth
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
+ 1
685 /* pipe_color_union and isl_color_value are interchangeable */
686 union isl_color_value
*color
= (void *) p_color
;
688 clear_color(ice
, psurf
->texture
, psurf
->u
.tex
.level
, &box
,
689 render_condition_enabled
,
690 isurf
->view
.format
, isurf
->view
.swizzle
, *color
);
694 * The pipe->clear_depth_stencil() driver hook.
696 * This clears the given depth/stencil surface.
699 iris_clear_depth_stencil(struct pipe_context
*ctx
,
700 struct pipe_surface
*psurf
,
704 unsigned dst_x
, unsigned dst_y
,
705 unsigned width
, unsigned height
,
706 bool render_condition_enabled
)
708 struct iris_context
*ice
= (void *) ctx
;
709 struct pipe_box box
= {
712 .z
= psurf
->u
.tex
.first_layer
,
715 .depth
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
+ 1
718 assert(util_format_is_depth_or_stencil(psurf
->texture
->format
));
720 clear_depth_stencil(ice
, psurf
->texture
, psurf
->u
.tex
.level
, &box
,
721 render_condition_enabled
,
722 flags
& PIPE_CLEAR_DEPTH
, flags
& PIPE_CLEAR_STENCIL
,
727 iris_init_clear_functions(struct pipe_context
*ctx
)
729 ctx
->clear
= iris_clear
;
730 ctx
->clear_texture
= iris_clear_texture
;
731 ctx
->clear_render_target
= iris_clear_render_target
;
732 ctx
->clear_depth_stencil
= iris_clear_depth_stencil
;