src/gallium/drivers/iris/iris_resource.h

   1 /*
   2  * Copyright 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #ifndef IRIS_RESOURCE_H
  24 #define IRIS_RESOURCE_H
  25
  26 #include "pipe/p_state.h"
  27 #include "util/u_inlines.h"
  28 #include "util/u_range.h"
  29 #include "intel/isl/isl.h"
  30
  31 struct iris_batch;
  32 struct iris_context;
  33
  34 #define IRIS_MAX_MIPLEVELS 15
  35
  36 struct iris_format_info {
  37    enum isl_format fmt;
  38    struct isl_swizzle swizzle;
  39 };
  40
  41 #define IRIS_RESOURCE_FLAG_SHADER_MEMZONE  (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  42 #define IRIS_RESOURCE_FLAG_SURFACE_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  43 #define IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  44
  45 enum gen9_astc5x5_wa_tex_type {
  46    GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5 = 1 << 0,
  47    GEN9_ASTC5X5_WA_TEX_TYPE_AUX     = 1 << 1,
  48 };
  49
  50 /**
  51  * Resources represent a GPU buffer object or image (mipmap tree).
  52  *
  53  * They contain the storage (BO) and layout information (ISL surface).
  54  */
  55 struct iris_resource {
  56    struct pipe_resource base;
  57    enum pipe_format internal_format;
  58
  59    /**
  60     * The ISL surface layout information for this resource.
  61     *
  62     * This is not filled out for PIPE_BUFFER resources, but is guaranteed
  63     * to be zeroed.  Note that this also guarantees that res->surf.tiling
  64     * will be ISL_TILING_LINEAR, so it's safe to check that.
  65     */
  66    struct isl_surf surf;
  67
  68    /** Backing storage for the resource */
  69    struct iris_bo *bo;
  70
  71    /** offset at which data starts in the BO */
  72    uint64_t offset;
  73
  74    /**
  75     * A bitfield of PIPE_BIND_* indicating how this resource was bound
  76     * in the past.  Only meaningful for PIPE_BUFFER; used for flushing.
  77     */
  78    unsigned bind_history;
  79
  80    /**
  81     * For PIPE_BUFFER resources, a range which may contain valid data.
  82     *
  83     * This is a conservative estimate of what part of the buffer contains
  84     * valid data that we have to preserve.  The rest of the buffer is
  85     * considered invalid, and we can promote writes to that region to
  86     * be unsynchronized writes, avoiding blit copies.
  87     */
  88    struct util_range valid_buffer_range;
  89
  90    /**
  91     * Auxiliary buffer information (CCS, MCS, or HiZ).
  92     */
  93    struct {
  94       /** The surface layout for the auxiliary buffer. */
  95       struct isl_surf surf;
  96
  97       /** The buffer object containing the auxiliary data. */
  98       struct iris_bo *bo;
  99
 100       /** Offset into 'bo' where the auxiliary surface starts. */
 101       uint32_t offset;
 102
 103       /**
 104        * Fast clear color for this surface.  For depth surfaces, the clear
 105        * value is stored as a float32 in the red component.
 106        */
 107       union isl_color_value clear_color;
 108
 109       /** Buffer object containing the indirect clear color.  */
 110       struct iris_bo *clear_color_bo;
 111
 112       /** Offset into bo where the clear color can be found.  */
 113       uint64_t clear_color_offset;
 114
 115       /**
 116        * \brief The type of auxiliary compression used by this resource.
 117        *
 118        * This describes the type of auxiliary compression that is intended to
 119        * be used by this resource.  An aux usage of ISL_AUX_USAGE_NONE means
 120        * that auxiliary compression is permanently disabled.  An aux usage
 121        * other than ISL_AUX_USAGE_NONE does not imply that auxiliary
 122        * compression will always be enabled for this surface.
 123        */
 124       enum isl_aux_usage usage;
 125
 126       /**
 127        * A bitfield of ISL_AUX_* modes that might this resource might use.
 128        *
 129        * For example, a surface might use both CCS_E and CCS_D at times.
 130        */
 131       unsigned possible_usages;
 132
 133       /**
 134        * Same as possible_usages, but only with modes supported for sampling.
 135        */
 136       unsigned sampler_usages;
 137
 138       /**
 139        * \brief Maps miptree slices to their current aux state.
 140        *
 141        * This two-dimensional array is indexed as [level][layer] and stores an
 142        * aux state for each slice.
 143        */
 144       enum isl_aux_state **state;
 145
 146       /**
 147        * If (1 << level) is set, HiZ is enabled for that miplevel.
 148        */
 149       uint16_t has_hiz;
 150    } aux;
 151
 152    /**
 153     * For external surfaces, this is DRM format modifier that was used to
 154     * create or import the surface.  For internal surfaces, this will always
 155     * be DRM_FORMAT_MOD_INVALID.
 156     */
 157    const struct isl_drm_modifier_info *mod_info;
 158 };
 159
 160 /**
 161  * A simple <resource, offset> tuple for storing a reference to a
 162  * piece of state stored in a GPU buffer object.
 163  */
 164 struct iris_state_ref {
 165    struct pipe_resource *res;
 166    uint32_t offset;
 167 };
 168
 169 /**
 170  * Gallium CSO for sampler views (texture views).
 171  *
 172  * In addition to the normal pipe_resource, this adds an ISL view
 173  * which may reinterpret the format or restrict levels/layers.
 174  *
 175  * These can also be linear texture buffers.
 176  */
 177 struct iris_sampler_view {
 178    struct pipe_sampler_view base;
 179    struct isl_view view;
 180
 181    union isl_color_value clear_color;
 182
 183    /* A short-cut (not a reference) to the actual resource being viewed.
 184     * Multi-planar (or depth+stencil) images may have multiple resources
 185     * chained together; this skips having to traverse base->texture->*.
 186     */
 187    struct iris_resource *res;
 188
 189    /** The resource (BO) holding our SURFACE_STATE. */
 190    struct iris_state_ref surface_state;
 191 };
 192
 193 /**
 194  * Image view representation.
 195  */
 196 struct iris_image_view {
 197    struct pipe_image_view base;
 198
 199    /** The resource (BO) holding our SURFACE_STATE. */
 200    struct iris_state_ref surface_state;
 201 };
 202
 203 /**
 204  * Gallium CSO for surfaces (framebuffer attachments).
 205  *
 206  * A view of a surface that can be bound to a color render target or
 207  * depth/stencil attachment.
 208  */
 209 struct iris_surface {
 210    struct pipe_surface base;
 211    struct isl_view view;
 212    struct isl_view read_view;
 213    union isl_color_value clear_color;
 214
 215    /** The resource (BO) holding our SURFACE_STATE. */
 216    struct iris_state_ref surface_state;
 217    /** The resource (BO) holding our SURFACE_STATE for read. */
 218    struct iris_state_ref surface_state_read;
 219 };
 220
 221 /**
 222  * Transfer object - information about a buffer mapping.
 223  */
 224 struct iris_transfer {
 225    struct pipe_transfer base;
 226    struct pipe_debug_callback *dbg;
 227    void *buffer;
 228    void *ptr;
 229
 230    /** A linear staging resource for GPU-based copy_region transfers. */
 231    struct pipe_resource *staging;
 232    struct blorp_context *blorp;
 233    struct iris_batch *batch;
 234
 235    void (*unmap)(struct iris_transfer *);
 236 };
 237
 238 /**
 239  * Unwrap a pipe_resource to get the underlying iris_bo (for convenience).
 240  */
 241 static inline struct iris_bo *
 242 iris_resource_bo(struct pipe_resource *p_res)
 243 {
 244    struct iris_resource *res = (void *) p_res;
 245    return res->bo;
 246 }
 247
 248 struct iris_format_info iris_format_for_usage(const struct gen_device_info *,
 249                                               enum pipe_format pf,
 250                                               isl_surf_usage_flags_t usage);
 251
 252 struct pipe_resource *iris_resource_get_separate_stencil(struct pipe_resource *);
 253
 254 void iris_get_depth_stencil_resources(struct pipe_resource *res,
 255                                       struct iris_resource **out_z,
 256                                       struct iris_resource **out_s);
 257 bool iris_resource_set_clear_color(struct iris_context *ice,
 258                                    struct iris_resource *res,
 259                                    union isl_color_value color);
 260 union isl_color_value
 261 iris_resource_get_clear_color(const struct iris_resource *res,
 262                               struct iris_bo **clear_color_bo,
 263                               uint64_t *clear_color_offset);
 264
 265 void iris_init_screen_resource_functions(struct pipe_screen *pscreen);
 266
 267 void iris_dirty_for_history(struct iris_context *ice,
 268                             struct iris_resource *res);
 269 uint32_t iris_flush_bits_for_history(struct iris_resource *res);
 270
 271 void iris_flush_and_dirty_for_history(struct iris_context *ice,
 272                                       struct iris_batch *batch,
 273                                       struct iris_resource *res,
 274                                       uint32_t extra_flags,
 275                                       const char *reason);
 276
 277 unsigned iris_get_num_logical_layers(const struct iris_resource *res,
 278                                      unsigned level);
 279
 280 void iris_resource_disable_aux(struct iris_resource *res);
 281
 282 #define INTEL_REMAINING_LAYERS UINT32_MAX
 283 #define INTEL_REMAINING_LEVELS UINT32_MAX
 284
 285 void
 286 iris_hiz_exec(struct iris_context *ice,
 287               struct iris_batch *batch,
 288               struct iris_resource *res,
 289               unsigned int level, unsigned int start_layer,
 290               unsigned int num_layers, enum isl_aux_op op,
 291               bool update_clear_depth);
 292
 293 /**
 294  * Prepare a miptree for access
 295  *
 296  * This function should be called prior to any access to miptree in order to
 297  * perform any needed resolves.
 298  *
 299  * \param[in]  start_level    The first mip level to be accessed
 300  *
 301  * \param[in]  num_levels     The number of miplevels to be accessed or
 302  *                            INTEL_REMAINING_LEVELS to indicate every level
 303  *                            above start_level will be accessed
 304  *
 305  * \param[in]  start_layer    The first array slice or 3D layer to be accessed
 306  *
 307  * \param[in]  num_layers     The number of array slices or 3D layers be
 308  *                            accessed or INTEL_REMAINING_LAYERS to indicate
 309  *                            every layer above start_layer will be accessed
 310  *
 311  * \param[in]  aux_supported  Whether or not the access will support the
 312  *                            miptree's auxiliary compression format;  this
 313  *                            must be false for uncompressed miptrees
 314  *
 315  * \param[in]  fast_clear_supported Whether or not the access will support
 316  *                                  fast clears in the miptree's auxiliary
 317  *                                  compression format
 318  */
 319 void
 320 iris_resource_prepare_access(struct iris_context *ice,
 321                              struct iris_batch *batch,
 322                              struct iris_resource *res,
 323                              uint32_t start_level, uint32_t num_levels,
 324                              uint32_t start_layer, uint32_t num_layers,
 325                              enum isl_aux_usage aux_usage,
 326                              bool fast_clear_supported);
 327
 328 /**
 329  * Complete a write operation
 330  *
 331  * This function should be called after any operation writes to a miptree.
 332  * This will update the miptree's compression state so that future resolves
 333  * happen correctly.  Technically, this function can be called before the
 334  * write occurs but the caller must ensure that they don't interlace
 335  * iris_resource_prepare_access and iris_resource_finish_write calls to
 336  * overlapping layer/level ranges.
 337  *
 338  * \param[in]  level             The mip level that was written
 339  *
 340  * \param[in]  start_layer       The first array slice or 3D layer written
 341  *
 342  * \param[in]  num_layers        The number of array slices or 3D layers
 343  *                               written or INTEL_REMAINING_LAYERS to indicate
 344  *                               every layer above start_layer was written
 345  *
 346  * \param[in]  written_with_aux  Whether or not the write was done with
 347  *                               auxiliary compression enabled
 348  */
 349 void
 350 iris_resource_finish_write(struct iris_context *ice,
 351                            struct iris_resource *res, uint32_t level,
 352                            uint32_t start_layer, uint32_t num_layers,
 353                            enum isl_aux_usage aux_usage);
 354
 355 /** Get the auxiliary compression state of a miptree slice */
 356 enum isl_aux_state
 357 iris_resource_get_aux_state(const struct iris_resource *res,
 358                             uint32_t level, uint32_t layer);
 359
 360 /**
 361  * Set the auxiliary compression state of a miptree slice range
 362  *
 363  * This function directly sets the auxiliary compression state of a slice
 364  * range of a miptree.  It only modifies data structures and does not do any
 365  * resolves.  This should only be called by code which directly performs
 366  * compression operations such as fast clears and resolves.  Most code should
 367  * use iris_resource_prepare_access or iris_resource_finish_write.
 368  */
 369 void
 370 iris_resource_set_aux_state(struct iris_context *ice,
 371                             struct iris_resource *res, uint32_t level,
 372                             uint32_t start_layer, uint32_t num_layers,
 373                             enum isl_aux_state aux_state);
 374
 375 /**
 376  * Prepare a miptree for raw access
 377  *
 378  * This helper prepares the miptree for access that knows nothing about any
 379  * sort of compression whatsoever.  This is useful when mapping the surface or
 380  * using it with the blitter.
 381  */
 382 static inline void
 383 iris_resource_access_raw(struct iris_context *ice,
 384                          struct iris_batch *batch,
 385                          struct iris_resource *res,
 386                          uint32_t level, uint32_t layer,
 387                          uint32_t num_layers,
 388                          bool write)
 389 {
 390    iris_resource_prepare_access(ice, batch, res, level, 1, layer, num_layers,
 391                                 ISL_AUX_USAGE_NONE, false);
 392    if (write) {
 393       iris_resource_finish_write(ice, res, level, layer, num_layers,
 394                                  ISL_AUX_USAGE_NONE);
 395    }
 396 }
 397
 398 enum isl_dim_layout iris_get_isl_dim_layout(const struct gen_device_info *devinfo,
 399                                             enum isl_tiling tiling,
 400                                             enum pipe_texture_target target);
 401 enum isl_surf_dim target_to_isl_surf_dim(enum pipe_texture_target target);
 402 uint32_t iris_resource_get_tile_offsets(const struct iris_resource *res,
 403                                         uint32_t level, uint32_t z,
 404                                         uint32_t *tile_x, uint32_t *tile_y);
 405 enum isl_aux_usage iris_resource_texture_aux_usage(struct iris_context *ice,
 406                                                    const struct iris_resource *res,
 407                                                    enum isl_format view_fmt,
 408                                                    enum gen9_astc5x5_wa_tex_type);
 409 void iris_resource_prepare_texture(struct iris_context *ice,
 410                                    struct iris_batch *batch,
 411                                    struct iris_resource *res,
 412                                    enum isl_format view_format,
 413                                    uint32_t start_level, uint32_t num_levels,
 414                                    uint32_t start_layer, uint32_t num_layers,
 415                                    enum gen9_astc5x5_wa_tex_type);
 416 void iris_resource_prepare_image(struct iris_context *ice,
 417                                  struct iris_batch *batch,
 418                                  struct iris_resource *res);
 419
 420 static inline bool
 421 iris_resource_unfinished_aux_import(struct iris_resource *res)
 422 {
 423    return res->base.next != NULL && res->mod_info &&
 424       res->mod_info->aux_usage != ISL_AUX_USAGE_NONE;
 425 }
 426
 427 void iris_resource_finish_aux_import(struct pipe_screen *pscreen,
 428                                      struct iris_resource *res);
 429
 430 bool iris_has_color_unresolved(const struct iris_resource *res,
 431                                unsigned start_level, unsigned num_levels,
 432                                unsigned start_layer, unsigned num_layers);
 433
 434 void iris_resource_check_level_layer(const struct iris_resource *res,
 435                                      uint32_t level, uint32_t layer);
 436
 437 bool iris_resource_level_has_hiz(const struct iris_resource *res,
 438                                  uint32_t level);
 439 bool iris_has_color_unresolved(const struct iris_resource *res,
 440                                unsigned start_level, unsigned num_levels,
 441                                unsigned start_layer, unsigned num_layers);
 442
 443 enum isl_aux_usage iris_resource_render_aux_usage(struct iris_context *ice,
 444                                                   struct iris_resource *res,
 445                                                   enum isl_format render_fmt,
 446                                                   bool blend_enabled,
 447                                                   bool draw_aux_disabled);
 448 void iris_resource_prepare_render(struct iris_context *ice,
 449                                   struct iris_batch *batch,
 450                                   struct iris_resource *res, uint32_t level,
 451                                   uint32_t start_layer, uint32_t layer_count,
 452                                   enum isl_aux_usage aux_usage);
 453 void iris_resource_finish_render(struct iris_context *ice,
 454                                  struct iris_resource *res, uint32_t level,
 455                                  uint32_t start_layer, uint32_t layer_count,
 456                                  enum isl_aux_usage aux_usage);
 457 void iris_resource_prepare_depth(struct iris_context *ice,
 458                                  struct iris_batch *batch,
 459                                  struct iris_resource *res, uint32_t level,
 460                                  uint32_t start_layer, uint32_t layer_count);
 461 void iris_resource_finish_depth(struct iris_context *ice,
 462                                 struct iris_resource *res, uint32_t level,
 463                                 uint32_t start_layer, uint32_t layer_count,
 464                                 bool depth_written);
 465 #endif