2 * Copyright 2017 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #ifndef IRIS_RESOURCE_H
24 #define IRIS_RESOURCE_H
26 #include "pipe/p_state.h"
27 #include "util/u_inlines.h"
28 #include "util/u_range.h"
29 #include "intel/isl/isl.h"
34 #define IRIS_MAX_MIPLEVELS 15
36 struct iris_format_info
{
38 struct isl_swizzle swizzle
;
41 #define IRIS_RESOURCE_FLAG_SHADER_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
42 #define IRIS_RESOURCE_FLAG_SURFACE_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
43 #define IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
45 enum gen9_astc5x5_wa_tex_type
{
46 GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5
= 1 << 0,
47 GEN9_ASTC5X5_WA_TEX_TYPE_AUX
= 1 << 1,
51 * Resources represent a GPU buffer object or image (mipmap tree).
53 * They contain the storage (BO) and layout information (ISL surface).
55 struct iris_resource
{
56 struct pipe_resource base
;
57 enum pipe_format internal_format
;
60 * The ISL surface layout information for this resource.
62 * This is not filled out for PIPE_BUFFER resources, but is guaranteed
63 * to be zeroed. Note that this also guarantees that res->surf.tiling
64 * will be ISL_TILING_LINEAR, so it's safe to check that.
68 /** Backing storage for the resource */
71 /** offset at which data starts in the BO */
75 * A bitfield of PIPE_BIND_* indicating how this resource was bound
76 * in the past. Only meaningful for PIPE_BUFFER; used for flushing.
78 unsigned bind_history
;
81 * A bitfield of MESA_SHADER_* stages indicating where this resource
87 * For PIPE_BUFFER resources, a range which may contain valid data.
89 * This is a conservative estimate of what part of the buffer contains
90 * valid data that we have to preserve. The rest of the buffer is
91 * considered invalid, and we can promote writes to that region to
92 * be unsynchronized writes, avoiding blit copies.
94 struct util_range valid_buffer_range
;
97 * Auxiliary buffer information (CCS, MCS, or HiZ).
100 /** The surface layout for the auxiliary buffer. */
101 struct isl_surf surf
;
103 /** The buffer object containing the auxiliary data. */
106 /** Offset into 'bo' where the auxiliary surface starts. */
110 struct isl_surf surf
;
112 /** The buffer object containing the auxiliary data. */
115 /** Offset into 'bo' where the auxiliary surface starts. */
120 * Fast clear color for this surface. For depth surfaces, the clear
121 * value is stored as a float32 in the red component.
123 union isl_color_value clear_color
;
125 /** Buffer object containing the indirect clear color. */
126 struct iris_bo
*clear_color_bo
;
128 /** Offset into bo where the clear color can be found. */
129 uint64_t clear_color_offset
;
132 * \brief The type of auxiliary compression used by this resource.
134 * This describes the type of auxiliary compression that is intended to
135 * be used by this resource. An aux usage of ISL_AUX_USAGE_NONE means
136 * that auxiliary compression is permanently disabled. An aux usage
137 * other than ISL_AUX_USAGE_NONE does not imply that auxiliary
138 * compression will always be enabled for this surface.
140 enum isl_aux_usage usage
;
143 * A bitfield of ISL_AUX_* modes that might this resource might use.
145 * For example, a surface might use both CCS_E and CCS_D at times.
147 unsigned possible_usages
;
150 * Same as possible_usages, but only with modes supported for sampling.
152 unsigned sampler_usages
;
155 * \brief Maps miptree slices to their current aux state.
157 * This two-dimensional array is indexed as [level][layer] and stores an
158 * aux state for each slice.
160 enum isl_aux_state
**state
;
163 * If (1 << level) is set, HiZ is enabled for that miplevel.
169 * For external surfaces, this is DRM format modifier that was used to
170 * create or import the surface. For internal surfaces, this will always
171 * be DRM_FORMAT_MOD_INVALID.
173 const struct isl_drm_modifier_info
*mod_info
;
177 * A simple <resource, offset> tuple for storing a reference to a
178 * piece of state stored in a GPU buffer object.
180 struct iris_state_ref
{
181 struct pipe_resource
*res
;
186 * Gallium CSO for sampler views (texture views).
188 * In addition to the normal pipe_resource, this adds an ISL view
189 * which may reinterpret the format or restrict levels/layers.
191 * These can also be linear texture buffers.
193 struct iris_sampler_view
{
194 struct pipe_sampler_view base
;
195 struct isl_view view
;
197 union isl_color_value clear_color
;
199 /* A short-cut (not a reference) to the actual resource being viewed.
200 * Multi-planar (or depth+stencil) images may have multiple resources
201 * chained together; this skips having to traverse base->texture->*.
203 struct iris_resource
*res
;
205 /** The resource (BO) holding our SURFACE_STATE. */
206 struct iris_state_ref surface_state
;
210 * Image view representation.
212 struct iris_image_view
{
213 struct pipe_image_view base
;
215 /** The resource (BO) holding our SURFACE_STATE. */
216 struct iris_state_ref surface_state
;
220 * Gallium CSO for surfaces (framebuffer attachments).
222 * A view of a surface that can be bound to a color render target or
223 * depth/stencil attachment.
225 struct iris_surface
{
226 struct pipe_surface base
;
227 struct isl_view view
;
228 struct isl_view read_view
;
229 union isl_color_value clear_color
;
231 /** The resource (BO) holding our SURFACE_STATE. */
232 struct iris_state_ref surface_state
;
233 /** The resource (BO) holding our SURFACE_STATE for read. */
234 struct iris_state_ref surface_state_read
;
238 * Transfer object - information about a buffer mapping.
240 struct iris_transfer
{
241 struct pipe_transfer base
;
242 struct pipe_debug_callback
*dbg
;
246 /** A linear staging resource for GPU-based copy_region transfers. */
247 struct pipe_resource
*staging
;
248 struct blorp_context
*blorp
;
249 struct iris_batch
*batch
;
251 bool dest_had_defined_contents
;
253 void (*unmap
)(struct iris_transfer
*);
257 * Unwrap a pipe_resource to get the underlying iris_bo (for convenience).
259 static inline struct iris_bo
*
260 iris_resource_bo(struct pipe_resource
*p_res
)
262 struct iris_resource
*res
= (void *) p_res
;
266 struct iris_format_info
iris_format_for_usage(const struct gen_device_info
*,
268 isl_surf_usage_flags_t usage
);
270 struct pipe_resource
*iris_resource_get_separate_stencil(struct pipe_resource
*);
272 void iris_get_depth_stencil_resources(struct pipe_resource
*res
,
273 struct iris_resource
**out_z
,
274 struct iris_resource
**out_s
);
275 bool iris_resource_set_clear_color(struct iris_context
*ice
,
276 struct iris_resource
*res
,
277 union isl_color_value color
);
278 union isl_color_value
279 iris_resource_get_clear_color(const struct iris_resource
*res
,
280 struct iris_bo
**clear_color_bo
,
281 uint64_t *clear_color_offset
);
283 void iris_init_screen_resource_functions(struct pipe_screen
*pscreen
);
285 void iris_dirty_for_history(struct iris_context
*ice
,
286 struct iris_resource
*res
);
287 uint32_t iris_flush_bits_for_history(struct iris_resource
*res
);
289 void iris_flush_and_dirty_for_history(struct iris_context
*ice
,
290 struct iris_batch
*batch
,
291 struct iris_resource
*res
,
292 uint32_t extra_flags
,
295 unsigned iris_get_num_logical_layers(const struct iris_resource
*res
,
298 void iris_resource_disable_aux(struct iris_resource
*res
);
300 #define INTEL_REMAINING_LAYERS UINT32_MAX
301 #define INTEL_REMAINING_LEVELS UINT32_MAX
304 iris_hiz_exec(struct iris_context
*ice
,
305 struct iris_batch
*batch
,
306 struct iris_resource
*res
,
307 unsigned int level
, unsigned int start_layer
,
308 unsigned int num_layers
, enum isl_aux_op op
,
309 bool update_clear_depth
);
312 * Prepare a miptree for access
314 * This function should be called prior to any access to miptree in order to
315 * perform any needed resolves.
317 * \param[in] start_level The first mip level to be accessed
319 * \param[in] num_levels The number of miplevels to be accessed or
320 * INTEL_REMAINING_LEVELS to indicate every level
321 * above start_level will be accessed
323 * \param[in] start_layer The first array slice or 3D layer to be accessed
325 * \param[in] num_layers The number of array slices or 3D layers be
326 * accessed or INTEL_REMAINING_LAYERS to indicate
327 * every layer above start_layer will be accessed
329 * \param[in] aux_supported Whether or not the access will support the
330 * miptree's auxiliary compression format; this
331 * must be false for uncompressed miptrees
333 * \param[in] fast_clear_supported Whether or not the access will support
334 * fast clears in the miptree's auxiliary
338 iris_resource_prepare_access(struct iris_context
*ice
,
339 struct iris_batch
*batch
,
340 struct iris_resource
*res
,
341 uint32_t start_level
, uint32_t num_levels
,
342 uint32_t start_layer
, uint32_t num_layers
,
343 enum isl_aux_usage aux_usage
,
344 bool fast_clear_supported
);
347 * Complete a write operation
349 * This function should be called after any operation writes to a miptree.
350 * This will update the miptree's compression state so that future resolves
351 * happen correctly. Technically, this function can be called before the
352 * write occurs but the caller must ensure that they don't interlace
353 * iris_resource_prepare_access and iris_resource_finish_write calls to
354 * overlapping layer/level ranges.
356 * \param[in] level The mip level that was written
358 * \param[in] start_layer The first array slice or 3D layer written
360 * \param[in] num_layers The number of array slices or 3D layers
361 * written or INTEL_REMAINING_LAYERS to indicate
362 * every layer above start_layer was written
364 * \param[in] written_with_aux Whether or not the write was done with
365 * auxiliary compression enabled
368 iris_resource_finish_write(struct iris_context
*ice
,
369 struct iris_resource
*res
, uint32_t level
,
370 uint32_t start_layer
, uint32_t num_layers
,
371 enum isl_aux_usage aux_usage
);
373 /** Get the auxiliary compression state of a miptree slice */
375 iris_resource_get_aux_state(const struct iris_resource
*res
,
376 uint32_t level
, uint32_t layer
);
379 * Set the auxiliary compression state of a miptree slice range
381 * This function directly sets the auxiliary compression state of a slice
382 * range of a miptree. It only modifies data structures and does not do any
383 * resolves. This should only be called by code which directly performs
384 * compression operations such as fast clears and resolves. Most code should
385 * use iris_resource_prepare_access or iris_resource_finish_write.
388 iris_resource_set_aux_state(struct iris_context
*ice
,
389 struct iris_resource
*res
, uint32_t level
,
390 uint32_t start_layer
, uint32_t num_layers
,
391 enum isl_aux_state aux_state
);
394 * Prepare a miptree for raw access
396 * This helper prepares the miptree for access that knows nothing about any
397 * sort of compression whatsoever. This is useful when mapping the surface or
398 * using it with the blitter.
401 iris_resource_access_raw(struct iris_context
*ice
,
402 struct iris_batch
*batch
,
403 struct iris_resource
*res
,
404 uint32_t level
, uint32_t layer
,
408 iris_resource_prepare_access(ice
, batch
, res
, level
, 1, layer
, num_layers
,
409 ISL_AUX_USAGE_NONE
, false);
411 iris_resource_finish_write(ice
, res
, level
, layer
, num_layers
,
416 enum isl_dim_layout
iris_get_isl_dim_layout(const struct gen_device_info
*devinfo
,
417 enum isl_tiling tiling
,
418 enum pipe_texture_target target
);
419 enum isl_surf_dim
target_to_isl_surf_dim(enum pipe_texture_target target
);
420 uint32_t iris_resource_get_tile_offsets(const struct iris_resource
*res
,
421 uint32_t level
, uint32_t z
,
422 uint32_t *tile_x
, uint32_t *tile_y
);
423 enum isl_aux_usage
iris_resource_texture_aux_usage(struct iris_context
*ice
,
424 const struct iris_resource
*res
,
425 enum isl_format view_fmt
,
426 enum gen9_astc5x5_wa_tex_type
);
427 void iris_resource_prepare_texture(struct iris_context
*ice
,
428 struct iris_batch
*batch
,
429 struct iris_resource
*res
,
430 enum isl_format view_format
,
431 uint32_t start_level
, uint32_t num_levels
,
432 uint32_t start_layer
, uint32_t num_layers
,
433 enum gen9_astc5x5_wa_tex_type
);
436 iris_resource_unfinished_aux_import(struct iris_resource
*res
)
438 return res
->base
.next
!= NULL
&& res
->mod_info
&&
439 res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
442 void iris_resource_finish_aux_import(struct pipe_screen
*pscreen
,
443 struct iris_resource
*res
);
445 bool iris_has_color_unresolved(const struct iris_resource
*res
,
446 unsigned start_level
, unsigned num_levels
,
447 unsigned start_layer
, unsigned num_layers
);
449 void iris_resource_check_level_layer(const struct iris_resource
*res
,
450 uint32_t level
, uint32_t layer
);
452 bool iris_resource_level_has_hiz(const struct iris_resource
*res
,
454 bool iris_has_color_unresolved(const struct iris_resource
*res
,
455 unsigned start_level
, unsigned num_levels
,
456 unsigned start_layer
, unsigned num_layers
);
458 enum isl_aux_usage
iris_resource_render_aux_usage(struct iris_context
*ice
,
459 struct iris_resource
*res
,
460 enum isl_format render_fmt
,
462 bool draw_aux_disabled
);
463 void iris_resource_prepare_render(struct iris_context
*ice
,
464 struct iris_batch
*batch
,
465 struct iris_resource
*res
, uint32_t level
,
466 uint32_t start_layer
, uint32_t layer_count
,
467 enum isl_aux_usage aux_usage
);
468 void iris_resource_finish_render(struct iris_context
*ice
,
469 struct iris_resource
*res
, uint32_t level
,
470 uint32_t start_layer
, uint32_t layer_count
,
471 enum isl_aux_usage aux_usage
);
472 void iris_resource_prepare_depth(struct iris_context
*ice
,
473 struct iris_batch
*batch
,
474 struct iris_resource
*res
, uint32_t level
,
475 uint32_t start_layer
, uint32_t layer_count
);
476 void iris_resource_finish_depth(struct iris_context
*ice
,
477 struct iris_resource
*res
, uint32_t level
,
478 uint32_t start_layer
, uint32_t layer_count
,