src/gallium/drivers/iris/iris_resource.h

   1 /*
   2  * Copyright 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #ifndef IRIS_RESOURCE_H
  24 #define IRIS_RESOURCE_H
  25
  26 #include "pipe/p_state.h"
  27 #include "util/u_inlines.h"
  28 #include "util/u_range.h"
  29 #include "intel/isl/isl.h"
  30 #include "iris_bufmgr.h"
  31
  32 struct iris_batch;
  33 struct iris_context;
  34
  35 #define IRIS_MAX_MIPLEVELS 15
  36
  37 struct iris_format_info {
  38    enum isl_format fmt;
  39    struct isl_swizzle swizzle;
  40 };
  41
  42 #define IRIS_RESOURCE_FLAG_SHADER_MEMZONE  (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  43 #define IRIS_RESOURCE_FLAG_SURFACE_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  44 #define IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  45
  46 /**
  47  * Resources represent a GPU buffer object or image (mipmap tree).
  48  *
  49  * They contain the storage (BO) and layout information (ISL surface).
  50  */
  51 struct iris_resource {
  52    struct pipe_resource base;
  53    enum pipe_format internal_format;
  54
  55    /**
  56     * The ISL surface layout information for this resource.
  57     *
  58     * This is not filled out for PIPE_BUFFER resources, but is guaranteed
  59     * to be zeroed.  Note that this also guarantees that res->surf.tiling
  60     * will be ISL_TILING_LINEAR, so it's safe to check that.
  61     */
  62    struct isl_surf surf;
  63
  64    /** Backing storage for the resource */
  65    struct iris_bo *bo;
  66
  67    /** offset at which data starts in the BO */
  68    uint64_t offset;
  69
  70    /**
  71     * A bitfield of PIPE_BIND_* indicating how this resource was bound
  72     * in the past.  Only meaningful for PIPE_BUFFER; used for flushing.
  73     */
  74    unsigned bind_history;
  75
  76    /**
  77     * A bitfield of MESA_SHADER_* stages indicating where this resource
  78     * was bound.
  79     */
  80    unsigned bind_stages;
  81
  82    /**
  83     * For PIPE_BUFFER resources, a range which may contain valid data.
  84     *
  85     * This is a conservative estimate of what part of the buffer contains
  86     * valid data that we have to preserve.  The rest of the buffer is
  87     * considered invalid, and we can promote writes to that region to
  88     * be unsynchronized writes, avoiding blit copies.
  89     */
  90    struct util_range valid_buffer_range;
  91
  92    /**
  93     * Auxiliary buffer information (CCS, MCS, or HiZ).
  94     */
  95    struct {
  96       /** The surface layout for the auxiliary buffer. */
  97       struct isl_surf surf;
  98
  99       /** The buffer object containing the auxiliary data. */
 100       struct iris_bo *bo;
 101
 102       /** Offset into 'bo' where the auxiliary surface starts. */
 103       uint32_t offset;
 104
 105       struct {
 106          struct isl_surf surf;
 107
 108          /** Offset into 'bo' where the auxiliary surface starts. */
 109          uint32_t offset;
 110       } extra_aux;
 111
 112       /**
 113        * Fast clear color for this surface.  For depth surfaces, the clear
 114        * value is stored as a float32 in the red component.
 115        */
 116       union isl_color_value clear_color;
 117
 118       /** Buffer object containing the indirect clear color.  */
 119       struct iris_bo *clear_color_bo;
 120
 121       /** Offset into bo where the clear color can be found.  */
 122       uint64_t clear_color_offset;
 123
 124       /**
 125        * \brief The type of auxiliary compression used by this resource.
 126        *
 127        * This describes the type of auxiliary compression that is intended to
 128        * be used by this resource.  An aux usage of ISL_AUX_USAGE_NONE means
 129        * that auxiliary compression is permanently disabled.  An aux usage
 130        * other than ISL_AUX_USAGE_NONE does not imply that auxiliary
 131        * compression will always be enabled for this surface.
 132        */
 133       enum isl_aux_usage usage;
 134
 135       /**
 136        * A bitfield of ISL_AUX_* modes that might this resource might use.
 137        *
 138        * For example, a surface might use both CCS_E and CCS_D at times.
 139        */
 140       unsigned possible_usages;
 141
 142       /**
 143        * Same as possible_usages, but only with modes supported for sampling.
 144        */
 145       unsigned sampler_usages;
 146
 147       /**
 148        * \brief Maps miptree slices to their current aux state.
 149        *
 150        * This two-dimensional array is indexed as [level][layer] and stores an
 151        * aux state for each slice.
 152        */
 153       enum isl_aux_state **state;
 154
 155       /**
 156        * If (1 << level) is set, HiZ is enabled for that miplevel.
 157        */
 158       uint16_t has_hiz;
 159    } aux;
 160
 161    /**
 162     * For external surfaces, this is format that was used to create or import
 163     * the surface. For internal surfaces, this will always be
 164     * PIPE_FORMAT_NONE.
 165     */
 166    enum pipe_format external_format;
 167
 168    /**
 169     * For external surfaces, this is DRM format modifier that was used to
 170     * create or import the surface.  For internal surfaces, this will always
 171     * be DRM_FORMAT_MOD_INVALID.
 172     */
 173    const struct isl_drm_modifier_info *mod_info;
 174 };
 175
 176 /**
 177  * A simple <resource, offset> tuple for storing a reference to a
 178  * piece of state stored in a GPU buffer object.
 179  */
 180 struct iris_state_ref {
 181    struct pipe_resource *res;
 182    uint32_t offset;
 183 };
 184
 185 /**
 186  * The SURFACE_STATE descriptors for a resource.
 187  */
 188 struct iris_surface_state {
 189    /**
 190     * CPU-side copy of the packed SURFACE_STATE structures, already
 191     * aligned so they can be uploaded as a contiguous pile of bytes.
 192     *
 193     * This can be updated and re-uploaded if (e.g.) addresses need to change.
 194     */
 195    uint32_t *cpu;
 196
 197    /**
 198     * How many states are there?  (Each aux mode has its own state.)
 199     */
 200    unsigned num_states;
 201
 202    /**
 203     * Address of the resource (res->bo->gtt_offset).  Note that "Surface
 204     * Base Address" may be offset from this value.
 205     */
 206    uint64_t bo_address;
 207
 208    /** A reference to the GPU buffer holding our uploaded SURFACE_STATE */
 209    struct iris_state_ref ref;
 210 };
 211
 212 /**
 213  * Gallium CSO for sampler views (texture views).
 214  *
 215  * In addition to the normal pipe_resource, this adds an ISL view
 216  * which may reinterpret the format or restrict levels/layers.
 217  *
 218  * These can also be linear texture buffers.
 219  */
 220 struct iris_sampler_view {
 221    struct pipe_sampler_view base;
 222    struct isl_view view;
 223
 224    union isl_color_value clear_color;
 225
 226    /* A short-cut (not a reference) to the actual resource being viewed.
 227     * Multi-planar (or depth+stencil) images may have multiple resources
 228     * chained together; this skips having to traverse base->texture->*.
 229     */
 230    struct iris_resource *res;
 231
 232    /** The resource (BO) holding our SURFACE_STATE. */
 233    struct iris_surface_state surface_state;
 234 };
 235
 236 /**
 237  * Image view representation.
 238  */
 239 struct iris_image_view {
 240    struct pipe_image_view base;
 241
 242    /** The resource (BO) holding our SURFACE_STATE. */
 243    struct iris_surface_state surface_state;
 244 };
 245
 246 /**
 247  * Gallium CSO for surfaces (framebuffer attachments).
 248  *
 249  * A view of a surface that can be bound to a color render target or
 250  * depth/stencil attachment.
 251  */
 252 struct iris_surface {
 253    struct pipe_surface base;
 254    struct isl_view view;
 255    struct isl_view read_view;
 256    union isl_color_value clear_color;
 257
 258    /** The resource (BO) holding our SURFACE_STATE. */
 259    struct iris_surface_state surface_state;
 260    /** The resource (BO) holding our SURFACE_STATE for read. */
 261    struct iris_surface_state surface_state_read;
 262 };
 263
 264 /**
 265  * Transfer object - information about a buffer mapping.
 266  */
 267 struct iris_transfer {
 268    struct pipe_transfer base;
 269    struct pipe_debug_callback *dbg;
 270    void *buffer;
 271    void *ptr;
 272
 273    /** A linear staging resource for GPU-based copy_region transfers. */
 274    struct pipe_resource *staging;
 275    struct blorp_context *blorp;
 276    struct iris_batch *batch;
 277
 278    bool dest_had_defined_contents;
 279
 280    void (*unmap)(struct iris_transfer *);
 281 };
 282
 283 /**
 284  * Unwrap a pipe_resource to get the underlying iris_bo (for convenience).
 285  */
 286 static inline struct iris_bo *
 287 iris_resource_bo(struct pipe_resource *p_res)
 288 {
 289    struct iris_resource *res = (void *) p_res;
 290    return res->bo;
 291 }
 292
 293 static inline uint32_t
 294 iris_mocs(const struct iris_bo *bo, const struct isl_device *dev)
 295 {
 296    return bo && bo->external ? dev->mocs.external : dev->mocs.internal;
 297 }
 298
 299 struct iris_format_info iris_format_for_usage(const struct gen_device_info *,
 300                                               enum pipe_format pf,
 301                                               isl_surf_usage_flags_t usage);
 302
 303 struct pipe_resource *iris_resource_get_separate_stencil(struct pipe_resource *);
 304
 305 void iris_get_depth_stencil_resources(struct pipe_resource *res,
 306                                       struct iris_resource **out_z,
 307                                       struct iris_resource **out_s);
 308 bool iris_resource_set_clear_color(struct iris_context *ice,
 309                                    struct iris_resource *res,
 310                                    union isl_color_value color);
 311 union isl_color_value
 312 iris_resource_get_clear_color(const struct iris_resource *res,
 313                               struct iris_bo **clear_color_bo,
 314                               uint64_t *clear_color_offset);
 315
 316 void iris_init_screen_resource_functions(struct pipe_screen *pscreen);
 317
 318 void iris_dirty_for_history(struct iris_context *ice,
 319                             struct iris_resource *res);
 320 uint32_t iris_flush_bits_for_history(struct iris_resource *res);
 321
 322 void iris_flush_and_dirty_for_history(struct iris_context *ice,
 323                                       struct iris_batch *batch,
 324                                       struct iris_resource *res,
 325                                       uint32_t extra_flags,
 326                                       const char *reason);
 327
 328 unsigned iris_get_num_logical_layers(const struct iris_resource *res,
 329                                      unsigned level);
 330
 331 void iris_resource_disable_aux(struct iris_resource *res);
 332
 333 #define INTEL_REMAINING_LAYERS UINT32_MAX
 334 #define INTEL_REMAINING_LEVELS UINT32_MAX
 335
 336 void
 337 iris_hiz_exec(struct iris_context *ice,
 338               struct iris_batch *batch,
 339               struct iris_resource *res,
 340               unsigned int level, unsigned int start_layer,
 341               unsigned int num_layers, enum isl_aux_op op,
 342               bool update_clear_depth);
 343
 344 /**
 345  * Prepare a miptree for access
 346  *
 347  * This function should be called prior to any access to miptree in order to
 348  * perform any needed resolves.
 349  *
 350  * \param[in]  start_level    The first mip level to be accessed
 351  *
 352  * \param[in]  num_levels     The number of miplevels to be accessed or
 353  *                            INTEL_REMAINING_LEVELS to indicate every level
 354  *                            above start_level will be accessed
 355  *
 356  * \param[in]  start_layer    The first array slice or 3D layer to be accessed
 357  *
 358  * \param[in]  num_layers     The number of array slices or 3D layers be
 359  *                            accessed or INTEL_REMAINING_LAYERS to indicate
 360  *                            every layer above start_layer will be accessed
 361  *
 362  * \param[in]  aux_supported  Whether or not the access will support the
 363  *                            miptree's auxiliary compression format;  this
 364  *                            must be false for uncompressed miptrees
 365  *
 366  * \param[in]  fast_clear_supported Whether or not the access will support
 367  *                                  fast clears in the miptree's auxiliary
 368  *                                  compression format
 369  */
 370 void
 371 iris_resource_prepare_access(struct iris_context *ice,
 372                              struct iris_batch *batch,
 373                              struct iris_resource *res,
 374                              uint32_t start_level, uint32_t num_levels,
 375                              uint32_t start_layer, uint32_t num_layers,
 376                              enum isl_aux_usage aux_usage,
 377                              bool fast_clear_supported);
 378
 379 /**
 380  * Complete a write operation
 381  *
 382  * This function should be called after any operation writes to a miptree.
 383  * This will update the miptree's compression state so that future resolves
 384  * happen correctly.  Technically, this function can be called before the
 385  * write occurs but the caller must ensure that they don't interlace
 386  * iris_resource_prepare_access and iris_resource_finish_write calls to
 387  * overlapping layer/level ranges.
 388  *
 389  * \param[in]  level             The mip level that was written
 390  *
 391  * \param[in]  start_layer       The first array slice or 3D layer written
 392  *
 393  * \param[in]  num_layers        The number of array slices or 3D layers
 394  *                               written or INTEL_REMAINING_LAYERS to indicate
 395  *                               every layer above start_layer was written
 396  *
 397  * \param[in]  written_with_aux  Whether or not the write was done with
 398  *                               auxiliary compression enabled
 399  */
 400 void
 401 iris_resource_finish_write(struct iris_context *ice,
 402                            struct iris_resource *res, uint32_t level,
 403                            uint32_t start_layer, uint32_t num_layers,
 404                            enum isl_aux_usage aux_usage);
 405
 406 /** Get the auxiliary compression state of a miptree slice */
 407 enum isl_aux_state
 408 iris_resource_get_aux_state(const struct iris_resource *res,
 409                             uint32_t level, uint32_t layer);
 410
 411 /**
 412  * Set the auxiliary compression state of a miptree slice range
 413  *
 414  * This function directly sets the auxiliary compression state of a slice
 415  * range of a miptree.  It only modifies data structures and does not do any
 416  * resolves.  This should only be called by code which directly performs
 417  * compression operations such as fast clears and resolves.  Most code should
 418  * use iris_resource_prepare_access or iris_resource_finish_write.
 419  */
 420 void
 421 iris_resource_set_aux_state(struct iris_context *ice,
 422                             struct iris_resource *res, uint32_t level,
 423                             uint32_t start_layer, uint32_t num_layers,
 424                             enum isl_aux_state aux_state);
 425
 426 /**
 427  * Prepare a miptree for raw access
 428  *
 429  * This helper prepares the miptree for access that knows nothing about any
 430  * sort of compression whatsoever.  This is useful when mapping the surface or
 431  * using it with the blitter.
 432  */
 433 static inline void
 434 iris_resource_access_raw(struct iris_context *ice,
 435                          struct iris_batch *batch,
 436                          struct iris_resource *res,
 437                          uint32_t level, uint32_t layer,
 438                          uint32_t num_layers,
 439                          bool write)
 440 {
 441    iris_resource_prepare_access(ice, batch, res, level, 1, layer, num_layers,
 442                                 ISL_AUX_USAGE_NONE, false);
 443    if (write) {
 444       iris_resource_finish_write(ice, res, level, layer, num_layers,
 445                                  ISL_AUX_USAGE_NONE);
 446    }
 447 }
 448
 449 enum isl_dim_layout iris_get_isl_dim_layout(const struct gen_device_info *devinfo,
 450                                             enum isl_tiling tiling,
 451                                             enum pipe_texture_target target);
 452 enum isl_surf_dim target_to_isl_surf_dim(enum pipe_texture_target target);
 453 uint32_t iris_resource_get_tile_offsets(const struct iris_resource *res,
 454                                         uint32_t level, uint32_t z,
 455                                         uint32_t *tile_x, uint32_t *tile_y);
 456 enum isl_aux_usage iris_resource_texture_aux_usage(struct iris_context *ice,
 457                                                    const struct iris_resource *res,
 458                                                    enum isl_format view_fmt);
 459 void iris_resource_prepare_texture(struct iris_context *ice,
 460                                    struct iris_batch *batch,
 461                                    struct iris_resource *res,
 462                                    enum isl_format view_format,
 463                                    uint32_t start_level, uint32_t num_levels,
 464                                    uint32_t start_layer, uint32_t num_layers);
 465
 466 static inline bool
 467 iris_resource_unfinished_aux_import(struct iris_resource *res)
 468 {
 469    return res->base.next != NULL && res->mod_info &&
 470       res->mod_info->aux_usage != ISL_AUX_USAGE_NONE;
 471 }
 472
 473 void iris_resource_finish_aux_import(struct pipe_screen *pscreen,
 474                                      struct iris_resource *res);
 475
 476 bool iris_has_color_unresolved(const struct iris_resource *res,
 477                                unsigned start_level, unsigned num_levels,
 478                                unsigned start_layer, unsigned num_layers);
 479
 480 void iris_resource_check_level_layer(const struct iris_resource *res,
 481                                      uint32_t level, uint32_t layer);
 482
 483 bool iris_resource_level_has_hiz(const struct iris_resource *res,
 484                                  uint32_t level);
 485
 486 bool iris_sample_with_depth_aux(const struct gen_device_info *devinfo,
 487                                 const struct iris_resource *res);
 488
 489 bool iris_has_color_unresolved(const struct iris_resource *res,
 490                                unsigned start_level, unsigned num_levels,
 491                                unsigned start_layer, unsigned num_layers);
 492
 493 enum isl_aux_usage iris_resource_render_aux_usage(struct iris_context *ice,
 494                                                   struct iris_resource *res,
 495                                                   enum isl_format render_fmt,
 496                                                   bool blend_enabled,
 497                                                   bool draw_aux_disabled);
 498 void iris_resource_prepare_render(struct iris_context *ice,
 499                                   struct iris_batch *batch,
 500                                   struct iris_resource *res, uint32_t level,
 501                                   uint32_t start_layer, uint32_t layer_count,
 502                                   enum isl_aux_usage aux_usage);
 503 void iris_resource_finish_render(struct iris_context *ice,
 504                                  struct iris_resource *res, uint32_t level,
 505                                  uint32_t start_layer, uint32_t layer_count,
 506                                  enum isl_aux_usage aux_usage);
 507 void iris_resource_prepare_depth(struct iris_context *ice,
 508                                  struct iris_batch *batch,
 509                                  struct iris_resource *res, uint32_t level,
 510                                  uint32_t start_layer, uint32_t layer_count);
 511 void iris_resource_finish_depth(struct iris_context *ice,
 512                                 struct iris_resource *res, uint32_t level,
 513                                 uint32_t start_layer, uint32_t layer_count,
 514                                 bool depth_written);
 515 #endif