src/gallium/drivers/iris/iris_resource.h

   1 /*
   2  * Copyright 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #ifndef IRIS_RESOURCE_H
  24 #define IRIS_RESOURCE_H
  25
  26 #include "pipe/p_state.h"
  27 #include "util/u_inlines.h"
  28 #include "intel/isl/isl.h"
  29
  30 struct iris_batch;
  31 struct iris_context;
  32
  33 #define IRIS_MAX_MIPLEVELS 15
  34
  35 struct iris_format_info {
  36    enum isl_format fmt;
  37    struct isl_swizzle swizzle;
  38 };
  39
  40 #define IRIS_RESOURCE_FLAG_SHADER_MEMZONE  (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  41 #define IRIS_RESOURCE_FLAG_SURFACE_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  42 #define IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  43
  44 /**
  45  * Resources represent a GPU buffer object or image (mipmap tree).
  46  *
  47  * They contain the storage (BO) and layout information (ISL surface).
  48  */
  49 struct iris_resource {
  50    struct pipe_resource base;
  51    enum pipe_format internal_format;
  52
  53    /**
  54     * The ISL surface layout information for this resource.
  55     *
  56     * This is not filled out for PIPE_BUFFER resources, but is guaranteed
  57     * to be zeroed.  Note that this also guarantees that res->surf.tiling
  58     * will be ISL_TILING_LINEAR, so it's safe to check that.
  59     */
  60    struct isl_surf surf;
  61
  62    /** Backing storage for the resource */
  63    struct iris_bo *bo;
  64
  65    /**
  66     * A bitfield of PIPE_BIND_* indicating how this resource was bound
  67     * in the past.  Only meaningful for PIPE_BUFFER; used for flushing.
  68     */
  69    unsigned bind_history;
  70 };
  71
  72 /**
  73  * A simple <resource, offset> tuple for storing a reference to a
  74  * piece of state stored in a GPU buffer object.
  75  */
  76 struct iris_state_ref {
  77    struct pipe_resource *res;
  78    uint32_t offset;
  79 };
  80
  81 /**
  82  * Gallium CSO for sampler views (texture views).
  83  *
  84  * In addition to the normal pipe_resource, this adds an ISL view
  85  * which may reinterpret the format or restrict levels/layers.
  86  *
  87  * These can also be linear texture buffers.
  88  */
  89 struct iris_sampler_view {
  90    struct pipe_sampler_view base;
  91    struct isl_view view;
  92
  93    /* A short-cut (not a reference) to the actual resource being viewed.
  94     * Multi-planar (or depth+stencil) images may have multiple resources
  95     * chained together; this skips having to traverse base->texture->*.
  96     */
  97    struct iris_resource *res;
  98
  99    /** The resource (BO) holding our SURFACE_STATE. */
 100    struct iris_state_ref surface_state;
 101 };
 102
 103 /**
 104  * Gallium CSO for surfaces (framebuffer attachments).
 105  *
 106  * A view of a surface that can be bound to a color render target or
 107  * depth/stencil attachment.
 108  */
 109 struct iris_surface {
 110    struct pipe_surface base;
 111    struct isl_view view;
 112
 113    /** The resource (BO) holding our SURFACE_STATE. */
 114    struct iris_state_ref surface_state;
 115 };
 116
 117 /**
 118  * Transfer object - information about a buffer mapping.
 119  */
 120 struct iris_transfer {
 121    struct pipe_transfer base;
 122    struct pipe_debug_callback *dbg;
 123    void *buffer;
 124    void *ptr;
 125
 126    void (*unmap)(struct iris_transfer *);
 127 };
 128
 129 /**
 130  * Unwrap a pipe_resource to get the underlying iris_bo (for convenience).
 131  */
 132 static inline struct iris_bo *
 133 iris_resource_bo(struct pipe_resource *p_res)
 134 {
 135    struct iris_resource *res = (void *) p_res;
 136    return res->bo;
 137 }
 138
 139 struct iris_format_info iris_format_for_usage(const struct gen_device_info *,
 140                                               enum pipe_format pf,
 141                                               isl_surf_usage_flags_t usage);
 142
 143 struct pipe_resource *iris_resource_get_separate_stencil(struct pipe_resource *);
 144
 145 void iris_get_depth_stencil_resources(struct pipe_resource *res,
 146                                       struct iris_resource **out_z,
 147                                       struct iris_resource **out_s);
 148
 149 void iris_init_screen_resource_functions(struct pipe_screen *pscreen);
 150
 151 void iris_flush_and_dirty_for_history(struct iris_context *ice,
 152                                       struct iris_batch *batch,
 153                                       struct iris_resource *res);
 154
 155 #endif