src/gallium/drivers/iris/iris_resource.h

   1 /*
   2  * Copyright 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #ifndef IRIS_RESOURCE_H
  24 #define IRIS_RESOURCE_H
  25
  26 #include "pipe/p_state.h"
  27 #include "util/u_inlines.h"
  28 #include "intel/isl/isl.h"
  29
  30 struct iris_batch;
  31 struct iris_context;
  32
  33 #define IRIS_MAX_MIPLEVELS 15
  34
  35 struct iris_format_info {
  36    enum isl_format fmt;
  37    struct isl_swizzle swizzle;
  38 };
  39
  40 #define IRIS_RESOURCE_FLAG_SHADER_MEMZONE  (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  41 #define IRIS_RESOURCE_FLAG_SURFACE_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  42 #define IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  43
  44 enum gen9_astc5x5_wa_tex_type {
  45    GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5 = 1 << 0,
  46    GEN9_ASTC5X5_WA_TEX_TYPE_AUX     = 1 << 1,
  47 };
  48
  49 /**
  50  * Resources represent a GPU buffer object or image (mipmap tree).
  51  *
  52  * They contain the storage (BO) and layout information (ISL surface).
  53  */
  54 struct iris_resource {
  55    struct pipe_resource base;
  56    enum pipe_format internal_format;
  57
  58    /**
  59     * The ISL surface layout information for this resource.
  60     *
  61     * This is not filled out for PIPE_BUFFER resources, but is guaranteed
  62     * to be zeroed.  Note that this also guarantees that res->surf.tiling
  63     * will be ISL_TILING_LINEAR, so it's safe to check that.
  64     */
  65    struct isl_surf surf;
  66
  67    /** Backing storage for the resource */
  68    struct iris_bo *bo;
  69
  70    /**
  71     * A bitfield of PIPE_BIND_* indicating how this resource was bound
  72     * in the past.  Only meaningful for PIPE_BUFFER; used for flushing.
  73     */
  74    unsigned bind_history;
  75
  76    /**
  77     * Auxiliary buffer information (CCS, MCS, or HiZ).
  78     */
  79    struct {
  80       /** The surface layout for the auxiliary buffer. */
  81       struct isl_surf surf;
  82
  83       /** The buffer object containing the auxiliary data. */
  84       struct iris_bo *bo;
  85
  86       /** Offset into 'bo' where the auxiliary surface starts. */
  87       uint32_t offset;
  88
  89       /**
  90        * \brief The type of auxiliary compression used by this resource.
  91        *
  92        * This describes the type of auxiliary compression that is intended to
  93        * be used by this resource.  An aux usage of ISL_AUX_USAGE_NONE means
  94        * that auxiliary compression is permanently disabled.  An aux usage
  95        * other than ISL_AUX_USAGE_NONE does not imply that auxiliary
  96        * compression will always be enabled for this surface.
  97        */
  98       enum isl_aux_usage usage;
  99
 100       /**
 101        * A bitfield of ISL_AUX_* modes that might this resource might use.
 102        *
 103        * For example, a surface might use both CCS_E and CCS_D at times.
 104        */
 105       unsigned possible_usages;
 106
 107       /**
 108        * \brief Maps miptree slices to their current aux state.
 109        *
 110        * This two-dimensional array is indexed as [level][layer] and stores an
 111        * aux state for each slice.
 112        */
 113       enum isl_aux_state **state;
 114    } aux;
 115 };
 116
 117 /**
 118  * A simple <resource, offset> tuple for storing a reference to a
 119  * piece of state stored in a GPU buffer object.
 120  */
 121 struct iris_state_ref {
 122    struct pipe_resource *res;
 123    uint32_t offset;
 124 };
 125
 126 /**
 127  * Gallium CSO for sampler views (texture views).
 128  *
 129  * In addition to the normal pipe_resource, this adds an ISL view
 130  * which may reinterpret the format or restrict levels/layers.
 131  *
 132  * These can also be linear texture buffers.
 133  */
 134 struct iris_sampler_view {
 135    struct pipe_sampler_view base;
 136    struct isl_view view;
 137
 138    /* A short-cut (not a reference) to the actual resource being viewed.
 139     * Multi-planar (or depth+stencil) images may have multiple resources
 140     * chained together; this skips having to traverse base->texture->*.
 141     */
 142    struct iris_resource *res;
 143
 144    /** The resource (BO) holding our SURFACE_STATE. */
 145    struct iris_state_ref surface_state;
 146 };
 147
 148 /**
 149  * Gallium CSO for surfaces (framebuffer attachments).
 150  *
 151  * A view of a surface that can be bound to a color render target or
 152  * depth/stencil attachment.
 153  */
 154 struct iris_surface {
 155    struct pipe_surface base;
 156    struct isl_view view;
 157
 158    /** The resource (BO) holding our SURFACE_STATE. */
 159    struct iris_state_ref surface_state;
 160 };
 161
 162 /**
 163  * Transfer object - information about a buffer mapping.
 164  */
 165 struct iris_transfer {
 166    struct pipe_transfer base;
 167    struct pipe_debug_callback *dbg;
 168    void *buffer;
 169    void *ptr;
 170
 171    void (*unmap)(struct iris_transfer *);
 172 };
 173
 174 /**
 175  * Unwrap a pipe_resource to get the underlying iris_bo (for convenience).
 176  */
 177 static inline struct iris_bo *
 178 iris_resource_bo(struct pipe_resource *p_res)
 179 {
 180    struct iris_resource *res = (void *) p_res;
 181    return res->bo;
 182 }
 183
 184 struct iris_format_info iris_format_for_usage(const struct gen_device_info *,
 185                                               enum pipe_format pf,
 186                                               isl_surf_usage_flags_t usage);
 187
 188 struct pipe_resource *iris_resource_get_separate_stencil(struct pipe_resource *);
 189
 190 void iris_get_depth_stencil_resources(struct pipe_resource *res,
 191                                       struct iris_resource **out_z,
 192                                       struct iris_resource **out_s);
 193
 194 void iris_init_screen_resource_functions(struct pipe_screen *pscreen);
 195
 196 void iris_flush_and_dirty_for_history(struct iris_context *ice,
 197                                       struct iris_batch *batch,
 198                                       struct iris_resource *res);
 199
 200 unsigned iris_get_num_logical_layers(const struct iris_resource *res,
 201                                      unsigned level);
 202
 203 void iris_resource_disable_aux(struct iris_resource *res);
 204
 205 #define INTEL_REMAINING_LAYERS UINT32_MAX
 206 #define INTEL_REMAINING_LEVELS UINT32_MAX
 207
 208 /**
 209  * Prepare a miptree for access
 210  *
 211  * This function should be called prior to any access to miptree in order to
 212  * perform any needed resolves.
 213  *
 214  * \param[in]  start_level    The first mip level to be accessed
 215  *
 216  * \param[in]  num_levels     The number of miplevels to be accessed or
 217  *                            INTEL_REMAINING_LEVELS to indicate every level
 218  *                            above start_level will be accessed
 219  *
 220  * \param[in]  start_layer    The first array slice or 3D layer to be accessed
 221  *
 222  * \param[in]  num_layers     The number of array slices or 3D layers be
 223  *                            accessed or INTEL_REMAINING_LAYERS to indicate
 224  *                            every layer above start_layer will be accessed
 225  *
 226  * \param[in]  aux_supported  Whether or not the access will support the
 227  *                            miptree's auxiliary compression format;  this
 228  *                            must be false for uncompressed miptrees
 229  *
 230  * \param[in]  fast_clear_supported Whether or not the access will support
 231  *                                  fast clears in the miptree's auxiliary
 232  *                                  compression format
 233  */
 234 void
 235 iris_resource_prepare_access(struct iris_context *ice,
 236                              struct iris_batch *batch,
 237                              struct iris_resource *res,
 238                              uint32_t start_level, uint32_t num_levels,
 239                              uint32_t start_layer, uint32_t num_layers,
 240                              enum isl_aux_usage aux_usage,
 241                              bool fast_clear_supported);
 242
 243 /**
 244  * Complete a write operation
 245  *
 246  * This function should be called after any operation writes to a miptree.
 247  * This will update the miptree's compression state so that future resolves
 248  * happen correctly.  Technically, this function can be called before the
 249  * write occurs but the caller must ensure that they don't interlace
 250  * iris_resource_prepare_access and iris_resource_finish_write calls to
 251  * overlapping layer/level ranges.
 252  *
 253  * \param[in]  level             The mip level that was written
 254  *
 255  * \param[in]  start_layer       The first array slice or 3D layer written
 256  *
 257  * \param[in]  num_layers        The number of array slices or 3D layers
 258  *                               written or INTEL_REMAINING_LAYERS to indicate
 259  *                               every layer above start_layer was written
 260  *
 261  * \param[in]  written_with_aux  Whether or not the write was done with
 262  *                               auxiliary compression enabled
 263  */
 264 void
 265 iris_resource_finish_write(struct iris_context *ice,
 266                            struct iris_resource *res, uint32_t level,
 267                            uint32_t start_layer, uint32_t num_layers,
 268                            enum isl_aux_usage aux_usage);
 269
 270 /** Get the auxiliary compression state of a miptree slice */
 271 enum isl_aux_state
 272 iris_resource_get_aux_state(const struct iris_resource *res,
 273                             uint32_t level, uint32_t layer);
 274
 275 /**
 276  * Set the auxiliary compression state of a miptree slice range
 277  *
 278  * This function directly sets the auxiliary compression state of a slice
 279  * range of a miptree.  It only modifies data structures and does not do any
 280  * resolves.  This should only be called by code which directly performs
 281  * compression operations such as fast clears and resolves.  Most code should
 282  * use iris_resource_prepare_access or iris_resource_finish_write.
 283  */
 284 void
 285 iris_resource_set_aux_state(struct iris_resource *res, uint32_t level,
 286                             uint32_t start_layer, uint32_t num_layers,
 287                             enum isl_aux_state aux_state);
 288
 289 /**
 290  * Prepare a miptree for raw access
 291  *
 292  * This helper prepares the miptree for access that knows nothing about any
 293  * sort of compression whatsoever.  This is useful when mapping the surface or
 294  * using it with the blitter.
 295  */
 296 static inline void
 297 iris_resource_access_raw(struct iris_context *ice,
 298                          struct iris_batch *batch,
 299                          struct iris_resource *res,
 300                          uint32_t level, uint32_t layer,
 301                          bool write)
 302 {
 303    iris_resource_prepare_access(ice, batch, res, level, 1, layer, 1,
 304                                 ISL_AUX_USAGE_NONE, false);
 305    if (write)
 306       iris_resource_finish_write(ice, res, level, layer, 1, ISL_AUX_USAGE_NONE);
 307 }
 308
 309 enum isl_aux_usage iris_resource_texture_aux_usage(struct iris_context *ice,
 310                                                    const struct iris_resource *res,
 311                                                    enum isl_format view_fmt,
 312                                                    enum gen9_astc5x5_wa_tex_type);
 313 void iris_resource_prepare_texture(struct iris_context *ice,
 314                                    struct iris_batch *batch,
 315                                    struct iris_resource *res,
 316                                    enum isl_format view_format,
 317                                    uint32_t start_level, uint32_t num_levels,
 318                                    uint32_t start_layer, uint32_t num_layers,
 319                                    enum gen9_astc5x5_wa_tex_type);
 320 void iris_resource_prepare_image(struct iris_context *ice,
 321                                  struct iris_batch *batch,
 322                                  struct iris_resource *res);
 323
 324 void iris_resource_check_level_layer(const struct iris_resource *res,
 325                                      uint32_t level, uint32_t layer);
 326
 327 bool iris_resource_level_has_hiz(const struct iris_resource *res,
 328                                  uint32_t level);
 329
 330 enum isl_aux_usage iris_resource_render_aux_usage(struct iris_context *ice,
 331                                                   struct iris_resource *res,
 332                                                   enum isl_format render_fmt,
 333                                                   bool blend_enabled,
 334                                                   bool draw_aux_disabled);
 335 void iris_resource_prepare_render(struct iris_context *ice,
 336                                   struct iris_batch *batch,
 337                                   struct iris_resource *res, uint32_t level,
 338                                   uint32_t start_layer, uint32_t layer_count,
 339                                   enum isl_aux_usage aux_usage);
 340 void iris_resource_finish_render(struct iris_context *ice,
 341                                  struct iris_resource *res, uint32_t level,
 342                                  uint32_t start_layer, uint32_t layer_count,
 343                                  enum isl_aux_usage aux_usage);
 344 void iris_resource_prepare_depth(struct iris_context *ice,
 345                                  struct iris_batch *batch,
 346                                  struct iris_resource *res, uint32_t level,
 347                                  uint32_t start_layer, uint32_t layer_count);
 348 void iris_resource_finish_depth(struct iris_context *ice,
 349                                 struct iris_resource *res, uint32_t level,
 350                                 uint32_t start_layer, uint32_t layer_count,
 351                                 bool depth_written);
 352 #endif