2 * Copyright 2017 Intel Corporation
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9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
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23 #ifndef IRIS_RESOURCE_H
24 #define IRIS_RESOURCE_H
26 #include "pipe/p_state.h"
27 #include "util/u_inlines.h"
28 #include "intel/isl/isl.h"
33 #define IRIS_MAX_MIPLEVELS 15
35 struct iris_format_info
{
37 struct isl_swizzle swizzle
;
40 #define IRIS_RESOURCE_FLAG_SHADER_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
41 #define IRIS_RESOURCE_FLAG_SURFACE_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
42 #define IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
44 enum gen9_astc5x5_wa_tex_type
{
45 GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5
= 1 << 0,
46 GEN9_ASTC5X5_WA_TEX_TYPE_AUX
= 1 << 1,
50 * Resources represent a GPU buffer object or image (mipmap tree).
52 * They contain the storage (BO) and layout information (ISL surface).
54 struct iris_resource
{
55 struct pipe_resource base
;
56 enum pipe_format internal_format
;
59 * The ISL surface layout information for this resource.
61 * This is not filled out for PIPE_BUFFER resources, but is guaranteed
62 * to be zeroed. Note that this also guarantees that res->surf.tiling
63 * will be ISL_TILING_LINEAR, so it's safe to check that.
67 /** Backing storage for the resource */
71 * A bitfield of PIPE_BIND_* indicating how this resource was bound
72 * in the past. Only meaningful for PIPE_BUFFER; used for flushing.
74 unsigned bind_history
;
77 * Auxiliary buffer information (CCS, MCS, or HiZ).
80 /** The surface layout for the auxiliary buffer. */
83 /** The buffer object containing the auxiliary data. */
86 /** Offset into 'bo' where the auxiliary surface starts. */
90 * Fast clear color for this surface. For depth surfaces, the clear
91 * value is stored as a float32 in the red component.
93 union isl_color_value clear_color
;
95 /** Buffer object containing the indirect clear color. */
96 struct iris_bo
*clear_color_bo
;
98 /** Offset into bo where the clear color can be found. */
99 uint64_t clear_color_offset
;
102 * \brief The type of auxiliary compression used by this resource.
104 * This describes the type of auxiliary compression that is intended to
105 * be used by this resource. An aux usage of ISL_AUX_USAGE_NONE means
106 * that auxiliary compression is permanently disabled. An aux usage
107 * other than ISL_AUX_USAGE_NONE does not imply that auxiliary
108 * compression will always be enabled for this surface.
110 enum isl_aux_usage usage
;
113 * A bitfield of ISL_AUX_* modes that might this resource might use.
115 * For example, a surface might use both CCS_E and CCS_D at times.
117 unsigned possible_usages
;
120 * Same as possible_usages, but only with modes supported for sampling.
122 unsigned sampler_usages
;
125 * \brief Maps miptree slices to their current aux state.
127 * This two-dimensional array is indexed as [level][layer] and stores an
128 * aux state for each slice.
130 enum isl_aux_state
**state
;
133 * If (1 << level) is set, HiZ is enabled for that miplevel.
139 * For external surfaces, this is DRM format modifier that was used to
140 * create or import the surface. For internal surfaces, this will always
141 * be DRM_FORMAT_MOD_INVALID.
143 const struct isl_drm_modifier_info
*mod_info
;
147 * A simple <resource, offset> tuple for storing a reference to a
148 * piece of state stored in a GPU buffer object.
150 struct iris_state_ref
{
151 struct pipe_resource
*res
;
156 * Gallium CSO for sampler views (texture views).
158 * In addition to the normal pipe_resource, this adds an ISL view
159 * which may reinterpret the format or restrict levels/layers.
161 * These can also be linear texture buffers.
163 struct iris_sampler_view
{
164 struct pipe_sampler_view base
;
165 struct isl_view view
;
167 union isl_color_value clear_color
;
169 /* A short-cut (not a reference) to the actual resource being viewed.
170 * Multi-planar (or depth+stencil) images may have multiple resources
171 * chained together; this skips having to traverse base->texture->*.
173 struct iris_resource
*res
;
175 /** The resource (BO) holding our SURFACE_STATE. */
176 struct iris_state_ref surface_state
;
180 * Gallium CSO for surfaces (framebuffer attachments).
182 * A view of a surface that can be bound to a color render target or
183 * depth/stencil attachment.
185 struct iris_surface
{
186 struct pipe_surface base
;
187 struct isl_view view
;
188 union isl_color_value clear_color
;
190 /** The resource (BO) holding our SURFACE_STATE. */
191 struct iris_state_ref surface_state
;
195 * Transfer object - information about a buffer mapping.
197 struct iris_transfer
{
198 struct pipe_transfer base
;
199 struct pipe_debug_callback
*dbg
;
203 /** A linear staging resource for GPU-based copy_region transfers. */
204 struct pipe_resource
*staging
;
205 struct blorp_context
*blorp
;
206 struct iris_batch
*batch
;
208 void (*unmap
)(struct iris_transfer
*);
212 * Unwrap a pipe_resource to get the underlying iris_bo (for convenience).
214 static inline struct iris_bo
*
215 iris_resource_bo(struct pipe_resource
*p_res
)
217 struct iris_resource
*res
= (void *) p_res
;
221 struct iris_format_info
iris_format_for_usage(const struct gen_device_info
*,
223 isl_surf_usage_flags_t usage
);
225 struct pipe_resource
*iris_resource_get_separate_stencil(struct pipe_resource
*);
227 void iris_get_depth_stencil_resources(struct pipe_resource
*res
,
228 struct iris_resource
**out_z
,
229 struct iris_resource
**out_s
);
230 bool iris_resource_set_clear_color(struct iris_context
*ice
,
231 struct iris_resource
*res
,
232 union isl_color_value color
);
233 union isl_color_value
234 iris_resource_get_clear_color(const struct iris_resource
*res
,
235 struct iris_bo
**clear_color_bo
,
236 uint64_t *clear_color_offset
);
238 void iris_init_screen_resource_functions(struct pipe_screen
*pscreen
);
240 void iris_flush_and_dirty_for_history(struct iris_context
*ice
,
241 struct iris_batch
*batch
,
242 struct iris_resource
*res
);
244 unsigned iris_get_num_logical_layers(const struct iris_resource
*res
,
247 void iris_resource_disable_aux(struct iris_resource
*res
);
249 #define INTEL_REMAINING_LAYERS UINT32_MAX
250 #define INTEL_REMAINING_LEVELS UINT32_MAX
253 iris_hiz_exec(struct iris_context
*ice
,
254 struct iris_batch
*batch
,
255 struct iris_resource
*res
,
256 unsigned int level
, unsigned int start_layer
,
257 unsigned int num_layers
, enum isl_aux_op op
,
258 bool update_clear_depth
);
261 * Prepare a miptree for access
263 * This function should be called prior to any access to miptree in order to
264 * perform any needed resolves.
266 * \param[in] start_level The first mip level to be accessed
268 * \param[in] num_levels The number of miplevels to be accessed or
269 * INTEL_REMAINING_LEVELS to indicate every level
270 * above start_level will be accessed
272 * \param[in] start_layer The first array slice or 3D layer to be accessed
274 * \param[in] num_layers The number of array slices or 3D layers be
275 * accessed or INTEL_REMAINING_LAYERS to indicate
276 * every layer above start_layer will be accessed
278 * \param[in] aux_supported Whether or not the access will support the
279 * miptree's auxiliary compression format; this
280 * must be false for uncompressed miptrees
282 * \param[in] fast_clear_supported Whether or not the access will support
283 * fast clears in the miptree's auxiliary
287 iris_resource_prepare_access(struct iris_context
*ice
,
288 struct iris_batch
*batch
,
289 struct iris_resource
*res
,
290 uint32_t start_level
, uint32_t num_levels
,
291 uint32_t start_layer
, uint32_t num_layers
,
292 enum isl_aux_usage aux_usage
,
293 bool fast_clear_supported
);
296 * Complete a write operation
298 * This function should be called after any operation writes to a miptree.
299 * This will update the miptree's compression state so that future resolves
300 * happen correctly. Technically, this function can be called before the
301 * write occurs but the caller must ensure that they don't interlace
302 * iris_resource_prepare_access and iris_resource_finish_write calls to
303 * overlapping layer/level ranges.
305 * \param[in] level The mip level that was written
307 * \param[in] start_layer The first array slice or 3D layer written
309 * \param[in] num_layers The number of array slices or 3D layers
310 * written or INTEL_REMAINING_LAYERS to indicate
311 * every layer above start_layer was written
313 * \param[in] written_with_aux Whether or not the write was done with
314 * auxiliary compression enabled
317 iris_resource_finish_write(struct iris_context
*ice
,
318 struct iris_resource
*res
, uint32_t level
,
319 uint32_t start_layer
, uint32_t num_layers
,
320 enum isl_aux_usage aux_usage
);
322 /** Get the auxiliary compression state of a miptree slice */
324 iris_resource_get_aux_state(const struct iris_resource
*res
,
325 uint32_t level
, uint32_t layer
);
328 * Set the auxiliary compression state of a miptree slice range
330 * This function directly sets the auxiliary compression state of a slice
331 * range of a miptree. It only modifies data structures and does not do any
332 * resolves. This should only be called by code which directly performs
333 * compression operations such as fast clears and resolves. Most code should
334 * use iris_resource_prepare_access or iris_resource_finish_write.
337 iris_resource_set_aux_state(struct iris_context
*ice
,
338 struct iris_resource
*res
, uint32_t level
,
339 uint32_t start_layer
, uint32_t num_layers
,
340 enum isl_aux_state aux_state
);
343 * Prepare a miptree for raw access
345 * This helper prepares the miptree for access that knows nothing about any
346 * sort of compression whatsoever. This is useful when mapping the surface or
347 * using it with the blitter.
350 iris_resource_access_raw(struct iris_context
*ice
,
351 struct iris_batch
*batch
,
352 struct iris_resource
*res
,
353 uint32_t level
, uint32_t layer
,
357 iris_resource_prepare_access(ice
, batch
, res
, level
, 1, layer
, num_layers
,
358 ISL_AUX_USAGE_NONE
, false);
360 iris_resource_finish_write(ice
, res
, level
, layer
, num_layers
,
365 enum isl_aux_usage
iris_resource_texture_aux_usage(struct iris_context
*ice
,
366 const struct iris_resource
*res
,
367 enum isl_format view_fmt
,
368 enum gen9_astc5x5_wa_tex_type
);
369 void iris_resource_prepare_texture(struct iris_context
*ice
,
370 struct iris_batch
*batch
,
371 struct iris_resource
*res
,
372 enum isl_format view_format
,
373 uint32_t start_level
, uint32_t num_levels
,
374 uint32_t start_layer
, uint32_t num_layers
,
375 enum gen9_astc5x5_wa_tex_type
);
376 void iris_resource_prepare_image(struct iris_context
*ice
,
377 struct iris_batch
*batch
,
378 struct iris_resource
*res
);
380 void iris_resource_check_level_layer(const struct iris_resource
*res
,
381 uint32_t level
, uint32_t layer
);
383 bool iris_resource_level_has_hiz(const struct iris_resource
*res
,
386 enum isl_aux_usage
iris_resource_render_aux_usage(struct iris_context
*ice
,
387 struct iris_resource
*res
,
388 enum isl_format render_fmt
,
390 bool draw_aux_disabled
);
391 void iris_resource_prepare_render(struct iris_context
*ice
,
392 struct iris_batch
*batch
,
393 struct iris_resource
*res
, uint32_t level
,
394 uint32_t start_layer
, uint32_t layer_count
,
395 enum isl_aux_usage aux_usage
);
396 void iris_resource_finish_render(struct iris_context
*ice
,
397 struct iris_resource
*res
, uint32_t level
,
398 uint32_t start_layer
, uint32_t layer_count
,
399 enum isl_aux_usage aux_usage
);
400 void iris_resource_prepare_depth(struct iris_context
*ice
,
401 struct iris_batch
*batch
,
402 struct iris_resource
*res
, uint32_t level
,
403 uint32_t start_layer
, uint32_t layer_count
);
404 void iris_resource_finish_depth(struct iris_context
*ice
,
405 struct iris_resource
*res
, uint32_t level
,
406 uint32_t start_layer
, uint32_t layer_count
,