2 * Copyright 2017 Intel Corporation
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9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
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23 #ifndef IRIS_RESOURCE_H
24 #define IRIS_RESOURCE_H
26 #include "pipe/p_state.h"
27 #include "util/u_inlines.h"
28 #include "intel/isl/isl.h"
33 #define IRIS_MAX_MIPLEVELS 15
35 struct iris_format_info
{
37 struct isl_swizzle swizzle
;
40 #define IRIS_RESOURCE_FLAG_SHADER_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
41 #define IRIS_RESOURCE_FLAG_SURFACE_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
42 #define IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
44 enum gen9_astc5x5_wa_tex_type
{
45 GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5
= 1 << 0,
46 GEN9_ASTC5X5_WA_TEX_TYPE_AUX
= 1 << 1,
50 * Resources represent a GPU buffer object or image (mipmap tree).
52 * They contain the storage (BO) and layout information (ISL surface).
54 struct iris_resource
{
55 struct pipe_resource base
;
56 enum pipe_format internal_format
;
59 * The ISL surface layout information for this resource.
61 * This is not filled out for PIPE_BUFFER resources, but is guaranteed
62 * to be zeroed. Note that this also guarantees that res->surf.tiling
63 * will be ISL_TILING_LINEAR, so it's safe to check that.
67 /** Backing storage for the resource */
71 * A bitfield of PIPE_BIND_* indicating how this resource was bound
72 * in the past. Only meaningful for PIPE_BUFFER; used for flushing.
74 unsigned bind_history
;
77 * Auxiliary buffer information (CCS, MCS, or HiZ).
80 /** The surface layout for the auxiliary buffer. */
83 /** The buffer object containing the auxiliary data. */
86 /** Offset into 'bo' where the auxiliary surface starts. */
90 * \brief The type of auxiliary compression used by this resource.
92 * This describes the type of auxiliary compression that is intended to
93 * be used by this resource. An aux usage of ISL_AUX_USAGE_NONE means
94 * that auxiliary compression is permanently disabled. An aux usage
95 * other than ISL_AUX_USAGE_NONE does not imply that auxiliary
96 * compression will always be enabled for this surface.
98 enum isl_aux_usage usage
;
101 * A bitfield of ISL_AUX_* modes that might this resource might use.
103 * For example, a surface might use both CCS_E and CCS_D at times.
105 unsigned possible_usages
;
108 * \brief Maps miptree slices to their current aux state.
110 * This two-dimensional array is indexed as [level][layer] and stores an
111 * aux state for each slice.
113 enum isl_aux_state
**state
;
116 * If (1 << level) is set, HiZ is enabled for that miplevel.
122 * For external surfaces, this is DRM format modifier that was used to
123 * create or import the surface. For internal surfaces, this will always
124 * be DRM_FORMAT_MOD_INVALID.
126 const struct isl_drm_modifier_info
*mod_info
;
130 * A simple <resource, offset> tuple for storing a reference to a
131 * piece of state stored in a GPU buffer object.
133 struct iris_state_ref
{
134 struct pipe_resource
*res
;
139 * Gallium CSO for sampler views (texture views).
141 * In addition to the normal pipe_resource, this adds an ISL view
142 * which may reinterpret the format or restrict levels/layers.
144 * These can also be linear texture buffers.
146 struct iris_sampler_view
{
147 struct pipe_sampler_view base
;
148 struct isl_view view
;
150 /* A short-cut (not a reference) to the actual resource being viewed.
151 * Multi-planar (or depth+stencil) images may have multiple resources
152 * chained together; this skips having to traverse base->texture->*.
154 struct iris_resource
*res
;
156 /** The resource (BO) holding our SURFACE_STATE. */
157 struct iris_state_ref surface_state
;
161 * Gallium CSO for surfaces (framebuffer attachments).
163 * A view of a surface that can be bound to a color render target or
164 * depth/stencil attachment.
166 struct iris_surface
{
167 struct pipe_surface base
;
168 struct isl_view view
;
170 /** The resource (BO) holding our SURFACE_STATE. */
171 struct iris_state_ref surface_state
;
175 * Transfer object - information about a buffer mapping.
177 struct iris_transfer
{
178 struct pipe_transfer base
;
179 struct pipe_debug_callback
*dbg
;
183 void (*unmap
)(struct iris_transfer
*);
187 * Unwrap a pipe_resource to get the underlying iris_bo (for convenience).
189 static inline struct iris_bo
*
190 iris_resource_bo(struct pipe_resource
*p_res
)
192 struct iris_resource
*res
= (void *) p_res
;
196 struct iris_format_info
iris_format_for_usage(const struct gen_device_info
*,
198 isl_surf_usage_flags_t usage
);
200 struct pipe_resource
*iris_resource_get_separate_stencil(struct pipe_resource
*);
202 void iris_get_depth_stencil_resources(struct pipe_resource
*res
,
203 struct iris_resource
**out_z
,
204 struct iris_resource
**out_s
);
206 void iris_init_screen_resource_functions(struct pipe_screen
*pscreen
);
208 void iris_flush_and_dirty_for_history(struct iris_context
*ice
,
209 struct iris_batch
*batch
,
210 struct iris_resource
*res
);
212 unsigned iris_get_num_logical_layers(const struct iris_resource
*res
,
215 void iris_resource_disable_aux(struct iris_resource
*res
);
217 #define INTEL_REMAINING_LAYERS UINT32_MAX
218 #define INTEL_REMAINING_LEVELS UINT32_MAX
221 * Prepare a miptree for access
223 * This function should be called prior to any access to miptree in order to
224 * perform any needed resolves.
226 * \param[in] start_level The first mip level to be accessed
228 * \param[in] num_levels The number of miplevels to be accessed or
229 * INTEL_REMAINING_LEVELS to indicate every level
230 * above start_level will be accessed
232 * \param[in] start_layer The first array slice or 3D layer to be accessed
234 * \param[in] num_layers The number of array slices or 3D layers be
235 * accessed or INTEL_REMAINING_LAYERS to indicate
236 * every layer above start_layer will be accessed
238 * \param[in] aux_supported Whether or not the access will support the
239 * miptree's auxiliary compression format; this
240 * must be false for uncompressed miptrees
242 * \param[in] fast_clear_supported Whether or not the access will support
243 * fast clears in the miptree's auxiliary
247 iris_resource_prepare_access(struct iris_context
*ice
,
248 struct iris_batch
*batch
,
249 struct iris_resource
*res
,
250 uint32_t start_level
, uint32_t num_levels
,
251 uint32_t start_layer
, uint32_t num_layers
,
252 enum isl_aux_usage aux_usage
,
253 bool fast_clear_supported
);
256 * Complete a write operation
258 * This function should be called after any operation writes to a miptree.
259 * This will update the miptree's compression state so that future resolves
260 * happen correctly. Technically, this function can be called before the
261 * write occurs but the caller must ensure that they don't interlace
262 * iris_resource_prepare_access and iris_resource_finish_write calls to
263 * overlapping layer/level ranges.
265 * \param[in] level The mip level that was written
267 * \param[in] start_layer The first array slice or 3D layer written
269 * \param[in] num_layers The number of array slices or 3D layers
270 * written or INTEL_REMAINING_LAYERS to indicate
271 * every layer above start_layer was written
273 * \param[in] written_with_aux Whether or not the write was done with
274 * auxiliary compression enabled
277 iris_resource_finish_write(struct iris_context
*ice
,
278 struct iris_resource
*res
, uint32_t level
,
279 uint32_t start_layer
, uint32_t num_layers
,
280 enum isl_aux_usage aux_usage
);
282 /** Get the auxiliary compression state of a miptree slice */
284 iris_resource_get_aux_state(const struct iris_resource
*res
,
285 uint32_t level
, uint32_t layer
);
288 * Set the auxiliary compression state of a miptree slice range
290 * This function directly sets the auxiliary compression state of a slice
291 * range of a miptree. It only modifies data structures and does not do any
292 * resolves. This should only be called by code which directly performs
293 * compression operations such as fast clears and resolves. Most code should
294 * use iris_resource_prepare_access or iris_resource_finish_write.
297 iris_resource_set_aux_state(struct iris_context
*ice
,
298 struct iris_resource
*res
, uint32_t level
,
299 uint32_t start_layer
, uint32_t num_layers
,
300 enum isl_aux_state aux_state
);
303 * Prepare a miptree for raw access
305 * This helper prepares the miptree for access that knows nothing about any
306 * sort of compression whatsoever. This is useful when mapping the surface or
307 * using it with the blitter.
310 iris_resource_access_raw(struct iris_context
*ice
,
311 struct iris_batch
*batch
,
312 struct iris_resource
*res
,
313 uint32_t level
, uint32_t layer
,
317 iris_resource_prepare_access(ice
, batch
, res
, level
, 1, layer
, num_layers
,
318 ISL_AUX_USAGE_NONE
, false);
320 iris_resource_finish_write(ice
, res
, level
, layer
, num_layers
,
325 enum isl_aux_usage
iris_resource_texture_aux_usage(struct iris_context
*ice
,
326 const struct iris_resource
*res
,
327 enum isl_format view_fmt
,
328 enum gen9_astc5x5_wa_tex_type
);
329 void iris_resource_prepare_texture(struct iris_context
*ice
,
330 struct iris_batch
*batch
,
331 struct iris_resource
*res
,
332 enum isl_format view_format
,
333 uint32_t start_level
, uint32_t num_levels
,
334 uint32_t start_layer
, uint32_t num_layers
,
335 enum gen9_astc5x5_wa_tex_type
);
336 void iris_resource_prepare_image(struct iris_context
*ice
,
337 struct iris_batch
*batch
,
338 struct iris_resource
*res
);
340 void iris_resource_check_level_layer(const struct iris_resource
*res
,
341 uint32_t level
, uint32_t layer
);
343 bool iris_resource_level_has_hiz(const struct iris_resource
*res
,
346 enum isl_aux_usage
iris_resource_render_aux_usage(struct iris_context
*ice
,
347 struct iris_resource
*res
,
348 enum isl_format render_fmt
,
350 bool draw_aux_disabled
);
351 void iris_resource_prepare_render(struct iris_context
*ice
,
352 struct iris_batch
*batch
,
353 struct iris_resource
*res
, uint32_t level
,
354 uint32_t start_layer
, uint32_t layer_count
,
355 enum isl_aux_usage aux_usage
);
356 void iris_resource_finish_render(struct iris_context
*ice
,
357 struct iris_resource
*res
, uint32_t level
,
358 uint32_t start_layer
, uint32_t layer_count
,
359 enum isl_aux_usage aux_usage
);
360 void iris_resource_prepare_depth(struct iris_context
*ice
,
361 struct iris_batch
*batch
,
362 struct iris_resource
*res
, uint32_t level
,
363 uint32_t start_layer
, uint32_t layer_count
);
364 void iris_resource_finish_depth(struct iris_context
*ice
,
365 struct iris_resource
*res
, uint32_t level
,
366 uint32_t start_layer
, uint32_t layer_count
,