src/gallium/drivers/iris/iris_screen.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20  * DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 /**
  24  * @file iris_screen.c
  25  *
  26  * Screen related driver hooks and capability lists.
  27  *
  28  * A program may use multiple rendering contexts (iris_context), but
  29  * they all share a common screen (iris_screen).  Global driver state
  30  * can be stored in the screen; it may be accessed by multiple threads.
  31  */
  32
  33 #include <stdio.h>
  34 #include <errno.h>
  35 #include <sys/ioctl.h>
  36 #include "pipe/p_defines.h"
  37 #include "pipe/p_state.h"
  38 #include "pipe/p_context.h"
  39 #include "pipe/p_screen.h"
  40 #include "util/u_inlines.h"
  41 #include "util/u_format.h"
  42 #include "util/u_upload_mgr.h"
  43 #include "util/ralloc.h"
  44 #include "drm-uapi/i915_drm.h"
  45 #include "iris_context.h"
  46 #include "iris_defines.h"
  47 #include "iris_pipe.h"
  48 #include "iris_resource.h"
  49 #include "iris_screen.h"
  50 #include "intel/compiler/brw_compiler.h"
  51
  52 static void
  53 iris_flush_frontbuffer(struct pipe_screen *_screen,
  54                        struct pipe_resource *resource,
  55                        unsigned level, unsigned layer,
  56                        void *context_private, struct pipe_box *box)
  57 {
  58 }
  59
  60 static const char *
  61 iris_get_vendor(struct pipe_screen *pscreen)
  62 {
  63    return "Mesa Project";
  64 }
  65
  66 static const char *
  67 iris_get_device_vendor(struct pipe_screen *pscreen)
  68 {
  69    return "Intel";
  70 }
  71
  72 static const char *
  73 iris_get_name(struct pipe_screen *pscreen)
  74 {
  75    struct iris_screen *screen = (struct iris_screen *)pscreen;
  76    const char *chipset;
  77
  78    switch (screen->pci_id) {
  79 #undef CHIPSET
  80 #define CHIPSET(id, symbol, str) case id: chipset = str; break;
  81 #include "pci_ids/i965_pci_ids.h"
  82    default:
  83       chipset = "Unknown Intel Chipset";
  84       break;
  85    }
  86    return &chipset[9];
  87 }
  88
  89 static int
  90 iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  91 {
  92    struct iris_screen *screen = (struct iris_screen *)pscreen;
  93    const struct gen_device_info *devinfo = &screen->devinfo;
  94
  95    switch (param) {
  96    case PIPE_CAP_NPOT_TEXTURES:
  97    case PIPE_CAP_ANISOTROPIC_FILTER:
  98    case PIPE_CAP_POINT_SPRITE:
  99    case PIPE_CAP_OCCLUSION_QUERY:
 100    case PIPE_CAP_QUERY_TIME_ELAPSED:
 101    case PIPE_CAP_TEXTURE_SWIZZLE:
 102    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 103    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 104    case PIPE_CAP_SM3:
 105    case PIPE_CAP_PRIMITIVE_RESTART:
 106    case PIPE_CAP_INDEP_BLEND_ENABLE:
 107    case PIPE_CAP_INDEP_BLEND_FUNC:
 108    case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
 109    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 110    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 111    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 112    case PIPE_CAP_TGSI_INSTANCEID:
 113    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 114    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 115    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 116    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 117    case PIPE_CAP_CONDITIONAL_RENDER:
 118    case PIPE_CAP_TEXTURE_BARRIER:
 119    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 120    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 121    case PIPE_CAP_COMPUTE:
 122    case PIPE_CAP_START_INSTANCE:
 123    case PIPE_CAP_QUERY_TIMESTAMP:
 124    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 125    case PIPE_CAP_CUBE_MAP_ARRAY:
 126    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 127    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 128    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 129    case PIPE_CAP_TEXTURE_QUERY_LOD:
 130    case PIPE_CAP_SAMPLE_SHADING:
 131    case PIPE_CAP_DRAW_INDIRECT:
 132    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 133    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 134    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 135    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 136    case PIPE_CAP_ACCELERATED:
 137    case PIPE_CAP_UMA:
 138    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 139    case PIPE_CAP_CLIP_HALFZ:
 140    case PIPE_CAP_TGSI_TEXCOORD:
 141    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 142    case PIPE_CAP_DOUBLES:
 143    case PIPE_CAP_INT64:
 144    case PIPE_CAP_INT64_DIVMOD:
 145    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 146    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 147    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 148    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 149    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 150    case PIPE_CAP_CULL_DISTANCE:
 151    case PIPE_CAP_PACKED_UNIFORMS:
 152    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 153    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 154    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 155    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 156    case PIPE_CAP_POST_DEPTH_COVERAGE:
 157    case PIPE_CAP_QUERY_SO_OVERFLOW:
 158    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 159    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 160    case PIPE_CAP_TGSI_CLOCK:
 161    case PIPE_CAP_TGSI_BALLOT:
 162    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 163    case PIPE_CAP_CLEAR_TEXTURE:
 164    case PIPE_CAP_TGSI_VOTE:
 165    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 166    case PIPE_CAP_TEXTURE_GATHER_SM5:
 167    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 168    case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
 169       return true;
 170
 171    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 172       return 1;
 173    case PIPE_CAP_MAX_RENDER_TARGETS:
 174       return BRW_MAX_DRAW_BUFFERS;
 175    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 176    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 177       return 15; /* 16384x16384 */
 178    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 179       return 12; /* 2048x2048 */
 180    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 181       return 4;
 182    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 183       return 2048;
 184    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 185       return BRW_MAX_SOL_BINDINGS / IRIS_MAX_SOL_BUFFERS;
 186    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 187       return BRW_MAX_SOL_BINDINGS;
 188    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 189       return 460;
 190    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 191       return 140;
 192    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 193       /* 3DSTATE_CONSTANT_XS requires the start of UBOs to be 32B aligned */
 194       return 32;
 195    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 196       /* Choose a cacheline (64 bytes) so that we can safely have the CPU and
 197        * GPU writing the same SSBO on non-coherent systems (Atom CPUs).  With
 198        * UBOs, the GPU never writes, so there's no problem.  For an SSBO, the
 199        * GPU and the CPU can be updating disjoint regions of the buffer
 200        * simultaneously and that will break if the regions overlap the same
 201        * cacheline.
 202        */
 203       return 64;
 204    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 205       return 1 << 27;
 206    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 207       return 16; // XXX: u_screen says 256 is the minimum value...
 208    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 209       return true; // XXX: ?????
 210    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 211       return 1 << 27; /* 128MB */
 212    case PIPE_CAP_MAX_VIEWPORTS:
 213       return 16;
 214    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 215       return 256;
 216    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 217       return 1024;
 218    case PIPE_CAP_MAX_GS_INVOCATIONS:
 219       return 32;
 220    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 221       return 4;
 222    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 223       return -32;
 224    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 225       return 31;
 226    case PIPE_CAP_MAX_VERTEX_STREAMS:
 227       return 4;
 228    case PIPE_CAP_VENDOR_ID:
 229       return 0x8086;
 230    case PIPE_CAP_DEVICE_ID:
 231       return screen->pci_id;
 232    case PIPE_CAP_VIDEO_MEMORY:
 233       return 0xffffffff; // XXX: bogus
 234    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 235       return 32;
 236    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 237       /* AMD_pinned_memory assumes the flexibility of using client memory
 238        * for any buffer (incl. vertex buffers) which rules out the prospect
 239        * of using snooped buffers, as using snooped buffers without
 240        * cogniscience is likely to be detrimental to performance and require
 241        * extensive checking in the driver for correctness, e.g. to prevent
 242        * illegal snoop <-> snoop transfers.
 243        */
 244       return devinfo->has_llc;
 245
 246    // XXX: don't hardcode 00:00:02.0 PCI here
 247    case PIPE_CAP_PCI_GROUP:
 248       return 0;
 249    case PIPE_CAP_PCI_BUS:
 250       return 0;
 251    case PIPE_CAP_PCI_DEVICE:
 252       return 2;
 253    case PIPE_CAP_PCI_FUNCTION:
 254       return 0;
 255
 256    default:
 257       return u_pipe_screen_get_param_defaults(pscreen, param);
 258    }
 259    return 0;
 260 }
 261
 262 static float
 263 iris_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 264 {
 265    switch (param) {
 266    case PIPE_CAPF_MAX_LINE_WIDTH:
 267    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 268       return 7.375f;
 269
 270    case PIPE_CAPF_MAX_POINT_WIDTH:
 271    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 272       return 255.0f;
 273
 274    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 275       return 16.0f;
 276    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 277       return 15.0f;
 278    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 279    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 280    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 281       return 0.0f;
 282    default:
 283       unreachable("unknown param");
 284    }
 285 }
 286
 287 static int
 288 iris_get_shader_param(struct pipe_screen *pscreen,
 289                       enum pipe_shader_type p_stage,
 290                       enum pipe_shader_cap param)
 291 {
 292    struct iris_screen *screen = (struct iris_screen *)pscreen;
 293    struct brw_compiler *compiler = screen->compiler;
 294    gl_shader_stage stage = stage_from_pipe(p_stage);
 295
 296    /* this is probably not totally correct.. but it's a start: */
 297    switch (param) {
 298    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 299       return stage == MESA_SHADER_FRAGMENT ? 1024 : 16384;
 300    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 301    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 302    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 303       return stage == MESA_SHADER_FRAGMENT ? 1024 : 0;
 304
 305    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 306       return UINT_MAX;
 307
 308    case PIPE_SHADER_CAP_MAX_INPUTS:
 309       return stage == MESA_SHADER_VERTEX ? 16 : 32;
 310    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 311       return 32;
 312    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 313       return 16 * 1024 * sizeof(float);
 314    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 315       return 16;
 316    case PIPE_SHADER_CAP_MAX_TEMPS:
 317       return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
 318    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 319       return 0;
 320    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 321       return !compiler->glsl_compiler_options[stage].EmitNoIndirectInput;
 322    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 323       return !compiler->glsl_compiler_options[stage].EmitNoIndirectOutput;
 324    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 325       return !compiler->glsl_compiler_options[stage].EmitNoIndirectTemp;
 326    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 327       return 1;
 328    case PIPE_SHADER_CAP_SUBROUTINES:
 329       return 0;
 330    case PIPE_SHADER_CAP_INTEGERS:
 331    case PIPE_SHADER_CAP_SCALAR_ISA:
 332       return 1;
 333    case PIPE_SHADER_CAP_INT64_ATOMICS:
 334    case PIPE_SHADER_CAP_FP16:
 335       return 0;
 336    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 337    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 338    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 339       return IRIS_MAX_TEXTURE_SAMPLERS;
 340    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 341       return IRIS_MAX_ABOS + IRIS_MAX_SSBOS;
 342    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 343    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 344       return 0;
 345    case PIPE_SHADER_CAP_PREFERRED_IR:
 346       return PIPE_SHADER_IR_NIR;
 347    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 348       return 0;
 349    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 350       return 32;
 351    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 352    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 353    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 354    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 355    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 356    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 357    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 358    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 359       return 0;
 360    default:
 361       unreachable("unknown shader param");
 362    }
 363 }
 364
 365 static int
 366 iris_get_compute_param(struct pipe_screen *pscreen,
 367                        enum pipe_shader_ir ir_type,
 368                        enum pipe_compute_cap param,
 369                        void *ret)
 370 {
 371    /* TODO: compute shaders */
 372    return 0;
 373 }
 374
 375 static uint64_t
 376 iris_get_timestamp(struct pipe_screen *pscreen)
 377 {
 378    struct iris_screen *screen = (struct iris_screen *) pscreen;
 379    const unsigned TIMESTAMP = 0x2358;
 380    uint64_t result;
 381
 382    iris_reg_read(screen->bufmgr, TIMESTAMP | 1, &result);
 383
 384    result = iris_timebase_scale(&screen->devinfo, result);
 385    result &= (1ull << TIMESTAMP_BITS) - 1;
 386
 387    return result;
 388 }
 389
 390 static void
 391 iris_destroy_screen(struct pipe_screen *pscreen)
 392 {
 393    struct iris_screen *screen = (struct iris_screen *) pscreen;
 394    iris_bo_unreference(screen->workaround_bo);
 395    ralloc_free(screen);
 396 }
 397
 398 static void
 399 iris_fence_reference(struct pipe_screen *screen,
 400                      struct pipe_fence_handle **ptr,
 401                      struct pipe_fence_handle *fence)
 402 {
 403 }
 404
 405 static boolean
 406 iris_fence_finish(struct pipe_screen *screen,
 407                   struct pipe_context *ctx,
 408                   struct pipe_fence_handle *fence,
 409                   uint64_t timeout)
 410 {
 411    return true;
 412 }
 413
 414 static void
 415 iris_query_memory_info(struct pipe_screen *pscreen,
 416                        struct pipe_memory_info *info)
 417 {
 418 }
 419
 420 static const void *
 421 iris_get_compiler_options(struct pipe_screen *pscreen,
 422                           enum pipe_shader_ir ir,
 423                           enum pipe_shader_type pstage)
 424 {
 425    struct iris_screen *screen = (struct iris_screen *) pscreen;
 426    gl_shader_stage stage = stage_from_pipe(pstage);
 427    assert(ir == PIPE_SHADER_IR_NIR);
 428
 429    return screen->compiler->glsl_compiler_options[stage].NirOptions;
 430 }
 431
 432 static int
 433 iris_getparam(struct iris_screen *screen, int param, int *value)
 434 {
 435    struct drm_i915_getparam gp = { .param = param, .value = value };
 436
 437    if (ioctl(screen->fd, DRM_IOCTL_I915_GETPARAM, &gp) == -1)
 438       return -errno;
 439
 440    return 0;
 441 }
 442
 443 static bool
 444 iris_getparam_boolean(struct iris_screen *screen, int param)
 445 {
 446    int value = 0;
 447    return (iris_getparam(screen, param, &value) == 0) && value;
 448 }
 449
 450 static int
 451 iris_getparam_integer(struct iris_screen *screen, int param)
 452 {
 453    int value = -1;
 454
 455    if (iris_getparam(screen, param, &value) == 0)
 456       return value;
 457
 458    return -1;
 459 }
 460
 461 static void
 462 iris_shader_debug_log(void *data, const char *fmt, ...)
 463 {
 464    struct pipe_debug_callback *dbg = data;
 465    unsigned id = 0;
 466    va_list args;
 467
 468    if (!dbg->debug_message)
 469       return;
 470
 471    va_start(args, fmt);
 472    dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_SHADER_INFO, fmt, args);
 473    va_end(args);
 474 }
 475
 476 static void
 477 iris_shader_perf_log(void *data, const char *fmt, ...)
 478 {
 479    struct pipe_debug_callback *dbg = data;
 480    unsigned id = 0;
 481    va_list args;
 482
 483    if (!dbg->debug_message)
 484       return;
 485
 486    va_start(args, fmt);
 487    dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_PERF_INFO, fmt, args);
 488    va_end(args);
 489 }
 490
 491 struct pipe_screen *
 492 iris_screen_create(int fd)
 493 {
 494    struct iris_screen *screen = rzalloc(NULL, struct iris_screen);
 495    if (!screen)
 496       return NULL;
 497
 498    screen->fd = fd;
 499    screen->pci_id = iris_getparam_integer(screen, I915_PARAM_CHIPSET_ID);
 500
 501    if (!gen_get_device_info(screen->pci_id, &screen->devinfo))
 502       return NULL;
 503
 504    screen->devinfo.timestamp_frequency =
 505       iris_getparam_integer(screen, I915_PARAM_CS_TIMESTAMP_FREQUENCY);
 506
 507    screen->bufmgr = iris_bufmgr_init(&screen->devinfo, fd);
 508    if (!screen->bufmgr)
 509       return NULL;
 510
 511    screen->workaround_bo =
 512       iris_bo_alloc(screen->bufmgr, "workaround", 4096, IRIS_MEMZONE_OTHER);
 513    if (!screen->workaround_bo)
 514       return NULL;
 515
 516    brw_process_intel_debug_variable();
 517
 518    bool hw_has_swizzling = false; // XXX: detect?
 519    isl_device_init(&screen->isl_dev, &screen->devinfo, hw_has_swizzling);
 520
 521    screen->compiler = brw_compiler_create(screen, &screen->devinfo);
 522    screen->compiler->shader_debug_log = iris_shader_debug_log;
 523    screen->compiler->shader_perf_log = iris_shader_perf_log;
 524
 525    slab_create_parent(&screen->transfer_pool,
 526                       sizeof(struct iris_transfer), 64);
 527
 528    struct pipe_screen *pscreen = &screen->base;
 529
 530    iris_init_screen_resource_functions(pscreen);
 531
 532    pscreen->destroy = iris_destroy_screen;
 533    pscreen->get_name = iris_get_name;
 534    pscreen->get_vendor = iris_get_vendor;
 535    pscreen->get_device_vendor = iris_get_device_vendor;
 536    pscreen->get_param = iris_get_param;
 537    pscreen->get_shader_param = iris_get_shader_param;
 538    pscreen->get_compute_param = iris_get_compute_param;
 539    pscreen->get_paramf = iris_get_paramf;
 540    pscreen->get_compiler_options = iris_get_compiler_options;
 541    pscreen->is_format_supported = iris_is_format_supported;
 542    pscreen->context_create = iris_create_context;
 543    pscreen->flush_frontbuffer = iris_flush_frontbuffer;
 544    pscreen->get_timestamp = iris_get_timestamp;
 545    pscreen->fence_reference = iris_fence_reference;
 546    pscreen->fence_finish = iris_fence_finish;
 547    pscreen->query_memory_info = iris_query_memory_info;
 548
 549    return pscreen;
 550 }