src/gallium/drivers/iris/iris_screen.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20  * DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 /**
  24  * @file iris_screen.c
  25  *
  26  * Screen related driver hooks and capability lists.
  27  *
  28  * A program may use multiple rendering contexts (iris_context), but
  29  * they all share a common screen (iris_screen).  Global driver state
  30  * can be stored in the screen; it may be accessed by multiple threads.
  31  */
  32
  33 #include <stdio.h>
  34 #include <errno.h>
  35 #include <sys/ioctl.h>
  36 #include "pipe/p_defines.h"
  37 #include "pipe/p_state.h"
  38 #include "pipe/p_context.h"
  39 #include "pipe/p_screen.h"
  40 #include "util/debug.h"
  41 #include "util/u_inlines.h"
  42 #include "util/u_format.h"
  43 #include "util/u_transfer_helper.h"
  44 #include "util/u_upload_mgr.h"
  45 #include "util/ralloc.h"
  46 #include "util/xmlconfig.h"
  47 #include "drm-uapi/i915_drm.h"
  48 #include "iris_context.h"
  49 #include "iris_defines.h"
  50 #include "iris_fence.h"
  51 #include "iris_pipe.h"
  52 #include "iris_resource.h"
  53 #include "iris_screen.h"
  54 #include "intel/compiler/brw_compiler.h"
  55 #include "intel/common/gen_gem.h"
  56 #include "iris_monitor.h"
  57
  58 static void
  59 iris_flush_frontbuffer(struct pipe_screen *_screen,
  60                        struct pipe_resource *resource,
  61                        unsigned level, unsigned layer,
  62                        void *context_private, struct pipe_box *box)
  63 {
  64 }
  65
  66 static const char *
  67 iris_get_vendor(struct pipe_screen *pscreen)
  68 {
  69    return "Intel";
  70 }
  71
  72 static const char *
  73 iris_get_device_vendor(struct pipe_screen *pscreen)
  74 {
  75    return "Intel";
  76 }
  77
  78 static const char *
  79 iris_get_name(struct pipe_screen *pscreen)
  80 {
  81    struct iris_screen *screen = (struct iris_screen *)pscreen;
  82    static char buf[128];
  83    const char *chipset;
  84
  85    switch (screen->pci_id) {
  86 #undef CHIPSET
  87 #define CHIPSET(id, symbol, str) case id: chipset = str; break;
  88 #include "pci_ids/i965_pci_ids.h"
  89    default:
  90       chipset = "Unknown Intel Chipset";
  91       break;
  92    }
  93
  94    snprintf(buf, sizeof(buf), "Mesa %s", chipset);
  95    return buf;
  96 }
  97
  98 static uint64_t
  99 get_aperture_size(int fd)
 100 {
 101    struct drm_i915_gem_get_aperture aperture = {};
 102    gen_ioctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
 103    return aperture.aper_size;
 104 }
 105
 106 static int
 107 iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 108 {
 109    struct iris_screen *screen = (struct iris_screen *)pscreen;
 110    const struct gen_device_info *devinfo = &screen->devinfo;
 111
 112    switch (param) {
 113    case PIPE_CAP_NPOT_TEXTURES:
 114    case PIPE_CAP_ANISOTROPIC_FILTER:
 115    case PIPE_CAP_POINT_SPRITE:
 116    case PIPE_CAP_OCCLUSION_QUERY:
 117    case PIPE_CAP_QUERY_TIME_ELAPSED:
 118    case PIPE_CAP_TEXTURE_SWIZZLE:
 119    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 120    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 121    case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
 122    case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
 123    case PIPE_CAP_VERTEX_SHADER_SATURATE:
 124    case PIPE_CAP_PRIMITIVE_RESTART:
 125    case PIPE_CAP_INDEP_BLEND_ENABLE:
 126    case PIPE_CAP_INDEP_BLEND_FUNC:
 127    case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
 128    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 129    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 130    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 131    case PIPE_CAP_TGSI_INSTANCEID:
 132    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 133    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 134    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 135    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 136    case PIPE_CAP_CONDITIONAL_RENDER:
 137    case PIPE_CAP_TEXTURE_BARRIER:
 138    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 139    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 140    case PIPE_CAP_COMPUTE:
 141    case PIPE_CAP_START_INSTANCE:
 142    case PIPE_CAP_QUERY_TIMESTAMP:
 143    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 144    case PIPE_CAP_CUBE_MAP_ARRAY:
 145    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 146    case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE:
 147    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 148    case PIPE_CAP_TEXTURE_QUERY_LOD:
 149    case PIPE_CAP_SAMPLE_SHADING:
 150    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 151    case PIPE_CAP_DRAW_INDIRECT:
 152    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 153    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 154    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 155    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 156    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 157    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 158    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 159    case PIPE_CAP_ACCELERATED:
 160    case PIPE_CAP_UMA:
 161    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 162    case PIPE_CAP_CLIP_HALFZ:
 163    case PIPE_CAP_TGSI_TEXCOORD:
 164    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 165    case PIPE_CAP_DOUBLES:
 166    case PIPE_CAP_INT64:
 167    case PIPE_CAP_INT64_DIVMOD:
 168    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 169    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 170    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 171    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 172    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 173    case PIPE_CAP_CULL_DISTANCE:
 174    case PIPE_CAP_PACKED_UNIFORMS:
 175    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 176    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 177    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 178    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 179    case PIPE_CAP_QUERY_SO_OVERFLOW:
 180    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 181    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 182    case PIPE_CAP_TGSI_TXQS:
 183    case PIPE_CAP_TGSI_CLOCK:
 184    case PIPE_CAP_TGSI_BALLOT:
 185    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 186    case PIPE_CAP_CLEAR_TEXTURE:
 187    case PIPE_CAP_TGSI_VOTE:
 188    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 189    case PIPE_CAP_TEXTURE_GATHER_SM5:
 190    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 191    case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
 192    case PIPE_CAP_LOAD_CONSTBUF:
 193    case PIPE_CAP_NIR_COMPACT_ARRAYS:
 194    case PIPE_CAP_DRAW_PARAMETERS:
 195    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 196    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 197    case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES:
 198    case PIPE_CAP_INVALIDATE_BUFFER:
 199    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 200    case PIPE_CAP_CS_DERIVED_SYSTEM_VALUES_SUPPORTED:
 201    case PIPE_CAP_TEXTURE_SHADOW_LOD:
 202    case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
 203    case PIPE_CAP_GL_SPIRV:
 204    case PIPE_CAP_GL_SPIRV_VARIABLE_POINTERS:
 205    case PIPE_CAP_DEMOTE_TO_HELPER_INVOCATION:
 206       return true;
 207    case PIPE_CAP_FBFETCH:
 208       return BRW_MAX_DRAW_BUFFERS;
 209    case PIPE_CAP_FBFETCH_COHERENT:
 210    case PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE:
 211    case PIPE_CAP_POST_DEPTH_COVERAGE:
 212    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 213    case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
 214    case PIPE_CAP_FRAGMENT_SHADER_INTERLOCK:
 215    case PIPE_CAP_ATOMIC_FLOAT_MINMAX:
 216       return devinfo->gen >= 9;
 217    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 218       return 1;
 219    case PIPE_CAP_MAX_RENDER_TARGETS:
 220       return BRW_MAX_DRAW_BUFFERS;
 221    case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 222       return 16384;
 223    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 224       return IRIS_MAX_MIPLEVELS; /* 16384x16384 */
 225    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 226       return 12; /* 2048x2048 */
 227    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 228       return 4;
 229    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 230       return 2048;
 231    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 232       return BRW_MAX_SOL_BINDINGS / IRIS_MAX_SOL_BUFFERS;
 233    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 234       return BRW_MAX_SOL_BINDINGS;
 235    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 236    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 237       return 460;
 238    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 239       /* 3DSTATE_CONSTANT_XS requires the start of UBOs to be 32B aligned */
 240       return 32;
 241    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 242       return IRIS_MAP_BUFFER_ALIGNMENT;
 243    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 244       /* Choose a cacheline (64 bytes) so that we can safely have the CPU and
 245        * GPU writing the same SSBO on non-coherent systems (Atom CPUs).  With
 246        * UBOs, the GPU never writes, so there's no problem.  For an SSBO, the
 247        * GPU and the CPU can be updating disjoint regions of the buffer
 248        * simultaneously and that will break if the regions overlap the same
 249        * cacheline.
 250        */
 251       return 64;
 252    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 253       return 1 << 27;
 254    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 255       return 16; // XXX: u_screen says 256 is the minimum value...
 256    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 257       return true;
 258    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 259       return IRIS_MAX_TEXTURE_BUFFER_SIZE;
 260    case PIPE_CAP_MAX_VIEWPORTS:
 261       return 16;
 262    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 263       return 256;
 264    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 265       return 1024;
 266    case PIPE_CAP_MAX_GS_INVOCATIONS:
 267       return 32;
 268    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 269       return 4;
 270    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 271       return -32;
 272    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 273       return 31;
 274    case PIPE_CAP_MAX_VERTEX_STREAMS:
 275       return 4;
 276    case PIPE_CAP_VENDOR_ID:
 277       return 0x8086;
 278    case PIPE_CAP_DEVICE_ID:
 279       return screen->pci_id;
 280    case PIPE_CAP_VIDEO_MEMORY: {
 281       /* Once a batch uses more than 75% of the maximum mappable size, we
 282        * assume that there's some fragmentation, and we start doing extra
 283        * flushing, etc.  That's the big cliff apps will care about.
 284        */
 285       const unsigned gpu_mappable_megabytes =
 286          (screen->aperture_bytes * 3 / 4) / (1024 * 1024);
 287
 288       const long system_memory_pages = sysconf(_SC_PHYS_PAGES);
 289       const long system_page_size = sysconf(_SC_PAGE_SIZE);
 290
 291       if (system_memory_pages <= 0 || system_page_size <= 0)
 292          return -1;
 293
 294       const uint64_t system_memory_bytes =
 295          (uint64_t) system_memory_pages * (uint64_t) system_page_size;
 296
 297       const unsigned system_memory_megabytes =
 298          (unsigned) (system_memory_bytes / (1024 * 1024));
 299
 300       return MIN2(system_memory_megabytes, gpu_mappable_megabytes);
 301    }
 302    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 303    case PIPE_CAP_MAX_VARYINGS:
 304       return 32;
 305    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 306       /* AMD_pinned_memory assumes the flexibility of using client memory
 307        * for any buffer (incl. vertex buffers) which rules out the prospect
 308        * of using snooped buffers, as using snooped buffers without
 309        * cogniscience is likely to be detrimental to performance and require
 310        * extensive checking in the driver for correctness, e.g. to prevent
 311        * illegal snoop <-> snoop transfers.
 312        */
 313       return devinfo->has_llc;
 314    case PIPE_CAP_MAX_FRAMES_IN_FLIGHT:
 315       return screen->driconf.disable_throttling ? 0 : 1;
 316
 317    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 318       return PIPE_CONTEXT_PRIORITY_LOW |
 319              PIPE_CONTEXT_PRIORITY_MEDIUM |
 320              PIPE_CONTEXT_PRIORITY_HIGH;
 321
 322    // XXX: don't hardcode 00:00:02.0 PCI here
 323    case PIPE_CAP_PCI_GROUP:
 324       return 0;
 325    case PIPE_CAP_PCI_BUS:
 326       return 0;
 327    case PIPE_CAP_PCI_DEVICE:
 328       return 2;
 329    case PIPE_CAP_PCI_FUNCTION:
 330       return 0;
 331
 332    default:
 333       return u_pipe_screen_get_param_defaults(pscreen, param);
 334    }
 335    return 0;
 336 }
 337
 338 static float
 339 iris_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 340 {
 341    switch (param) {
 342    case PIPE_CAPF_MAX_LINE_WIDTH:
 343    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 344       return 7.375f;
 345
 346    case PIPE_CAPF_MAX_POINT_WIDTH:
 347    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 348       return 255.0f;
 349
 350    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 351       return 16.0f;
 352    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 353       return 15.0f;
 354    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 355    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 356    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 357       return 0.0f;
 358    default:
 359       unreachable("unknown param");
 360    }
 361 }
 362
 363 static int
 364 iris_get_shader_param(struct pipe_screen *pscreen,
 365                       enum pipe_shader_type p_stage,
 366                       enum pipe_shader_cap param)
 367 {
 368    gl_shader_stage stage = stage_from_pipe(p_stage);
 369
 370    /* this is probably not totally correct.. but it's a start: */
 371    switch (param) {
 372    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 373       return stage == MESA_SHADER_FRAGMENT ? 1024 : 16384;
 374    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 375    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 376    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 377       return stage == MESA_SHADER_FRAGMENT ? 1024 : 0;
 378
 379    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 380       return UINT_MAX;
 381
 382    case PIPE_SHADER_CAP_MAX_INPUTS:
 383       return stage == MESA_SHADER_VERTEX ? 16 : 32;
 384    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 385       return 32;
 386    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 387       return 16 * 1024 * sizeof(float);
 388    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 389       return 16;
 390    case PIPE_SHADER_CAP_MAX_TEMPS:
 391       return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
 392    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 393       return 0;
 394    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 395    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 396    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 397    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 398       /* Lie about these to avoid st/mesa's GLSL IR lowering of indirects,
 399        * which we don't want.  Our compiler backend will check brw_compiler's
 400        * options and call nir_lower_indirect_derefs appropriately anyway.
 401        */
 402       return true;
 403    case PIPE_SHADER_CAP_SUBROUTINES:
 404       return 0;
 405    case PIPE_SHADER_CAP_INTEGERS:
 406    case PIPE_SHADER_CAP_SCALAR_ISA:
 407       return 1;
 408    case PIPE_SHADER_CAP_INT64_ATOMICS:
 409    case PIPE_SHADER_CAP_FP16:
 410       return 0;
 411    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 412    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 413    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 414       return IRIS_MAX_TEXTURE_SAMPLERS;
 415    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 416       return IRIS_MAX_ABOS + IRIS_MAX_SSBOS;
 417    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 418    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 419       return 0;
 420    case PIPE_SHADER_CAP_PREFERRED_IR:
 421       return PIPE_SHADER_IR_NIR;
 422    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 423       return 1 << PIPE_SHADER_IR_NIR;
 424    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 425    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 426       return 1;
 427    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 428    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 429    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 430    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 431    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 432    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 433    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 434       return 0;
 435    default:
 436       unreachable("unknown shader param");
 437    }
 438 }
 439
 440 static int
 441 iris_get_compute_param(struct pipe_screen *pscreen,
 442                        enum pipe_shader_ir ir_type,
 443                        enum pipe_compute_cap param,
 444                        void *ret)
 445 {
 446    struct iris_screen *screen = (struct iris_screen *)pscreen;
 447    const struct gen_device_info *devinfo = &screen->devinfo;
 448
 449    const unsigned max_threads = MIN2(64, devinfo->max_cs_threads);
 450    const uint32_t max_invocations = 32 * max_threads;
 451
 452 #define RET(x) do {                  \
 453    if (ret)                          \
 454       memcpy(ret, x, sizeof(x));     \
 455    return sizeof(x);                 \
 456 } while (0)
 457
 458    switch (param) {
 459    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 460       RET((uint32_t []){ 32 });
 461
 462    case PIPE_COMPUTE_CAP_IR_TARGET:
 463       if (ret)
 464          strcpy(ret, "gen");
 465       return 4;
 466
 467    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 468       RET((uint64_t []) { 3 });
 469
 470    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 471       RET(((uint64_t []) { 65535, 65535, 65535 }));
 472
 473    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 474       /* MaxComputeWorkGroupSize[0..2] */
 475       RET(((uint64_t []) {max_invocations, max_invocations, max_invocations}));
 476
 477    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 478       /* MaxComputeWorkGroupInvocations */
 479       RET((uint64_t []) { max_invocations });
 480
 481    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 482       /* MaxComputeSharedMemorySize */
 483       RET((uint64_t []) { 64 * 1024 });
 484
 485    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 486       RET((uint32_t []) { 1 });
 487
 488    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 489       RET((uint32_t []) { BRW_SUBGROUP_SIZE });
 490
 491    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 492    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 493    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 494    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 495    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 496    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 497    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 498       // XXX: I think these are for Clover...
 499       return 0;
 500
 501    default:
 502       unreachable("unknown compute param");
 503    }
 504 }
 505
 506 static uint64_t
 507 iris_get_timestamp(struct pipe_screen *pscreen)
 508 {
 509    struct iris_screen *screen = (struct iris_screen *) pscreen;
 510    const unsigned TIMESTAMP = 0x2358;
 511    uint64_t result;
 512
 513    iris_reg_read(screen->bufmgr, TIMESTAMP | 1, &result);
 514
 515    result = gen_device_info_timebase_scale(&screen->devinfo, result);
 516    result &= (1ull << TIMESTAMP_BITS) - 1;
 517
 518    return result;
 519 }
 520
 521 static void
 522 iris_destroy_screen(struct pipe_screen *pscreen)
 523 {
 524    struct iris_screen *screen = (struct iris_screen *) pscreen;
 525    iris_bo_unreference(screen->workaround_bo);
 526    u_transfer_helper_destroy(pscreen->transfer_helper);
 527    iris_bufmgr_destroy(screen->bufmgr);
 528    disk_cache_destroy(screen->disk_cache);
 529    close(screen->fd);
 530    ralloc_free(screen);
 531 }
 532
 533 static void
 534 iris_query_memory_info(struct pipe_screen *pscreen,
 535                        struct pipe_memory_info *info)
 536 {
 537 }
 538
 539 static const void *
 540 iris_get_compiler_options(struct pipe_screen *pscreen,
 541                           enum pipe_shader_ir ir,
 542                           enum pipe_shader_type pstage)
 543 {
 544    struct iris_screen *screen = (struct iris_screen *) pscreen;
 545    gl_shader_stage stage = stage_from_pipe(pstage);
 546    assert(ir == PIPE_SHADER_IR_NIR);
 547
 548    return screen->compiler->glsl_compiler_options[stage].NirOptions;
 549 }
 550
 551 static struct disk_cache *
 552 iris_get_disk_shader_cache(struct pipe_screen *pscreen)
 553 {
 554    struct iris_screen *screen = (struct iris_screen *) pscreen;
 555    return screen->disk_cache;
 556 }
 557
 558 static int
 559 iris_getparam(struct iris_screen *screen, int param, int *value)
 560 {
 561    struct drm_i915_getparam gp = { .param = param, .value = value };
 562
 563    if (ioctl(screen->fd, DRM_IOCTL_I915_GETPARAM, &gp) == -1)
 564       return -errno;
 565
 566    return 0;
 567 }
 568
 569 static int
 570 iris_getparam_integer(struct iris_screen *screen, int param)
 571 {
 572    int value = -1;
 573
 574    if (iris_getparam(screen, param, &value) == 0)
 575       return value;
 576
 577    return -1;
 578 }
 579
 580 static void
 581 iris_shader_debug_log(void *data, const char *fmt, ...)
 582 {
 583    struct pipe_debug_callback *dbg = data;
 584    unsigned id = 0;
 585    va_list args;
 586
 587    if (!dbg->debug_message)
 588       return;
 589
 590    va_start(args, fmt);
 591    dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_SHADER_INFO, fmt, args);
 592    va_end(args);
 593 }
 594
 595 static void
 596 iris_shader_perf_log(void *data, const char *fmt, ...)
 597 {
 598    struct pipe_debug_callback *dbg = data;
 599    unsigned id = 0;
 600    va_list args;
 601    va_start(args, fmt);
 602
 603    if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
 604       va_list args_copy;
 605       va_copy(args_copy, args);
 606       vfprintf(stderr, fmt, args_copy);
 607       va_end(args_copy);
 608    }
 609
 610    if (dbg->debug_message) {
 611       dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_PERF_INFO, fmt, args);
 612    }
 613
 614    va_end(args);
 615 }
 616
 617 struct pipe_screen *
 618 iris_screen_create(int fd, const struct pipe_screen_config *config)
 619 {
 620    struct iris_screen *screen = rzalloc(NULL, struct iris_screen);
 621    if (!screen)
 622       return NULL;
 623
 624    screen->fd = fd;
 625
 626    if (!gen_get_device_info_from_fd(fd, &screen->devinfo))
 627       return NULL;
 628    screen->pci_id = screen->devinfo.chipset_id;
 629    screen->no_hw = screen->devinfo.no_hw;
 630
 631    if (screen->devinfo.gen < 8 || screen->devinfo.is_cherryview)
 632       return NULL;
 633
 634    screen->aperture_bytes = get_aperture_size(fd);
 635
 636    if (getenv("INTEL_NO_HW") != NULL)
 637       screen->no_hw = true;
 638
 639    bool bo_reuse = false;
 640    int bo_reuse_mode = driQueryOptioni(config->options, "bo_reuse");
 641    switch (bo_reuse_mode) {
 642    case DRI_CONF_BO_REUSE_DISABLED:
 643       break;
 644    case DRI_CONF_BO_REUSE_ALL:
 645       bo_reuse = true;
 646       break;
 647    }
 648
 649    screen->bufmgr = iris_bufmgr_init(&screen->devinfo, fd, bo_reuse);
 650    if (!screen->bufmgr)
 651       return NULL;
 652
 653    screen->workaround_bo =
 654       iris_bo_alloc(screen->bufmgr, "workaround", 4096, IRIS_MEMZONE_OTHER);
 655    if (!screen->workaround_bo)
 656       return NULL;
 657
 658    brw_process_intel_debug_variable();
 659
 660    screen->driconf.dual_color_blend_by_location =
 661       driQueryOptionb(config->options, "dual_color_blend_by_location");
 662    screen->driconf.disable_throttling =
 663       driQueryOptionb(config->options, "disable_throttling");
 664    screen->driconf.always_flush_cache =
 665       driQueryOptionb(config->options, "always_flush_cache");
 666
 667    screen->precompile = env_var_as_boolean("shader_precompile", true);
 668
 669    isl_device_init(&screen->isl_dev, &screen->devinfo, false);
 670
 671    screen->compiler = brw_compiler_create(screen, &screen->devinfo);
 672    screen->compiler->shader_debug_log = iris_shader_debug_log;
 673    screen->compiler->shader_perf_log = iris_shader_perf_log;
 674    screen->compiler->supports_pull_constants = false;
 675    screen->compiler->supports_shader_constants = true;
 676
 677    iris_disk_cache_init(screen);
 678
 679    slab_create_parent(&screen->transfer_pool,
 680                       sizeof(struct iris_transfer), 64);
 681
 682    screen->subslice_total =
 683       iris_getparam_integer(screen, I915_PARAM_SUBSLICE_TOTAL);
 684    assert(screen->subslice_total >= 1);
 685
 686    struct pipe_screen *pscreen = &screen->base;
 687
 688    iris_init_screen_fence_functions(pscreen);
 689    iris_init_screen_resource_functions(pscreen);
 690
 691    pscreen->destroy = iris_destroy_screen;
 692    pscreen->get_name = iris_get_name;
 693    pscreen->get_vendor = iris_get_vendor;
 694    pscreen->get_device_vendor = iris_get_device_vendor;
 695    pscreen->get_param = iris_get_param;
 696    pscreen->get_shader_param = iris_get_shader_param;
 697    pscreen->get_compute_param = iris_get_compute_param;
 698    pscreen->get_paramf = iris_get_paramf;
 699    pscreen->get_compiler_options = iris_get_compiler_options;
 700    pscreen->get_disk_shader_cache = iris_get_disk_shader_cache;
 701    pscreen->is_format_supported = iris_is_format_supported;
 702    pscreen->context_create = iris_create_context;
 703    pscreen->flush_frontbuffer = iris_flush_frontbuffer;
 704    pscreen->get_timestamp = iris_get_timestamp;
 705    pscreen->query_memory_info = iris_query_memory_info;
 706    pscreen->get_driver_query_group_info = iris_get_monitor_group_info;
 707    pscreen->get_driver_query_info = iris_get_monitor_info;
 708
 709    return pscreen;
 710 }