2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
26 * Screen related driver hooks and capability lists.
28 * A program may use multiple rendering contexts (iris_context), but
29 * they all share a common screen (iris_screen). Global driver state
30 * can be stored in the screen; it may be accessed by multiple threads.
35 #include <sys/ioctl.h>
36 #include "pipe/p_defines.h"
37 #include "pipe/p_state.h"
38 #include "pipe/p_context.h"
39 #include "pipe/p_screen.h"
40 #include "util/debug.h"
41 #include "util/u_inlines.h"
42 #include "util/u_format.h"
43 #include "util/u_transfer_helper.h"
44 #include "util/u_upload_mgr.h"
45 #include "util/ralloc.h"
46 #include "drm-uapi/i915_drm.h"
47 #include "iris_context.h"
48 #include "iris_defines.h"
49 #include "iris_fence.h"
50 #include "iris_pipe.h"
51 #include "iris_resource.h"
52 #include "iris_screen.h"
53 #include "intel/compiler/brw_compiler.h"
56 iris_flush_frontbuffer(struct pipe_screen
*_screen
,
57 struct pipe_resource
*resource
,
58 unsigned level
, unsigned layer
,
59 void *context_private
, struct pipe_box
*box
)
64 iris_get_vendor(struct pipe_screen
*pscreen
)
66 return "Mesa Project";
70 iris_get_device_vendor(struct pipe_screen
*pscreen
)
76 iris_get_name(struct pipe_screen
*pscreen
)
78 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
81 switch (screen
->pci_id
) {
83 #define CHIPSET(id, symbol, str) case id: chipset = str; break;
84 #include "pci_ids/i965_pci_ids.h"
86 chipset
= "Unknown Intel Chipset";
93 iris_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
95 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
96 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
99 case PIPE_CAP_NPOT_TEXTURES
:
100 case PIPE_CAP_ANISOTROPIC_FILTER
:
101 case PIPE_CAP_POINT_SPRITE
:
102 case PIPE_CAP_OCCLUSION_QUERY
:
103 case PIPE_CAP_QUERY_TIME_ELAPSED
:
104 case PIPE_CAP_TEXTURE_SWIZZLE
:
105 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE
:
106 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
108 case PIPE_CAP_PRIMITIVE_RESTART
:
109 case PIPE_CAP_INDEP_BLEND_ENABLE
:
110 case PIPE_CAP_INDEP_BLEND_FUNC
:
111 case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND
:
112 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
113 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
114 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
115 case PIPE_CAP_TGSI_INSTANCEID
:
116 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
117 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
118 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
119 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
120 case PIPE_CAP_CONDITIONAL_RENDER
:
121 case PIPE_CAP_TEXTURE_BARRIER
:
122 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
123 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
124 case PIPE_CAP_COMPUTE
:
125 case PIPE_CAP_START_INSTANCE
:
126 case PIPE_CAP_QUERY_TIMESTAMP
:
127 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
128 case PIPE_CAP_CUBE_MAP_ARRAY
:
129 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
130 case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE
:
131 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
132 case PIPE_CAP_TEXTURE_QUERY_LOD
:
133 case PIPE_CAP_SAMPLE_SHADING
:
134 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
135 case PIPE_CAP_DRAW_INDIRECT
:
136 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
137 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
138 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT
:
139 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
140 case PIPE_CAP_ACCELERATED
:
142 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
143 case PIPE_CAP_CLIP_HALFZ
:
144 case PIPE_CAP_TGSI_TEXCOORD
:
145 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
146 case PIPE_CAP_DOUBLES
:
148 case PIPE_CAP_INT64_DIVMOD
:
149 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
:
150 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
151 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
152 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
153 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
154 case PIPE_CAP_CULL_DISTANCE
:
155 case PIPE_CAP_PACKED_UNIFORMS
:
156 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET
:
157 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
158 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
159 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
160 case PIPE_CAP_QUERY_SO_OVERFLOW
:
161 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
162 case PIPE_CAP_TGSI_TEX_TXF_LZ
:
163 case PIPE_CAP_TGSI_TXQS
:
164 case PIPE_CAP_TGSI_CLOCK
:
165 case PIPE_CAP_TGSI_BALLOT
:
166 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
167 case PIPE_CAP_CLEAR_TEXTURE
:
168 case PIPE_CAP_TGSI_VOTE
:
169 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
170 case PIPE_CAP_TEXTURE_GATHER_SM5
:
171 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
172 case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS
:
173 case PIPE_CAP_LOAD_CONSTBUF
:
174 case PIPE_CAP_NIR_COMPACT_ARRAYS
:
176 case PIPE_CAP_TGSI_FS_FBFETCH
:
177 case PIPE_CAP_POST_DEPTH_COVERAGE
:
178 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
179 return devinfo
->gen
>= 9;
180 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
182 case PIPE_CAP_MAX_RENDER_TARGETS
:
183 return BRW_MAX_DRAW_BUFFERS
;
184 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
185 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
186 return 15; /* 16384x16384 */
187 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
188 return 12; /* 2048x2048 */
189 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
191 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
193 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
194 return BRW_MAX_SOL_BINDINGS
/ IRIS_MAX_SOL_BUFFERS
;
195 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
196 return BRW_MAX_SOL_BINDINGS
;
197 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
199 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY
:
201 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
202 /* 3DSTATE_CONSTANT_XS requires the start of UBOs to be 32B aligned */
204 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
205 /* Choose a cacheline (64 bytes) so that we can safely have the CPU and
206 * GPU writing the same SSBO on non-coherent systems (Atom CPUs). With
207 * UBOs, the GPU never writes, so there's no problem. For an SSBO, the
208 * GPU and the CPU can be updating disjoint regions of the buffer
209 * simultaneously and that will break if the regions overlap the same
213 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE
:
215 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
216 return 16; // XXX: u_screen says 256 is the minimum value...
217 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
218 return true; // XXX: ?????
219 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
220 return IRIS_MAX_TEXTURE_BUFFER_SIZE
;
221 case PIPE_CAP_MAX_VIEWPORTS
:
223 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
225 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
227 case PIPE_CAP_MAX_GS_INVOCATIONS
:
229 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
231 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
233 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
235 case PIPE_CAP_MAX_VERTEX_STREAMS
:
237 case PIPE_CAP_VENDOR_ID
:
239 case PIPE_CAP_DEVICE_ID
:
240 return screen
->pci_id
;
241 case PIPE_CAP_VIDEO_MEMORY
:
242 return 0xffffffff; // XXX: bogus
243 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
245 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
246 /* AMD_pinned_memory assumes the flexibility of using client memory
247 * for any buffer (incl. vertex buffers) which rules out the prospect
248 * of using snooped buffers, as using snooped buffers without
249 * cogniscience is likely to be detrimental to performance and require
250 * extensive checking in the driver for correctness, e.g. to prevent
251 * illegal snoop <-> snoop transfers.
253 return devinfo
->has_llc
;
255 // XXX: don't hardcode 00:00:02.0 PCI here
256 case PIPE_CAP_PCI_GROUP
:
258 case PIPE_CAP_PCI_BUS
:
260 case PIPE_CAP_PCI_DEVICE
:
262 case PIPE_CAP_PCI_FUNCTION
:
266 return u_pipe_screen_get_param_defaults(pscreen
, param
);
272 iris_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
275 case PIPE_CAPF_MAX_LINE_WIDTH
:
276 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
279 case PIPE_CAPF_MAX_POINT_WIDTH
:
280 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
283 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
285 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
287 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE
:
288 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE
:
289 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY
:
292 unreachable("unknown param");
297 iris_get_shader_param(struct pipe_screen
*pscreen
,
298 enum pipe_shader_type p_stage
,
299 enum pipe_shader_cap param
)
301 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
302 struct brw_compiler
*compiler
= screen
->compiler
;
303 gl_shader_stage stage
= stage_from_pipe(p_stage
);
305 /* this is probably not totally correct.. but it's a start: */
307 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
308 return stage
== MESA_SHADER_FRAGMENT
? 1024 : 16384;
309 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
310 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
311 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
312 return stage
== MESA_SHADER_FRAGMENT
? 1024 : 0;
314 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
317 case PIPE_SHADER_CAP_MAX_INPUTS
:
318 return stage
== MESA_SHADER_VERTEX
? 16 : 32;
319 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
321 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
322 return 16 * 1024 * sizeof(float);
323 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
325 case PIPE_SHADER_CAP_MAX_TEMPS
:
326 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
327 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
329 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
330 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
331 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
332 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
333 /* Lie about these to avoid st/mesa's GLSL IR lowering of indirects,
334 * which we don't want. Our compiler backend will check brw_compiler's
335 * options and call nir_lower_indirect_derefs appropriately anyway.
338 case PIPE_SHADER_CAP_SUBROUTINES
:
340 case PIPE_SHADER_CAP_INTEGERS
:
341 case PIPE_SHADER_CAP_SCALAR_ISA
:
343 case PIPE_SHADER_CAP_INT64_ATOMICS
:
344 case PIPE_SHADER_CAP_FP16
:
346 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
347 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
348 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
349 return IRIS_MAX_TEXTURE_SAMPLERS
;
350 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
351 return IRIS_MAX_ABOS
+ IRIS_MAX_SSBOS
;
352 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
353 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
355 case PIPE_SHADER_CAP_PREFERRED_IR
:
356 return PIPE_SHADER_IR_NIR
;
357 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
358 return 1 << PIPE_SHADER_IR_NIR
;
359 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
361 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
362 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
363 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
364 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
365 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
366 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
367 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
368 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
371 unreachable("unknown shader param");
376 iris_get_compute_param(struct pipe_screen
*pscreen
,
377 enum pipe_shader_ir ir_type
,
378 enum pipe_compute_cap param
,
381 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
382 struct brw_compiler
*compiler
= screen
->compiler
;
383 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
385 const unsigned max_threads
= MIN2(64, devinfo
->max_cs_threads
);
386 const uint32_t max_invocations
= 32 * max_threads
;
388 #define RET(x) do { \
390 memcpy(ret, x, sizeof(x)); \
395 case PIPE_COMPUTE_CAP_ADDRESS_BITS
:
396 RET((uint32_t []){ 32 });
398 case PIPE_COMPUTE_CAP_IR_TARGET
:
403 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
404 RET((uint64_t []) { 3 });
406 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
407 RET(((uint64_t []) { 65535, 65535, 65535 }));
409 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
410 /* MaxComputeWorkGroupSize[0..2] */
411 RET(((uint64_t []) {max_invocations
, max_invocations
, max_invocations
}));
413 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
414 /* MaxComputeWorkGroupInvocations */
415 RET((uint64_t []) { max_invocations
});
417 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
418 /* MaxComputeSharedMemorySize */
419 RET((uint64_t []) { 64 * 1024 });
421 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
422 RET((uint32_t []) { 1 });
424 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE
:
425 RET((uint32_t []) { BRW_SUBGROUP_SIZE
});
427 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
428 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
429 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
430 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
431 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
:
432 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
433 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK
:
434 // XXX: I think these are for Clover...
438 unreachable("unknown compute param");
443 iris_get_timestamp(struct pipe_screen
*pscreen
)
445 struct iris_screen
*screen
= (struct iris_screen
*) pscreen
;
446 const unsigned TIMESTAMP
= 0x2358;
449 iris_reg_read(screen
->bufmgr
, TIMESTAMP
| 1, &result
);
451 result
= iris_timebase_scale(&screen
->devinfo
, result
);
452 result
&= (1ull << TIMESTAMP_BITS
) - 1;
458 iris_destroy_screen(struct pipe_screen
*pscreen
)
460 struct iris_screen
*screen
= (struct iris_screen
*) pscreen
;
461 iris_bo_unreference(screen
->workaround_bo
);
462 u_transfer_helper_destroy(pscreen
->transfer_helper
);
463 iris_bufmgr_destroy(screen
->bufmgr
);
468 iris_query_memory_info(struct pipe_screen
*pscreen
,
469 struct pipe_memory_info
*info
)
474 iris_get_compiler_options(struct pipe_screen
*pscreen
,
475 enum pipe_shader_ir ir
,
476 enum pipe_shader_type pstage
)
478 struct iris_screen
*screen
= (struct iris_screen
*) pscreen
;
479 gl_shader_stage stage
= stage_from_pipe(pstage
);
480 assert(ir
== PIPE_SHADER_IR_NIR
);
482 return screen
->compiler
->glsl_compiler_options
[stage
].NirOptions
;
486 iris_getparam(struct iris_screen
*screen
, int param
, int *value
)
488 struct drm_i915_getparam gp
= { .param
= param
, .value
= value
};
490 if (ioctl(screen
->fd
, DRM_IOCTL_I915_GETPARAM
, &gp
) == -1)
497 iris_getparam_boolean(struct iris_screen
*screen
, int param
)
500 return (iris_getparam(screen
, param
, &value
) == 0) && value
;
504 iris_getparam_integer(struct iris_screen
*screen
, int param
)
508 if (iris_getparam(screen
, param
, &value
) == 0)
515 iris_shader_debug_log(void *data
, const char *fmt
, ...)
517 struct pipe_debug_callback
*dbg
= data
;
521 if (!dbg
->debug_message
)
525 dbg
->debug_message(dbg
->data
, &id
, PIPE_DEBUG_TYPE_SHADER_INFO
, fmt
, args
);
530 iris_shader_perf_log(void *data
, const char *fmt
, ...)
532 struct pipe_debug_callback
*dbg
= data
;
536 if (!dbg
->debug_message
)
540 dbg
->debug_message(dbg
->data
, &id
, PIPE_DEBUG_TYPE_PERF_INFO
, fmt
, args
);
545 iris_screen_create(int fd
)
547 struct iris_screen
*screen
= rzalloc(NULL
, struct iris_screen
);
552 screen
->pci_id
= iris_getparam_integer(screen
, I915_PARAM_CHIPSET_ID
);
554 if (!gen_get_device_info(screen
->pci_id
, &screen
->devinfo
))
557 if (screen
->devinfo
.gen
< 8 || screen
->devinfo
.is_cherryview
)
560 screen
->devinfo
.timestamp_frequency
=
561 iris_getparam_integer(screen
, I915_PARAM_CS_TIMESTAMP_FREQUENCY
);
563 screen
->bufmgr
= iris_bufmgr_init(&screen
->devinfo
, fd
);
567 screen
->workaround_bo
=
568 iris_bo_alloc(screen
->bufmgr
, "workaround", 4096, IRIS_MEMZONE_OTHER
);
569 if (!screen
->workaround_bo
)
572 brw_process_intel_debug_variable();
574 screen
->precompile
= env_var_as_boolean("shader_precompile", true);
576 bool hw_has_swizzling
= false; // XXX: detect?
577 isl_device_init(&screen
->isl_dev
, &screen
->devinfo
, hw_has_swizzling
);
579 screen
->compiler
= brw_compiler_create(screen
, &screen
->devinfo
);
580 screen
->compiler
->shader_debug_log
= iris_shader_debug_log
;
581 screen
->compiler
->shader_perf_log
= iris_shader_perf_log
;
582 screen
->compiler
->supports_pull_constants
= false;
584 slab_create_parent(&screen
->transfer_pool
,
585 sizeof(struct iris_transfer
), 64);
587 screen
->subslice_total
=
588 iris_getparam_integer(screen
, I915_PARAM_SUBSLICE_TOTAL
);
589 assert(screen
->subslice_total
>= 1);
591 struct pipe_screen
*pscreen
= &screen
->base
;
593 iris_init_screen_fence_functions(pscreen
);
594 iris_init_screen_resource_functions(pscreen
);
596 pscreen
->destroy
= iris_destroy_screen
;
597 pscreen
->get_name
= iris_get_name
;
598 pscreen
->get_vendor
= iris_get_vendor
;
599 pscreen
->get_device_vendor
= iris_get_device_vendor
;
600 pscreen
->get_param
= iris_get_param
;
601 pscreen
->get_shader_param
= iris_get_shader_param
;
602 pscreen
->get_compute_param
= iris_get_compute_param
;
603 pscreen
->get_paramf
= iris_get_paramf
;
604 pscreen
->get_compiler_options
= iris_get_compiler_options
;
605 pscreen
->is_format_supported
= iris_is_format_supported
;
606 pscreen
->context_create
= iris_create_context
;
607 pscreen
->flush_frontbuffer
= iris_flush_frontbuffer
;
608 pscreen
->get_timestamp
= iris_get_timestamp
;
609 pscreen
->query_memory_info
= iris_query_memory_info
;