2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
26 * Screen related driver hooks and capability lists.
28 * A program may use multiple rendering contexts (iris_context), but
29 * they all share a common screen (iris_screen). Global driver state
30 * can be stored in the screen; it may be accessed by multiple threads.
35 #include <sys/ioctl.h>
36 #include "pipe/p_defines.h"
37 #include "pipe/p_state.h"
38 #include "pipe/p_context.h"
39 #include "pipe/p_screen.h"
40 #include "util/debug.h"
41 #include "util/u_inlines.h"
42 #include "util/format/u_format.h"
43 #include "util/u_transfer_helper.h"
44 #include "util/u_upload_mgr.h"
45 #include "util/ralloc.h"
46 #include "util/xmlconfig.h"
47 #include "drm-uapi/i915_drm.h"
48 #include "iris_context.h"
49 #include "iris_defines.h"
50 #include "iris_fence.h"
51 #include "iris_pipe.h"
52 #include "iris_resource.h"
53 #include "iris_screen.h"
54 #include "intel/compiler/brw_compiler.h"
55 #include "intel/common/gen_gem.h"
56 #include "intel/common/gen_l3_config.h"
57 #include "iris_monitor.h"
60 iris_flush_frontbuffer(struct pipe_screen
*_screen
,
61 struct pipe_resource
*resource
,
62 unsigned level
, unsigned layer
,
63 void *context_private
, struct pipe_box
*box
)
68 iris_get_vendor(struct pipe_screen
*pscreen
)
74 iris_get_device_vendor(struct pipe_screen
*pscreen
)
80 iris_get_name(struct pipe_screen
*pscreen
)
82 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
84 const char *name
= gen_get_device_name(screen
->pci_id
);
87 name
= "Intel Unknown";
89 snprintf(buf
, sizeof(buf
), "Mesa %s", name
);
94 get_aperture_size(int fd
)
96 struct drm_i915_gem_get_aperture aperture
= {};
97 gen_ioctl(fd
, DRM_IOCTL_I915_GEM_GET_APERTURE
, &aperture
);
98 return aperture
.aper_size
;
102 iris_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
104 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
105 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
108 case PIPE_CAP_NPOT_TEXTURES
:
109 case PIPE_CAP_ANISOTROPIC_FILTER
:
110 case PIPE_CAP_POINT_SPRITE
:
111 case PIPE_CAP_OCCLUSION_QUERY
:
112 case PIPE_CAP_QUERY_TIME_ELAPSED
:
113 case PIPE_CAP_TEXTURE_SWIZZLE
:
114 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE
:
115 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
116 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD
:
117 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES
:
118 case PIPE_CAP_VERTEX_SHADER_SATURATE
:
119 case PIPE_CAP_PRIMITIVE_RESTART
:
120 case PIPE_CAP_INDEP_BLEND_ENABLE
:
121 case PIPE_CAP_INDEP_BLEND_FUNC
:
122 case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND
:
123 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
124 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
125 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
126 case PIPE_CAP_TGSI_INSTANCEID
:
127 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
128 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
129 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
130 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
131 case PIPE_CAP_CONDITIONAL_RENDER
:
132 case PIPE_CAP_TEXTURE_BARRIER
:
133 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
134 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
135 case PIPE_CAP_COMPUTE
:
136 case PIPE_CAP_START_INSTANCE
:
137 case PIPE_CAP_QUERY_TIMESTAMP
:
138 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
139 case PIPE_CAP_CUBE_MAP_ARRAY
:
140 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
141 case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE
:
142 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
143 case PIPE_CAP_TEXTURE_QUERY_LOD
:
144 case PIPE_CAP_SAMPLE_SHADING
:
145 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
146 case PIPE_CAP_DRAW_INDIRECT
:
147 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
148 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
149 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
150 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
151 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT
:
152 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
153 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
154 case PIPE_CAP_ACCELERATED
:
156 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
157 case PIPE_CAP_CLIP_HALFZ
:
158 case PIPE_CAP_TGSI_TEXCOORD
:
159 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
160 case PIPE_CAP_DOUBLES
:
162 case PIPE_CAP_INT64_DIVMOD
:
163 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
164 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
165 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
166 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
167 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
168 case PIPE_CAP_CULL_DISTANCE
:
169 case PIPE_CAP_PACKED_UNIFORMS
:
170 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET
:
171 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
172 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
173 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
174 case PIPE_CAP_QUERY_SO_OVERFLOW
:
175 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
176 case PIPE_CAP_TGSI_TEX_TXF_LZ
:
177 case PIPE_CAP_TGSI_TXQS
:
178 case PIPE_CAP_TGSI_CLOCK
:
179 case PIPE_CAP_TGSI_BALLOT
:
180 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
181 case PIPE_CAP_CLEAR_TEXTURE
:
182 case PIPE_CAP_TGSI_VOTE
:
183 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
184 case PIPE_CAP_TEXTURE_GATHER_SM5
:
185 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
186 case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS
:
187 case PIPE_CAP_LOAD_CONSTBUF
:
188 case PIPE_CAP_NIR_COMPACT_ARRAYS
:
189 case PIPE_CAP_DRAW_PARAMETERS
:
190 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
191 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
192 case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES
:
193 case PIPE_CAP_INVALIDATE_BUFFER
:
194 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
195 case PIPE_CAP_CS_DERIVED_SYSTEM_VALUES_SUPPORTED
:
196 case PIPE_CAP_TEXTURE_SHADOW_LOD
:
197 case PIPE_CAP_SHADER_SAMPLES_IDENTICAL
:
198 case PIPE_CAP_GL_SPIRV
:
199 case PIPE_CAP_GL_SPIRV_VARIABLE_POINTERS
:
200 case PIPE_CAP_DEMOTE_TO_HELPER_INVOCATION
:
201 case PIPE_CAP_NATIVE_FENCE_FD
:
202 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
204 case PIPE_CAP_FBFETCH
:
205 return BRW_MAX_DRAW_BUFFERS
;
206 case PIPE_CAP_FBFETCH_COHERENT
:
207 case PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE
:
208 case PIPE_CAP_POST_DEPTH_COVERAGE
:
209 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
210 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE
:
211 case PIPE_CAP_FRAGMENT_SHADER_INTERLOCK
:
212 case PIPE_CAP_ATOMIC_FLOAT_MINMAX
:
213 return devinfo
->gen
>= 9;
214 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
216 case PIPE_CAP_MAX_RENDER_TARGETS
:
217 return BRW_MAX_DRAW_BUFFERS
;
218 case PIPE_CAP_MAX_TEXTURE_2D_SIZE
:
220 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
221 return IRIS_MAX_MIPLEVELS
; /* 16384x16384 */
222 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
223 return 12; /* 2048x2048 */
224 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
226 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
228 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
229 return BRW_MAX_SOL_BINDINGS
/ IRIS_MAX_SOL_BUFFERS
;
230 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
231 return BRW_MAX_SOL_BINDINGS
;
232 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
233 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY
:
235 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
236 /* 3DSTATE_CONSTANT_XS requires the start of UBOs to be 32B aligned */
238 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
239 return IRIS_MAP_BUFFER_ALIGNMENT
;
240 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
241 /* Choose a cacheline (64 bytes) so that we can safely have the CPU and
242 * GPU writing the same SSBO on non-coherent systems (Atom CPUs). With
243 * UBOs, the GPU never writes, so there's no problem. For an SSBO, the
244 * GPU and the CPU can be updating disjoint regions of the buffer
245 * simultaneously and that will break if the regions overlap the same
249 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE
:
251 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
252 return 16; // XXX: u_screen says 256 is the minimum value...
253 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
255 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
256 return IRIS_MAX_TEXTURE_BUFFER_SIZE
;
257 case PIPE_CAP_MAX_VIEWPORTS
:
259 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
261 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
263 case PIPE_CAP_MAX_GS_INVOCATIONS
:
265 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
267 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
269 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
271 case PIPE_CAP_MAX_VERTEX_STREAMS
:
273 case PIPE_CAP_VENDOR_ID
:
275 case PIPE_CAP_DEVICE_ID
:
276 return screen
->pci_id
;
277 case PIPE_CAP_VIDEO_MEMORY
: {
278 /* Once a batch uses more than 75% of the maximum mappable size, we
279 * assume that there's some fragmentation, and we start doing extra
280 * flushing, etc. That's the big cliff apps will care about.
282 const unsigned gpu_mappable_megabytes
=
283 (screen
->aperture_bytes
* 3 / 4) / (1024 * 1024);
285 const long system_memory_pages
= sysconf(_SC_PHYS_PAGES
);
286 const long system_page_size
= sysconf(_SC_PAGE_SIZE
);
288 if (system_memory_pages
<= 0 || system_page_size
<= 0)
291 const uint64_t system_memory_bytes
=
292 (uint64_t) system_memory_pages
* (uint64_t) system_page_size
;
294 const unsigned system_memory_megabytes
=
295 (unsigned) (system_memory_bytes
/ (1024 * 1024));
297 return MIN2(system_memory_megabytes
, gpu_mappable_megabytes
);
299 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
300 case PIPE_CAP_MAX_VARYINGS
:
302 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
303 /* AMD_pinned_memory assumes the flexibility of using client memory
304 * for any buffer (incl. vertex buffers) which rules out the prospect
305 * of using snooped buffers, as using snooped buffers without
306 * cogniscience is likely to be detrimental to performance and require
307 * extensive checking in the driver for correctness, e.g. to prevent
308 * illegal snoop <-> snoop transfers.
310 return devinfo
->has_llc
;
311 case PIPE_CAP_THROTTLE
:
312 return screen
->driconf
.disable_throttling
? 0 : 1;
314 case PIPE_CAP_CONTEXT_PRIORITY_MASK
:
315 return PIPE_CONTEXT_PRIORITY_LOW
|
316 PIPE_CONTEXT_PRIORITY_MEDIUM
|
317 PIPE_CONTEXT_PRIORITY_HIGH
;
319 case PIPE_CAP_FRONTEND_NOOP
:
322 // XXX: don't hardcode 00:00:02.0 PCI here
323 case PIPE_CAP_PCI_GROUP
:
325 case PIPE_CAP_PCI_BUS
:
327 case PIPE_CAP_PCI_DEVICE
:
329 case PIPE_CAP_PCI_FUNCTION
:
332 case PIPE_CAP_OPENCL_INTEGER_FUNCTIONS
:
333 case PIPE_CAP_INTEGER_MULTIPLY_32X16
:
337 return u_pipe_screen_get_param_defaults(pscreen
, param
);
343 iris_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
346 case PIPE_CAPF_MAX_LINE_WIDTH
:
347 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
350 case PIPE_CAPF_MAX_POINT_WIDTH
:
351 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
354 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
356 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
358 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE
:
359 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE
:
360 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY
:
363 unreachable("unknown param");
368 iris_get_shader_param(struct pipe_screen
*pscreen
,
369 enum pipe_shader_type p_stage
,
370 enum pipe_shader_cap param
)
372 gl_shader_stage stage
= stage_from_pipe(p_stage
);
374 /* this is probably not totally correct.. but it's a start: */
376 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
377 return stage
== MESA_SHADER_FRAGMENT
? 1024 : 16384;
378 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
379 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
380 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
381 return stage
== MESA_SHADER_FRAGMENT
? 1024 : 0;
383 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
386 case PIPE_SHADER_CAP_MAX_INPUTS
:
387 return stage
== MESA_SHADER_VERTEX
? 16 : 32;
388 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
390 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
391 return 16 * 1024 * sizeof(float);
392 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
394 case PIPE_SHADER_CAP_MAX_TEMPS
:
395 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
396 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
398 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
399 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
400 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
401 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
402 /* Lie about these to avoid st/mesa's GLSL IR lowering of indirects,
403 * which we don't want. Our compiler backend will check brw_compiler's
404 * options and call nir_lower_indirect_derefs appropriately anyway.
407 case PIPE_SHADER_CAP_SUBROUTINES
:
409 case PIPE_SHADER_CAP_INTEGERS
:
411 case PIPE_SHADER_CAP_INT64_ATOMICS
:
412 case PIPE_SHADER_CAP_FP16
:
414 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
415 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
416 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
417 return IRIS_MAX_TEXTURE_SAMPLERS
;
418 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
419 return IRIS_MAX_ABOS
+ IRIS_MAX_SSBOS
;
420 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
421 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
423 case PIPE_SHADER_CAP_PREFERRED_IR
:
424 return PIPE_SHADER_IR_NIR
;
425 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
426 return 1 << PIPE_SHADER_IR_NIR
;
427 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
428 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
430 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
431 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
432 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
433 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
434 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
435 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
436 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
439 unreachable("unknown shader param");
444 iris_get_compute_param(struct pipe_screen
*pscreen
,
445 enum pipe_shader_ir ir_type
,
446 enum pipe_compute_cap param
,
449 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
450 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
452 const unsigned max_threads
= MIN2(64, devinfo
->max_cs_threads
);
453 const uint32_t max_invocations
= 32 * max_threads
;
455 #define RET(x) do { \
457 memcpy(ret, x, sizeof(x)); \
462 case PIPE_COMPUTE_CAP_ADDRESS_BITS
:
463 RET((uint32_t []){ 32 });
465 case PIPE_COMPUTE_CAP_IR_TARGET
:
470 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
471 RET((uint64_t []) { 3 });
473 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
474 RET(((uint64_t []) { 65535, 65535, 65535 }));
476 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
477 /* MaxComputeWorkGroupSize[0..2] */
478 RET(((uint64_t []) {max_invocations
, max_invocations
, max_invocations
}));
480 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
481 /* MaxComputeWorkGroupInvocations */
482 RET((uint64_t []) { max_invocations
});
484 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
485 /* MaxComputeSharedMemorySize */
486 RET((uint64_t []) { 64 * 1024 });
488 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
489 RET((uint32_t []) { 1 });
491 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE
:
492 RET((uint32_t []) { BRW_SUBGROUP_SIZE
});
494 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
495 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
496 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
497 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
498 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
:
499 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
500 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK
:
501 // XXX: I think these are for Clover...
505 unreachable("unknown compute param");
510 iris_get_timestamp(struct pipe_screen
*pscreen
)
512 struct iris_screen
*screen
= (struct iris_screen
*) pscreen
;
513 const unsigned TIMESTAMP
= 0x2358;
516 iris_reg_read(screen
->bufmgr
, TIMESTAMP
| 1, &result
);
518 result
= gen_device_info_timebase_scale(&screen
->devinfo
, result
);
519 result
&= (1ull << TIMESTAMP_BITS
) - 1;
525 iris_destroy_screen(struct pipe_screen
*pscreen
)
527 struct iris_screen
*screen
= (struct iris_screen
*) pscreen
;
528 iris_bo_unreference(screen
->workaround_bo
);
529 u_transfer_helper_destroy(pscreen
->transfer_helper
);
530 iris_bufmgr_destroy(screen
->bufmgr
);
531 disk_cache_destroy(screen
->disk_cache
);
537 iris_query_memory_info(struct pipe_screen
*pscreen
,
538 struct pipe_memory_info
*info
)
543 iris_get_compiler_options(struct pipe_screen
*pscreen
,
544 enum pipe_shader_ir ir
,
545 enum pipe_shader_type pstage
)
547 struct iris_screen
*screen
= (struct iris_screen
*) pscreen
;
548 gl_shader_stage stage
= stage_from_pipe(pstage
);
549 assert(ir
== PIPE_SHADER_IR_NIR
);
551 return screen
->compiler
->glsl_compiler_options
[stage
].NirOptions
;
554 static struct disk_cache
*
555 iris_get_disk_shader_cache(struct pipe_screen
*pscreen
)
557 struct iris_screen
*screen
= (struct iris_screen
*) pscreen
;
558 return screen
->disk_cache
;
562 iris_getparam(struct iris_screen
*screen
, int param
, int *value
)
564 struct drm_i915_getparam gp
= { .param
= param
, .value
= value
};
566 if (ioctl(screen
->fd
, DRM_IOCTL_I915_GETPARAM
, &gp
) == -1)
573 iris_getparam_integer(struct iris_screen
*screen
, int param
)
577 if (iris_getparam(screen
, param
, &value
) == 0)
583 static const struct gen_l3_config
*
584 iris_get_default_l3_config(const struct gen_device_info
*devinfo
,
587 bool wants_dc_cache
= true;
588 bool has_slm
= compute
;
589 const struct gen_l3_weights w
=
590 gen_get_default_l3_weights(devinfo
, wants_dc_cache
, has_slm
);
591 return gen_get_l3_config(devinfo
, w
);
595 iris_shader_debug_log(void *data
, const char *fmt
, ...)
597 struct pipe_debug_callback
*dbg
= data
;
601 if (!dbg
->debug_message
)
605 dbg
->debug_message(dbg
->data
, &id
, PIPE_DEBUG_TYPE_SHADER_INFO
, fmt
, args
);
610 iris_shader_perf_log(void *data
, const char *fmt
, ...)
612 struct pipe_debug_callback
*dbg
= data
;
617 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
619 va_copy(args_copy
, args
);
620 vfprintf(stderr
, fmt
, args_copy
);
624 if (dbg
->debug_message
) {
625 dbg
->debug_message(dbg
->data
, &id
, PIPE_DEBUG_TYPE_PERF_INFO
, fmt
, args
);
632 iris_screen_create(int fd
, const struct pipe_screen_config
*config
)
634 struct iris_screen
*screen
= rzalloc(NULL
, struct iris_screen
);
640 if (!gen_get_device_info_from_fd(fd
, &screen
->devinfo
))
642 screen
->pci_id
= screen
->devinfo
.chipset_id
;
643 screen
->no_hw
= screen
->devinfo
.no_hw
;
645 if (screen
->devinfo
.gen
< 8 || screen
->devinfo
.is_cherryview
)
648 screen
->aperture_bytes
= get_aperture_size(fd
);
650 if (getenv("INTEL_NO_HW") != NULL
)
651 screen
->no_hw
= true;
653 bool bo_reuse
= false;
654 int bo_reuse_mode
= driQueryOptioni(config
->options
, "bo_reuse");
655 switch (bo_reuse_mode
) {
656 case DRI_CONF_BO_REUSE_DISABLED
:
658 case DRI_CONF_BO_REUSE_ALL
:
663 screen
->bufmgr
= iris_bufmgr_init(&screen
->devinfo
, fd
, bo_reuse
);
667 screen
->workaround_bo
=
668 iris_bo_alloc(screen
->bufmgr
, "workaround", 4096, IRIS_MEMZONE_OTHER
);
669 if (!screen
->workaround_bo
)
672 brw_process_intel_debug_variable();
674 screen
->driconf
.dual_color_blend_by_location
=
675 driQueryOptionb(config
->options
, "dual_color_blend_by_location");
676 screen
->driconf
.disable_throttling
=
677 driQueryOptionb(config
->options
, "disable_throttling");
678 screen
->driconf
.always_flush_cache
=
679 driQueryOptionb(config
->options
, "always_flush_cache");
681 screen
->precompile
= env_var_as_boolean("shader_precompile", true);
683 isl_device_init(&screen
->isl_dev
, &screen
->devinfo
, false);
685 screen
->compiler
= brw_compiler_create(screen
, &screen
->devinfo
);
686 screen
->compiler
->shader_debug_log
= iris_shader_debug_log
;
687 screen
->compiler
->shader_perf_log
= iris_shader_perf_log
;
688 screen
->compiler
->supports_pull_constants
= false;
689 screen
->compiler
->supports_shader_constants
= true;
690 screen
->compiler
->compact_params
= false;
692 screen
->l3_config_3d
= iris_get_default_l3_config(&screen
->devinfo
, false);
693 screen
->l3_config_cs
= iris_get_default_l3_config(&screen
->devinfo
, true);
695 iris_disk_cache_init(screen
);
697 slab_create_parent(&screen
->transfer_pool
,
698 sizeof(struct iris_transfer
), 64);
700 screen
->subslice_total
=
701 iris_getparam_integer(screen
, I915_PARAM_SUBSLICE_TOTAL
);
702 assert(screen
->subslice_total
>= 1);
704 struct pipe_screen
*pscreen
= &screen
->base
;
706 iris_init_screen_fence_functions(pscreen
);
707 iris_init_screen_resource_functions(pscreen
);
709 pscreen
->destroy
= iris_destroy_screen
;
710 pscreen
->get_name
= iris_get_name
;
711 pscreen
->get_vendor
= iris_get_vendor
;
712 pscreen
->get_device_vendor
= iris_get_device_vendor
;
713 pscreen
->get_param
= iris_get_param
;
714 pscreen
->get_shader_param
= iris_get_shader_param
;
715 pscreen
->get_compute_param
= iris_get_compute_param
;
716 pscreen
->get_paramf
= iris_get_paramf
;
717 pscreen
->get_compiler_options
= iris_get_compiler_options
;
718 pscreen
->get_disk_shader_cache
= iris_get_disk_shader_cache
;
719 pscreen
->is_format_supported
= iris_is_format_supported
;
720 pscreen
->context_create
= iris_create_context
;
721 pscreen
->flush_frontbuffer
= iris_flush_frontbuffer
;
722 pscreen
->get_timestamp
= iris_get_timestamp
;
723 pscreen
->query_memory_info
= iris_query_memory_info
;
724 pscreen
->get_driver_query_group_info
= iris_get_monitor_group_info
;
725 pscreen
->get_driver_query_info
= iris_get_monitor_info
;